Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962992
R. Bachrach, M. Pool, K. Genovese, J.C. Moran, M. O'Halloran, T. J. Connolly
A semiconductor fabricator is a highly complex system that hosts the process tools capable of manufacturing IC product devices based upon their process flows. A typical process flow for a 0.15 /spl mu/m logic process consists of 300 to 400 steps with 22 to 24 mask steps. A variety of equipment sets and organizational architectures are possible for any process flow. The results of a comparative analysis of two such 300 mm FAB architectures are presented in this report. The impact of equipment sets on fab Sizing, Cost, and Performance are described as a function of operating characteristics.
{"title":"Comparative analysis of 300 mm FAB architectures impact of equipment sets on wafer cost and dynamic performance","authors":"R. Bachrach, M. Pool, K. Genovese, J.C. Moran, M. O'Halloran, T. J. Connolly","doi":"10.1109/ISSM.2001.962992","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962992","url":null,"abstract":"A semiconductor fabricator is a highly complex system that hosts the process tools capable of manufacturing IC product devices based upon their process flows. A typical process flow for a 0.15 /spl mu/m logic process consists of 300 to 400 steps with 22 to 24 mask steps. A variety of equipment sets and organizational architectures are possible for any process flow. The results of a comparative analysis of two such 300 mm FAB architectures are presented in this report. The impact of equipment sets on fab Sizing, Cost, and Performance are described as a function of operating characteristics.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963003
R. Noben, R. van Driel, T. Claasen-Vujcic
In order to improve cycle time in the furnace area, two alternatives are evaluated. Mini batch manufacturing and integrated metrology can both save valuable time. Dynamic simulations are used to investigate the influence of both options. The results are a cycle time improvement when going front large batch to mini batch manufacturing. The gain is up to 40% for normal lots and up to 30% for hot lots wafers. The consequence is an increase in the number of required tubes. Cycle time improvement versus costs is analysed. The cost of one hour cycle time gain is determined. Integrated metrology can save approximately 5-10% on the average cycle time.
{"title":"Cycle time advantages of mini batch manufacturing and integrated metrology in a 300 mm vertical furnace","authors":"R. Noben, R. van Driel, T. Claasen-Vujcic","doi":"10.1109/ISSM.2001.963003","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963003","url":null,"abstract":"In order to improve cycle time in the furnace area, two alternatives are evaluated. Mini batch manufacturing and integrated metrology can both save valuable time. Dynamic simulations are used to investigate the influence of both options. The results are a cycle time improvement when going front large batch to mini batch manufacturing. The gain is up to 40% for normal lots and up to 30% for hot lots wafers. The consequence is an increase in the number of required tubes. Cycle time improvement versus costs is analysed. The cost of one hour cycle time gain is determined. Integrated metrology can save approximately 5-10% on the average cycle time.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121210171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963015
S. Yajima, T. Nakano, K. Sadachi, Y. Ikura, H. Miura, A. Tomozawa
During the drastic product change from memory devices to discrete devices, we have made various technical improvements in photolithography processing corresponding to its design characteristics, as follows: (1) establishment of fine gate processing technology; (2) optimization of throughput and processing accuracy using new photoresist processing customized for each step; and (3) establishment of flexible stepper application methods aimed at products-change-free production. Consequently, we have obtained the following beneficial results: (1) processing of 0.25 /spl mu/m discrete devices has been set up without KrF lithography; (2) a 198% improvement in stepper throughput has been achieved; and (3) a 58% reduction of waiting time has been obtained.
{"title":"Throughput improvement in photolithography processing for flexible production","authors":"S. Yajima, T. Nakano, K. Sadachi, Y. Ikura, H. Miura, A. Tomozawa","doi":"10.1109/ISSM.2001.963015","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963015","url":null,"abstract":"During the drastic product change from memory devices to discrete devices, we have made various technical improvements in photolithography processing corresponding to its design characteristics, as follows: (1) establishment of fine gate processing technology; (2) optimization of throughput and processing accuracy using new photoresist processing customized for each step; and (3) establishment of flexible stepper application methods aimed at products-change-free production. Consequently, we have obtained the following beneficial results: (1) processing of 0.25 /spl mu/m discrete devices has been set up without KrF lithography; (2) a 198% improvement in stepper throughput has been achieved; and (3) a 58% reduction of waiting time has been obtained.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962995
M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda
Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.
{"title":"Floor layout planning method based on self-organization","authors":"M. Kobayashi, T. Makita, S. Matsui, M. Koyama, N. Fujii, I. Hatono, K. Ueda","doi":"10.1109/ISSM.2001.962995","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962995","url":null,"abstract":"Floor layout to realize short accumulated distance of product and high throughput is required. Currently, however, it is very difficult and takes a very long time to optimize floor planning in a wafer process, because of complex process flow. In this paper we propose a new method of floor planning based on self-organization to solve these problems. We verify the validity of applying this method to semiconductor manufacturing. Self-organization method can generate a floor layout plan autonomously. In particular, potential field modeling method can describe simulation models in a simple way, because it controls all entities in the same method. The results of simulation indicate that the proposed method can provide the layout plan with short accumulated distance of product without requiring considerable labor and time.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128596919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962913
A. Imai, R. Miyamoto, K. Ozawa
This paper introduces a way to build a system that supports maintenance work in the most suitable and efficient way for future semiconductor factories with changing technologies. This system not only has improved the working efficiency of a maintenance section greatly, but practical use of the proposed system attained a greater rate of equipment availability, and improvement in maintenance costs. For future growth of the semiconductor industry, greater cooperation between the semiconductor manufacturer, components maker, and equipment maker will be indispensable. We wish to promote cooperation for improvement in the equipment operation rate, including the formation of data sharing schemes using Internet technology and an intranet between semiconductor manufacturer, equipment maker, and material supplier, and common analysis, and the practical use of existing data for a new line with the assistance of this system.
{"title":"Universal architecture to improve equipment maintenance work","authors":"A. Imai, R. Miyamoto, K. Ozawa","doi":"10.1109/ISSM.2001.962913","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962913","url":null,"abstract":"This paper introduces a way to build a system that supports maintenance work in the most suitable and efficient way for future semiconductor factories with changing technologies. This system not only has improved the working efficiency of a maintenance section greatly, but practical use of the proposed system attained a greater rate of equipment availability, and improvement in maintenance costs. For future growth of the semiconductor industry, greater cooperation between the semiconductor manufacturer, components maker, and equipment maker will be indispensable. We wish to promote cooperation for improvement in the equipment operation rate, including the formation of data sharing schemes using Internet technology and an intranet between semiconductor manufacturer, equipment maker, and material supplier, and common analysis, and the practical use of existing data for a new line with the assistance of this system.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125515747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963017
K. Maruo, Y. Maeda, M. Niwano
This paper presents a high-sensitivity organic contaminants detection method for clean room air. Using a Fourier Transform Infra-Red spectroscopy (FTIR), we can detect various chemical compounds including organic contaminants in a few minutes. In addition, by combining two efficient methods: Multiple Internal Reflection (MIR) and Cold Trap (CT), the sensitivity rate of detection chemical compounds rises drastically. By conducting experiments, it has been demonstrated that this sensitivity rate reaches to the order of ppb. This method will be used as an integral part of clean room air monitoring systems.
{"title":"High-sensitive organic contaminants detecting method based on cold-trap and multiple-internal-reflection FTIR [clean room air monitoring systems]","authors":"K. Maruo, Y. Maeda, M. Niwano","doi":"10.1109/ISSM.2001.963017","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963017","url":null,"abstract":"This paper presents a high-sensitivity organic contaminants detection method for clean room air. Using a Fourier Transform Infra-Red spectroscopy (FTIR), we can detect various chemical compounds including organic contaminants in a few minutes. In addition, by combining two efficient methods: Multiple Internal Reflection (MIR) and Cold Trap (CT), the sensitivity rate of detection chemical compounds rises drastically. By conducting experiments, it has been demonstrated that this sensitivity rate reaches to the order of ppb. This method will be used as an integral part of clean room air monitoring systems.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122052212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.963004
Kye-Weon Kim, Yusin Yang, Chung Sam Chun, Sang Mun Chun, Dong Chun Lee, Sun-Yong Choi, S. Choi, Sung Jin Park
In CMP(Chemical Mechanical Polishing) process, if there are defects on the polishing pad, scratches are generated on the surface of the semiconductor wafer. We developed the inspection system of defects on the chemical mechanical polishing pad. The system uses a white light source and a CCD camera in order to inspect defects. We use the threshold method in order to find defects from images captured by the CCD camera, and the system can sort defects by size.
{"title":"Development of the inspection system of defects on a CMP (Chemical Mechanical Polishing) pad","authors":"Kye-Weon Kim, Yusin Yang, Chung Sam Chun, Sang Mun Chun, Dong Chun Lee, Sun-Yong Choi, S. Choi, Sung Jin Park","doi":"10.1109/ISSM.2001.963004","DOIUrl":"https://doi.org/10.1109/ISSM.2001.963004","url":null,"abstract":"In CMP(Chemical Mechanical Polishing) process, if there are defects on the polishing pad, scratches are generated on the surface of the semiconductor wafer. We developed the inspection system of defects on the chemical mechanical polishing pad. The system uses a white light source and a CCD camera in order to inspect defects. We use the threshold method in order to find defects from images captured by the CCD camera, and the system can sort defects by size.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"67 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122543716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962947
K. Lensing, R. Markle, B. Stirton, M. Laughery
Focuses on the current roles of metrology systems associated with a shallow trench isolation (STI) run-to-run (RtR) controller and recent advances AMD has made applying new, ODP scatterometry-based metrology to this application. It will compare industry standard metrology techniques to ODP, with the objective of identifying the STI metrology system or systems that will produce timely and reliable data streams with the largest quantity of process information at the highest possible signal to noise (S/N) ratio.
{"title":"Shallow trench isolation scatterometry metrology in a high volume fab","authors":"K. Lensing, R. Markle, B. Stirton, M. Laughery","doi":"10.1109/ISSM.2001.962947","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962947","url":null,"abstract":"Focuses on the current roles of metrology systems associated with a shallow trench isolation (STI) run-to-run (RtR) controller and recent advances AMD has made applying new, ODP scatterometry-based metrology to this application. It will compare industry standard metrology techniques to ODP, with the objective of identifying the STI metrology system or systems that will produce timely and reliable data streams with the largest quantity of process information at the highest possible signal to noise (S/N) ratio.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124098414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962976
Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho
Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.
{"title":"A study on ILD process of simple and CMP skip using polysilazane-based SOG","authors":"Jung-Ho Lee, Jung-Sik Choi, Dong-jun Lee, S. Chon, S. Hwang, Sang-Deog Cho","doi":"10.1109/ISSM.2001.962976","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962976","url":null,"abstract":"Unit process conditions including coating and baking were optimized to use polysilazane-based spin on glass(SZ-SOG) which has excellent gap filling and planarization ability in an inter layer dielectric (ILD) layer, and this material was successfully and simply integrated for the first time in an ILD layer of a logic device without an expensive chemical mechanical polishing (CMP) process. Device characteristics showed that breakdown voltage and transistor threshold voltage of devices with SZ-SOG in the ILD layer are comparable with those with the conventional borophosphosilicate glass (BPSG). Also, the yield results showed that SZ-SOG group without CMP is similar to BPSG group with CMP. SZ-SOG has no reliability problems even up to 1000 hr.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132844684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-10-08DOI: 10.1109/ISSM.2001.962985
J. Bernstein, Joohan Lee
Some applications are presented for implementing a novel laser-programmable interconnect element (MakeLink/sup TM/) formed vertically between two standard metallization layers. The average electrical resistance for the smallest link is less than 10/spl Omega/ at optimal laser energy. Life tests under accelerating DC current densities and temperatures indicated high electromigration reliability. This technology is shown to be scaleable down to 1.5 /spl mu/m pitch based on commercially available laser systems. Finite element models of various structures were simulated and the results show that there exists an acceptable process window for any scaled link. Properties such as standard CMOS process compatibility, no programming circuit, high current handling capability, hermeticity and radiation hardness, make it useful in customizable devices and to replace laser fuses for yield enhancement and other rapid customization applications.
{"title":"A laser formed MakeLink* for customization and repair","authors":"J. Bernstein, Joohan Lee","doi":"10.1109/ISSM.2001.962985","DOIUrl":"https://doi.org/10.1109/ISSM.2001.962985","url":null,"abstract":"Some applications are presented for implementing a novel laser-programmable interconnect element (MakeLink/sup TM/) formed vertically between two standard metallization layers. The average electrical resistance for the smallest link is less than 10/spl Omega/ at optimal laser energy. Life tests under accelerating DC current densities and temperatures indicated high electromigration reliability. This technology is shown to be scaleable down to 1.5 /spl mu/m pitch based on commercially available laser systems. Finite element models of various structures were simulated and the results show that there exists an acceptable process window for any scaled link. Properties such as standard CMOS process compatibility, no programming circuit, high current handling capability, hermeticity and radiation hardness, make it useful in customizable devices and to replace laser fuses for yield enhancement and other rapid customization applications.","PeriodicalId":356225,"journal":{"name":"2001 IEEE International Symposium on Semiconductor Manufacturing. ISSM 2001. Conference Proceedings (Cat. No.01CH37203)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126380276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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