Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114506
Kun-Han Tsai, J. Rajski
This paper proposes an integration method between DFT and ATPG to improve the pattern compression by pulsing interactive clocks (PIC) simultaneously. The proposed algorithm can accurately mask the unreliable cross clock domain transitions for any clock skews. In addition, it identifies the required flops to be inserted hold paths, and combined with ATPG to reduce the pattern count by up to 39% without compromising the test quality.
{"title":"Clock-domain-aware test for improving pattern compression","authors":"Kun-Han Tsai, J. Rajski","doi":"10.1109/VLSI-DAT.2015.7114506","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114506","url":null,"abstract":"This paper proposes an integration method between DFT and ATPG to improve the pattern compression by pulsing interactive clocks (PIC) simultaneously. The proposed algorithm can accurately mask the unreliable cross clock domain transitions for any clock skews. In addition, it identifies the required flops to be inserted hold paths, and combined with ATPG to reduce the pattern count by up to 39% without compromising the test quality.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130269707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114511
Jheng-Jhan He, Chih-Peng Fan
The K-Best algorithm for MIMO detections has been widely used in wireless communication systems. In this paper, to increase the throughput cost-effectively, two novel computational schemes are applied to design the K-Best detector. To reduce the number of visiting leaf nodes, we propose the pre-screening based enumeration, and almost half of leaf nodes are reduced for fast searches. To reduce the complexity of the sorting scheme, we apply the simplified Batcher's odd-even sorting algorithm (SBOESA) without sorting all outputs, and the required comparators are reduced through the simplified fast sorting design. The proposed 4×4 MIMO K-Best detector at 64QAM is implemented by TSMC 90nm process. The throughput of the proposed MIMO detector achieves up to 4.4Gbps. Compared with other designs, the proposed K-Best detector provides larger throughputs and performs superior hardware efficiency.
MIMO检测的K-Best算法在无线通信系统中得到了广泛应用。为了经济有效地提高吞吐量，本文采用了两种新的计算方案来设计K-Best检测器。为了减少访问叶节点的数量，我们提出了基于预筛选的枚举，几乎减少了一半的叶节点以实现快速搜索。为了降低排序方案的复杂性，我们采用简化的Batcher的奇偶排序算法(SBOESA)，不对所有输出进行排序，并通过简化的快速排序设计减少了所需的比较器。提出的4×4 MIMO K-Best 64QAM探测器采用台积电90nm工艺实现。所提出的MIMO检测器的吞吐量可达4.4Gbps。与其他设计相比，所提出的K-Best检测器提供了更大的吞吐量和更好的硬件效率。
{"title":"Design and VLSI implementation of novel pre-screening and simplified sorting based K-best detection for MIMO systems","authors":"Jheng-Jhan He, Chih-Peng Fan","doi":"10.1109/VLSI-DAT.2015.7114511","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114511","url":null,"abstract":"The K-Best algorithm for MIMO detections has been widely used in wireless communication systems. In this paper, to increase the throughput cost-effectively, two novel computational schemes are applied to design the K-Best detector. To reduce the number of visiting leaf nodes, we propose the pre-screening based enumeration, and almost half of leaf nodes are reduced for fast searches. To reduce the complexity of the sorting scheme, we apply the simplified Batcher's odd-even sorting algorithm (SBOESA) without sorting all outputs, and the required comparators are reduced through the simplified fast sorting design. The proposed 4×4 MIMO K-Best detector at 64QAM is implemented by TSMC 90nm process. The throughput of the proposed MIMO detector achieves up to 4.4Gbps. Compared with other designs, the proposed K-Best detector provides larger throughputs and performs superior hardware efficiency.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"76 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127182331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114499
Yanfeng Li, Yutao Liu, W. Rhee, Zhihua Wang
This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.
{"title":"A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator","authors":"Yanfeng Li, Yutao Liu, W. Rhee, Zhihua Wang","doi":"10.1109/VLSI-DAT.2015.7114499","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114499","url":null,"abstract":"This paper describes a PSRR enhancing method for the all-digital phase-locked loop (ADPLL) by utilizing a self-regulated gated ring-oscillator (SR-GRO) time-to-digital converter (TDC) and a voltage regulator just for a digitally-controlled oscillator (DCO). The SR-GRO employs a replica supply noise monitoring circuit which tracks supply noise and enables feed-forward error cancellation over broad spectrum. A prototype ADPLL implemented in 65nm CMOS achieves >25dB PSRR when 100mVpp 1MHz supply noise is injected to both the TDC and the DCO. Experimental results show that the SR-GRO TDC can also suppress the supply coupling induced phase noise.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"59 S1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120846210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114555
Carl Engblom
Summary form only given. It is increasingly clear that performance and capacity improvements predicated on Moore's law will not be sufficient to meet projected overall capacity demands in a networked society - in fact more than Moore will be needed. One way to meet these demands is enabled by 2.5D and 3D integration on chip-level. In this note we discuss technical and financial drivers of 2.5/3D from a system integration perspective. Further trends and different approaches in this field are discussed with pros and cons as well with technical and business model challenges. The note also touches on how these integration techniques can be even further strengthened when combined with on-chip or “near-chip” integration of photonics. This combination seems to have the potential to deliver technologies that can meet future capacity and performance requirements given other technical constraints e.g. power consumption.
{"title":"Drivers and aspects of 2.5/3D integration as a potential game-changer","authors":"Carl Engblom","doi":"10.1109/VLSI-DAT.2015.7114555","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114555","url":null,"abstract":"Summary form only given. It is increasingly clear that performance and capacity improvements predicated on Moore's law will not be sufficient to meet projected overall capacity demands in a networked society - in fact more than Moore will be needed. One way to meet these demands is enabled by 2.5D and 3D integration on chip-level. In this note we discuss technical and financial drivers of 2.5/3D from a system integration perspective. Further trends and different approaches in this field are discussed with pros and cons as well with technical and business model challenges. The note also touches on how these integration techniques can be even further strengthened when combined with on-chip or “near-chip” integration of photonics. This combination seems to have the potential to deliver technologies that can meet future capacity and performance requirements given other technical constraints e.g. power consumption.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114508
Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen
To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.
{"title":"System-level test coverage prediction by structural stress test data mining","authors":"Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen","doi":"10.1109/VLSI-DAT.2015.7114508","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114508","url":null,"abstract":"To achieve high quality of silicon ICs, system-level test (SLT) can be performed after regular final test. This is important for chips manufactured in advanced technologies, as systematic failures are getting harder to detect by conventional structural tests. However, due to long test time and extra human efforts, the cost for SLT is high. A possible way to replace SLT without quality loss is to identify SLT failure suspects with stress tests. In this work, we apply 60,000 structural stress test patterns to the CPU blocks of a real SOC product, using 20 stressed voltage-frequency corners. We try to identify the correlation between the stress test data and SLT-pass/fail results of the CPU blocks. By the proposed differential feature-based methodology, 32 outliers are identified, which are assumed to be CPU-fail chips. Because of the lack of exact CPU-fail chip IDs for verification, the identified chip IDs are compared with the IDs identified from previous works, which use the same data but different machine-learning features and method for the same purpose. After comparison, 30 out of a total of 33 CPU-fail suspects matched. Although this does not immediately imply that the SLT can be replaced by the structural stress tests, it shows more evidence that test data mining can be further explored for test time reduction and/or quality improvement.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114542
M. Takamiya
Energy autonomy enabled by the energy efficient design and the energy harvesting is the one of the top requirements for maintenance-free IoT sensor nodes and wearable/implanted devices. In this paper, energy efficient ultra-low voltage (<; 0.5V) circuits are shown. Energy autonomous wearable healthcare devices using the flexible, large-area, and distributed organic electronics are also shown.
{"title":"Energy efficient design and energy harvesting for energy autonomous systems","authors":"M. Takamiya","doi":"10.1109/VLSI-DAT.2015.7114542","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114542","url":null,"abstract":"Energy autonomy enabled by the energy efficient design and the energy harvesting is the one of the top requirements for maintenance-free IoT sensor nodes and wearable/implanted devices. In this paper, energy efficient ultra-low voltage (<; 0.5V) circuits are shown. Energy autonomous wearable healthcare devices using the flexible, large-area, and distributed organic electronics are also shown.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131387163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multi-threaded programmable shader pipeline 3D graphics SoC with support for OpenGL ES 2.0 has been developed and fabricated. The sample chip is ARMv4T compatible with the 3D processing capability of 14.9 Mvertices/s, 3.6 Mpixels/s and up to 4K resolution. The die size is 3.85×3.85 mm2, with 2.96M gates on a TSMC 90nm CMOS 1P9M. This new SoC includes software to support OpenGL ES API libraries, GLSL compilation and simulation. The SoC also comes with various development tools, including GPU simulators for hardware validation, profile assisted compiler optimization and compiler verification. For developers, we also present a QEMU-based simulation platform and SoC Performance Monitoring Tool Suite (PMTS) to assist developers in optimizing the system and detecting performance bottlenecks.
开发并制作了一个支持OpenGL ES 2.0的多线程可编程着色器管道3D图形SoC。该样品芯片兼容ARMv4T，具有14.9 m顶点/s, 360万像素/s和高达4K分辨率的3D处理能力。芯片尺寸为3.85×3.85 mm2，在台积电90nm CMOS 1P9M上具有2.96M栅极。这个新的SoC包括支持OpenGL ES API库、GLSL编译和仿真的软件。SoC还配备了各种开发工具，包括用于硬件验证的GPU模拟器，配置文件辅助编译器优化和编译器验证。对于开发人员，我们还提供了一个基于qemu的仿真平台和SoC性能监控工具套件(PMTS)，以帮助开发人员优化系统并检测性能瓶颈。
{"title":"An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support","authors":"Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, K. Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, S.W. Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee","doi":"10.1109/VLSI-DAT.2015.7114496","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114496","url":null,"abstract":"A multi-threaded programmable shader pipeline 3D graphics SoC with support for OpenGL ES 2.0 has been developed and fabricated. The sample chip is ARMv4T compatible with the 3D processing capability of 14.9 Mvertices/s, 3.6 Mpixels/s and up to 4K resolution. The die size is 3.85×3.85 mm2, with 2.96M gates on a TSMC 90nm CMOS 1P9M. This new SoC includes software to support OpenGL ES API libraries, GLSL compilation and simulation. The SoC also comes with various development tools, including GPU simulators for hardware validation, profile assisted compiler optimization and compiler verification. For developers, we also present a QEMU-based simulation platform and SoC Performance Monitoring Tool Suite (PMTS) to assist developers in optimizing the system and detecting performance bottlenecks.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131763260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114546
A. Kifli, Kun-Cheng Wu
Most of the ASIC designs that we currently encountered are SoC in nature. The success of SoC design methodology relies on the design reuse of existing cores (IPs). The tasks of integrating the cores and creating successful tests for the SoC should not be overlooked. These tasks may need a considerable amount of time from the designers and are inherently error-prone. Conventionally, designers have to understand the test requirement of all the IPs used in the SoC. A test plan is then created and the corresponding test wrapper for the IPs is added and integrated into the SoC design. Besides IPs test integration, designers typically need to plan for the scan DfT, test compression, test wrapper, memory BIST, and boundary scan. The above tasks are pretty standard, yet they are tedious and error-prone.
{"title":"SoC test integration platform","authors":"A. Kifli, Kun-Cheng Wu","doi":"10.1109/VLSI-DAT.2015.7114546","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114546","url":null,"abstract":"Most of the ASIC designs that we currently encountered are SoC in nature. The success of SoC design methodology relies on the design reuse of existing cores (IPs). The tasks of integrating the cores and creating successful tests for the SoC should not be overlooked. These tasks may need a considerable amount of time from the designers and are inherently error-prone. Conventionally, designers have to understand the test requirement of all the IPs used in the SoC. A test plan is then created and the corresponding test wrapper for the IPs is added and integrated into the SoC design. Besides IPs test integration, designers typically need to plan for the scan DfT, test compression, test wrapper, memory BIST, and boundary scan. The above tasks are pretty standard, yet they are tedious and error-prone.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116901745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114505
L. Chiou, L. Lu, Chieh-Yu Lin
Three-dimensional integrated circuits are expected to face increasingly severe thermal challenges and cost issues as the number of stacked ICs increases. Thermal analysis for 3D ICs is urgently required to assist system designers at the early phase of design to identify hot zones. Most thermal analyses obtain detailed temperature distribution by large matrix operations, and hence reduce analysis performance. Accordingly, we propose a compressed and combined sparse row (CCSR) matrix format to be used in the proposed effective matrix compression (EMC) method for matrix multiplication on GPU. The experimental results show EMC using CCSR is on average 44.93 times faster than matrix multiplication without any special compression format and on average at least 3.09 times faster than other compression formats.
{"title":"An effective matrix compression method for GPU-accelerated thermal analysis","authors":"L. Chiou, L. Lu, Chieh-Yu Lin","doi":"10.1109/VLSI-DAT.2015.7114505","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114505","url":null,"abstract":"Three-dimensional integrated circuits are expected to face increasingly severe thermal challenges and cost issues as the number of stacked ICs increases. Thermal analysis for 3D ICs is urgently required to assist system designers at the early phase of design to identify hot zones. Most thermal analyses obtain detailed temperature distribution by large matrix operations, and hence reduce analysis performance. Accordingly, we propose a compressed and combined sparse row (CCSR) matrix format to be used in the proposed effective matrix compression (EMC) method for matrix multiplication on GPU. The experimental results show EMC using CCSR is on average 44.93 times faster than matrix multiplication without any special compression format and on average at least 3.09 times faster than other compression formats.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124256523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114510
Hang Yu, Xinyuan Qian, M. Guo, Shoushun Chen, K. Low
This paper presents an online deblurring (ODB) algorithm for time delay integration (TDI) CMOS image sensor (CIS) used in small remote imaging systems, where image quality is degraded due to vibration caused by different factors. The ODB algorithm can detect and compensate the image shift so as to produce sharp TDI images. A 256×8-pixel prototype chip was fabricated using a 0.18μm CIS technology, which contains 8 TDI stages, column-parallel TDI accumulation and online deblurring circuits. The 4-transistor active pixel sensor (4T-APS) is applied, with the pixel size of 6.5μm×6.5μm and the fill factor of 28%.
{"title":"A time delay integration CMOS image sensor with online deblurring algorithm","authors":"Hang Yu, Xinyuan Qian, M. Guo, Shoushun Chen, K. Low","doi":"10.1109/VLSI-DAT.2015.7114510","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114510","url":null,"abstract":"This paper presents an online deblurring (ODB) algorithm for time delay integration (TDI) CMOS image sensor (CIS) used in small remote imaging systems, where image quality is degraded due to vibration caused by different factors. The ODB algorithm can detect and compensate the image shift so as to produce sharp TDI images. A 256×8-pixel prototype chip was fabricated using a 0.18μm CIS technology, which contains 8 TDI stages, column-parallel TDI accumulation and online deblurring circuits. The 4-transistor active pixel sensor (4T-APS) is applied, with the pixel size of 6.5μm×6.5μm and the fill factor of 28%.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121437524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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