Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114513
Jing-Shiun Lin, Ming-Der Shieh, Chungguang Liu, Der-Wei Yang
Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.
{"title":"Efficient highly-parallel turbo decoder for 3GPP LTE-Advanced","authors":"Jing-Shiun Lin, Ming-Der Shieh, Chungguang Liu, Der-Wei Yang","doi":"10.1109/VLSI-DAT.2015.7114513","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114513","url":null,"abstract":"Turbo codes have been widely adopted in latest wireless communication systems due to their excellent error correction capability. In 3GPP LTE-Advanced systems, a peak data rate of up to 1 Gbps should be satisfied. To meet this throughput requirement, several turbo decoding algorithms aimed at achieving highly parallel architecture have been investigated. However, the resulting hardware cost of turbo decoders is increased considerably with increasing parallelism. This paper presents a modified parallel-window decoding algorithm to reduce the warm-up computation ratio per each decoding window. In addition, a dual-mode computing schedule is proposed to support the requirement of various code rates and block lengths. Experimental results reveal that the proposed design, implemented in the TSMC 90-nm CMOS process, can achieve the highest throughput rate of 1.45 Gbps and improve the normalized area efficiency by about 24.53% compared to the existing 3GPP-LTE-Advanced turbo decoders.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"8 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115606077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114548
Chao-Wen Tzeng, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao
Using speed sensor to find out the unexpected process variation and design performance degradation is getting more and more attention. In this paper, we demonstrate the industrial case of identifying process variation, with the power of in-house developed DSS (Digital Speed Sensor). The identification result is validated by TEM (Transmission Electron Microscopy). In addition, by using DSS, we can observe how the test environment results in design performance degradation, not only during the CP (Circuit Probe) test but also the board-level test.
{"title":"Case study of process and design performance debugging with Digital Speed Sensor","authors":"Chao-Wen Tzeng, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao","doi":"10.1109/VLSI-DAT.2015.7114548","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114548","url":null,"abstract":"Using speed sensor to find out the unexpected process variation and design performance degradation is getting more and more attention. In this paper, we demonstrate the industrial case of identifying process variation, with the power of in-house developed DSS (Digital Speed Sensor). The identification result is validated by TEM (Transmission Electron Microscopy). In addition, by using DSS, we can observe how the test environment results in design performance degradation, not only during the CP (Circuit Probe) test but also the board-level test.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122899997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114514
Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, C. Chuang, Yuan-Hua Chu, W. Hwang
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.
{"title":"All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction","authors":"Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, C. Chuang, Yuan-Hua Chu, W. Hwang","doi":"10.1109/VLSI-DAT.2015.7114514","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114514","url":null,"abstract":"In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114543
Y. Yang
Summary form only given. This talk presents two hydrogel-based devices: a microgripper that can be wirelessly manipulated using magnetic fields, and a passive inertial switch using MWCNT-hydrogel composite integrated with an inductor/capacitor (L-C) resonator. The proposed microgripper can move freely in liquids when driven by direct current (dc) magnetic fields, and perform a gripping motion by using alternating current (ac) magnetic fields. The device is fabricated from a biocompatible hydrogel material that can be employed for intravascular applications. The actuation mechanism for gripping motions is realized by controlling the exposure dose on the hydrogel composite during the lithography process. The preliminary characterization of the device is also presented. The measurement results show that the gripping motion reached a full stroke at approximately 38 oC. By dispersing multiwall carbon nanotubes (MWCNT) into the material, the overall response time of the gripping motion decreases by approximately 2-fold. Device manipulations such as the gripping motion, translational motion, and rotational motion are also successfully demonstrated on a polyvinyl chloride (PVC) tube and in a polydimethylsiloxane (PDMS) microfluidic channel. The passive inertial switch consists of a PDMS micro-fluidic chip containing MWCNT-hydrogel composite and water droplet, and a glass substrate with a capacitor plate and an inductor coil. When the acceleration exceeds the designed threshold-level, the water passes through the channel to the hydrogel cavity. The hydrogel swells and changes the capacitance of the integrated L-C resonator, which in turn changes the resonant frequency that can be remotely detected. Each sensor unit does not require on-board power and circuitry for operation, so the proposed device is disposable, and is suitable for low-cost applications. All PDMS structures were fabricated using soft lithography. The L-C resonator was fabricated using a lift-off process to pattern metal layers on a glass substrate. The threshold g-values, which differ for various applications, were strongly affected by the channel widths. The phase-dip measurement shows that the resonant frequencies shift from 164 MHz to approximately 148 MHz when the device is activated by acceleration.
{"title":"Hydrogel-based microdevices","authors":"Y. Yang","doi":"10.1109/VLSI-DAT.2015.7114543","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114543","url":null,"abstract":"Summary form only given. This talk presents two hydrogel-based devices: a microgripper that can be wirelessly manipulated using magnetic fields, and a passive inertial switch using MWCNT-hydrogel composite integrated with an inductor/capacitor (L-C) resonator. The proposed microgripper can move freely in liquids when driven by direct current (dc) magnetic fields, and perform a gripping motion by using alternating current (ac) magnetic fields. The device is fabricated from a biocompatible hydrogel material that can be employed for intravascular applications. The actuation mechanism for gripping motions is realized by controlling the exposure dose on the hydrogel composite during the lithography process. The preliminary characterization of the device is also presented. The measurement results show that the gripping motion reached a full stroke at approximately 38 oC. By dispersing multiwall carbon nanotubes (MWCNT) into the material, the overall response time of the gripping motion decreases by approximately 2-fold. Device manipulations such as the gripping motion, translational motion, and rotational motion are also successfully demonstrated on a polyvinyl chloride (PVC) tube and in a polydimethylsiloxane (PDMS) microfluidic channel. The passive inertial switch consists of a PDMS micro-fluidic chip containing MWCNT-hydrogel composite and water droplet, and a glass substrate with a capacitor plate and an inductor coil. When the acceleration exceeds the designed threshold-level, the water passes through the channel to the hydrogel cavity. The hydrogel swells and changes the capacitance of the integrated L-C resonator, which in turn changes the resonant frequency that can be remotely detected. Each sensor unit does not require on-board power and circuitry for operation, so the proposed device is disposable, and is suitable for low-cost applications. All PDMS structures were fabricated using soft lithography. The L-C resonator was fabricated using a lift-off process to pattern metal layers on a glass substrate. The threshold g-values, which differ for various applications, were strongly affected by the channel widths. The phase-dip measurement shows that the resonant frequencies shift from 164 MHz to approximately 148 MHz when the device is activated by acceleration.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125276120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114501
H. Cruz, Hong-Yi Huang, Shueen-Yu Lee, C. Luo
A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.
{"title":"A 2.5 mW/ch, 50 Mcps, 10-analog channel, adaptively biased read-out front-end IC with 9.71 ps-RMS timing resolution for single-photon time-of-flight PET applications in 90 nm CMOS","authors":"H. Cruz, Hong-Yi Huang, Shueen-Yu Lee, C. Luo","doi":"10.1109/VLSI-DAT.2015.7114501","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114501","url":null,"abstract":"A 10-channel time-of-flight (TOF) positron emission tomography (PET) IC that uses a digital-to-analog (DAC) - based architecture is implemented in 90nm CMOS process. The DAC is used to compensate for timing resolution variation attributed to amplifier gain fluctuation. Mixed-signal reset signals enhance photon counting speed achieving 5M counts/s/ch. The IC uses adaptive biases to stabilize the gain of preamplifiers and comparators. Multi-stage preamplifiers and comparator architectures were selected for low power. Measurement results show that these techniques enable the IC to achieve 9.71ps-RMS of intrinsic jitter and 181.5ps-FWHM (Full-width-at-half-maximum) timing resolution using an avalanche photo-diode and laser setup while consuming 2.5mW at 0.5V and 1.2V power supplies. The IC was fabricated in a 90nm CMOS process with area of 3.3 × 2.7mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126760303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114521
C. Wu, W. Kuo, H.-J. Wang, Y. Huang, Y.-H. Chen, Y.-Y. Chou, Sakurai Yu, Shey-Shi Lu
A batteryless wearable ECG monitoring system-in-a-patch assembled by a biocompatible and pliable silicon-in-parylene technology is introduced. The system is capable of processing the acquired ECG signal and detecting arrhythmia by a built-in digital signal processor (DSP). An NFC communication system is used to interface the external reader. The silicon also integrates a sub-threshold ultra-low-voltage (ULV) boost converter to harvest body heat energy from a thermoelectric generator (TEG) attached to the chest to power up the ECG system. The boost converter operates with no external kick-off circuitry, and the average efficiency is up to 60%. The assembled all-in-one system achieves a very low profile (<;0.9mm); it includes one CMOS die, two SMD inductors (for the boost converter), and two in-parylene gold coils (for the NFC communication system). The pliable parylene mold provides excellent adhesion and skin comfort.
{"title":"A pliable and batteryless real-time ECG monitoring system-in-a-patch","authors":"C. Wu, W. Kuo, H.-J. Wang, Y. Huang, Y.-H. Chen, Y.-Y. Chou, Sakurai Yu, Shey-Shi Lu","doi":"10.1109/VLSI-DAT.2015.7114521","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114521","url":null,"abstract":"A batteryless wearable ECG monitoring system-in-a-patch assembled by a biocompatible and pliable silicon-in-parylene technology is introduced. The system is capable of processing the acquired ECG signal and detecting arrhythmia by a built-in digital signal processor (DSP). An NFC communication system is used to interface the external reader. The silicon also integrates a sub-threshold ultra-low-voltage (ULV) boost converter to harvest body heat energy from a thermoelectric generator (TEG) attached to the chest to power up the ECG system. The boost converter operates with no external kick-off circuitry, and the average efficiency is up to 60%. The assembled all-in-one system achieves a very low profile (<;0.9mm); it includes one CMOS die, two SMD inductors (for the boost converter), and two in-parylene gold coils (for the NFC communication system). The pliable parylene mold provides excellent adhesion and skin comfort.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127097536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114516
Yen-Fu Chen, K. Tang
This paper presents a wireless power transmission subsystem with high power supply rejection (PSR) low dropout (LDO) regulator and thermal protection mechanism for artificial retina application. The proposed subsystem performs the functions of rectification, regulation and thermal detection. It can provide a stable DC source for implanted devices, and the subsystem only needs a small rectification capacitor. The proposed LDO achieves high PSRR performance of 46 dB at 10 MHz without any external capacitor. Moreover, the system contains the thermal protection mechanism to prevent cells from being damaged. A power controller in the system controls the received power by adjusting resonant capacitance in feedback. By controlling the received power, the system avoids receiving excessive power, enhances the power transmission efficiency, and avoids the device to be damaged by excessive heat. The proposed subsystem is to be fabricated with the TSMC 0.18 um CMOS process and occupies area of 556 um × 700 um. It achieves a high power conversion efficiency of 73 % under output voltage of 3.3 V and load current of 5 mA.
本文提出了一种具有高电源抑制(PSR)、低差(LDO)调节器和热保护机制的用于人工视网膜的无线电力传输子系统。该子系统具有整流、调节和热检测功能。它可以为植入器件提供稳定的直流电源，并且子系统只需要一个小的整流电容。在没有任何外部电容的情况下，提出的LDO在10 MHz时实现了46 dB的高PSRR性能。此外，该系统包含热保护机制，防止细胞被损坏。系统中的功率控制器通过调节反馈谐振电容来控制接收功率。通过控制接收功率，避免系统接收功率过大，提高功率传输效率，避免设备受热损坏。该子系统采用台积电0.18 um CMOS工艺制造，占地面积为556 um × 700 um。在输出电压为3.3 V，负载电流为5 mA的情况下，其功率转换效率高达73%。
{"title":"A wireless power transmission subsystem with capacitor-less high PSR LDO and thermal protection mechanism for artificial retina application","authors":"Yen-Fu Chen, K. Tang","doi":"10.1109/VLSI-DAT.2015.7114516","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114516","url":null,"abstract":"This paper presents a wireless power transmission subsystem with high power supply rejection (PSR) low dropout (LDO) regulator and thermal protection mechanism for artificial retina application. The proposed subsystem performs the functions of rectification, regulation and thermal detection. It can provide a stable DC source for implanted devices, and the subsystem only needs a small rectification capacitor. The proposed LDO achieves high PSRR performance of 46 dB at 10 MHz without any external capacitor. Moreover, the system contains the thermal protection mechanism to prevent cells from being damaged. A power controller in the system controls the received power by adjusting resonant capacitance in feedback. By controlling the received power, the system avoids receiving excessive power, enhances the power transmission efficiency, and avoids the device to be damaged by excessive heat. The proposed subsystem is to be fabricated with the TSMC 0.18 um CMOS process and occupies area of 556 um × 700 um. It achieves a high power conversion efficiency of 73 % under output voltage of 3.3 V and load current of 5 mA.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114559
J. Costa
Summary form only given. Tunable and Reconfigurable applications using RFSOI-on-HR (high resistivity) silicon technology are being deployed in increasing numbers in today's advanced RF cellular handsets in order to provide increasing data rates demanded by the consumer market. These RFSOI solutions are being deployed to meet the demanding specifications of complex 4G RF cellular front-ends with numerous transmit and receive bands, as well as the possibility of multiple antennae and new architectures which involves Uplink and Downlink carrier aggregation. Such new architectures present extreme challenges for conventional fixed band systems composed of PA's, switches and filters. The talk will present a chronology of the RFSOI-on-HR silicon technology development in the industry through the last decade and highlight novel uses of its capabilities in 4G systems as well as the critical specifications needed in this application space.
{"title":"Tunable and reconfigurable solutions using RFSOI-on-HR-Si technologies","authors":"J. Costa","doi":"10.1109/VLSI-DAT.2015.7114559","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114559","url":null,"abstract":"Summary form only given. Tunable and Reconfigurable applications using RFSOI-on-HR (high resistivity) silicon technology are being deployed in increasing numbers in today's advanced RF cellular handsets in order to provide increasing data rates demanded by the consumer market. These RFSOI solutions are being deployed to meet the demanding specifications of complex 4G RF cellular front-ends with numerous transmit and receive bands, as well as the possibility of multiple antennae and new architectures which involves Uplink and Downlink carrier aggregation. Such new architectures present extreme challenges for conventional fixed band systems composed of PA's, switches and filters. The talk will present a chronology of the RFSOI-on-HR silicon technology development in the industry through the last decade and highlight novel uses of its capabilities in 4G systems as well as the critical specifications needed in this application space.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130314535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114561
Jean-Marc Le Meil, B. Aspar, E. Desbonnets, J. Raskin
The increasing demand for wireless data bandwidth and the rapid adoption of LTE and LTE Advanced standards push radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance [1]. In this paper, Soitec and UCL explain the value of using RF-SOI substrates and more especially the new generation of Soitec widely adopted eSI™ (enhanced Signal Integrity) substrate to achieve the RF IC performance requested to address the LTE Advanced smart phone market.
{"title":"Engineered substrates: The foundation to meet current and future RF requirements","authors":"Jean-Marc Le Meil, B. Aspar, E. Desbonnets, J. Raskin","doi":"10.1109/VLSI-DAT.2015.7114561","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114561","url":null,"abstract":"The increasing demand for wireless data bandwidth and the rapid adoption of LTE and LTE Advanced standards push radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance [1]. In this paper, Soitec and UCL explain the value of using RF-SOI substrates and more especially the new generation of Soitec widely adopted eSI™ (enhanced Signal Integrity) substrate to achieve the RF IC performance requested to address the LTE Advanced smart phone market.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114535
Sunil Dutt, Anshu Chauhan, Sukumar Nandi, G. Trivedi
Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-and-Accumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.
{"title":"Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units","authors":"Sunil Dutt, Anshu Chauhan, Sukumar Nandi, G. Trivedi","doi":"10.1109/VLSI-DAT.2015.7114535","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114535","url":null,"abstract":"Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-and-Accumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128688121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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