Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114540
G. Rincón-Mora
Summary form only given. Wireless microsensors and other miniaturized electronics cannot only monitor and better-manage power consumption in emerging small- and large-scale applications (for space, military, medical, agricultural, and consumer markets) but also add energy-saving and performance-enhancing intelligence to old, expensive, and difficult-to-replace infrastructures and tiny contraptions in difficult-to-reach places (like the human body). The energy these smart devices store, however, is often insufficient to power the functions they incorporate (such as telemetry, interface, processing, and others) for extended periods. Still more, replacing or recharging the batteries of hundreds of networked nodes is costly, and invasive in the case of the human body. Harvesting ambient energy to continually replenish a battery and wirelessly harnessing radiated energy periodically are therefore appealing alternatives, even if the development of relevant technologies today is, in relative terms, at its infancy. This talk discusses the state of the art and current research efforts in harnessing and conditioning energy and power from miniaturized transducers.
{"title":"Energy-harvesting microsystems","authors":"G. Rincón-Mora","doi":"10.1109/VLSI-DAT.2015.7114540","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114540","url":null,"abstract":"Summary form only given. Wireless microsensors and other miniaturized electronics cannot only monitor and better-manage power consumption in emerging small- and large-scale applications (for space, military, medical, agricultural, and consumer markets) but also add energy-saving and performance-enhancing intelligence to old, expensive, and difficult-to-replace infrastructures and tiny contraptions in difficult-to-reach places (like the human body). The energy these smart devices store, however, is often insufficient to power the functions they incorporate (such as telemetry, interface, processing, and others) for extended periods. Still more, replacing or recharging the batteries of hundreds of networked nodes is costly, and invasive in the case of the human body. Harvesting ambient energy to continually replenish a battery and wirelessly harnessing radiated energy periodically are therefore appealing alternatives, even if the development of relevant technologies today is, in relative terms, at its infancy. This talk discusses the state of the art and current research efforts in harnessing and conditioning energy and power from miniaturized transducers.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121204501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114550
Wen-Ping Lee, Cheng Wang
This work presents our verification methodology from architecture to RTL design. There are three major benefits of the proposed verification methodology. First, this methodology enables the verification task to start at architecture design stage even without the implementation details. Second, the verification framework is well-organized and suitable for fully automation. Hence, human-introduced errors can be eliminated and the verification environment can be brought up efficiently. Thus verification engineers can focus on developing scenario to verify the RTL design. The most important one is that this methodology defines a framework for verifying designs at different design stages. In addition, flexibility is also kept for successive refinement of testbench when design state move from architecture to RTL stage. High reusability saves many manual efforts from developing and maintaining different verification environments for different design state. High flexibility makes the verification environment to be easily extended for different design stages.
{"title":"Reusable and flexible verification methodology from architecture to RTL design","authors":"Wen-Ping Lee, Cheng Wang","doi":"10.1109/VLSI-DAT.2015.7114550","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114550","url":null,"abstract":"This work presents our verification methodology from architecture to RTL design. There are three major benefits of the proposed verification methodology. First, this methodology enables the verification task to start at architecture design stage even without the implementation details. Second, the verification framework is well-organized and suitable for fully automation. Hence, human-introduced errors can be eliminated and the verification environment can be brought up efficiently. Thus verification engineers can focus on developing scenario to verify the RTL design. The most important one is that this methodology defines a framework for verifying designs at different design stages. In addition, flexibility is also kept for successive refinement of testbench when design state move from architecture to RTL stage. High reusability saves many manual efforts from developing and maintaining different verification environments for different design state. High flexibility makes the verification environment to be easily extended for different design stages.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116716292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114535
Sunil Dutt, Anshu Chauhan, Sukumar Nandi, G. Trivedi
Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-and-Accumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.
{"title":"Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units","authors":"Sunil Dutt, Anshu Chauhan, Sukumar Nandi, G. Trivedi","doi":"10.1109/VLSI-DAT.2015.7114535","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114535","url":null,"abstract":"Variations in process parameter jeopardize the parametric yield which imposes severe cost implication on the semiconductor industry. Post-silicon tunning, such as Adaptive Body Bias (ABB) and Dynamic Voltage Scaling (DVS) is a powerful technique that mitigates the impacts of process parameter variations. However, since process parameter variations are getting aggravated with continued CMOS technology scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, to enhance the parametric yield, we integrate ABB and DVS for the Hybrid Redundant Multiply-and-Accumulate (HR-MAC) units. Simulation results based on the PTM 32nm CMOS technology show that the proposed approach enhances the parametric yield at Fast-Fast (FF), Fast-Slow (FS), Slow-Fast (SF) and Slow-Slow (SS) process corners by 81.5%, 45.3%, 59.92% and 89.08%, respectively.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128688121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114574
Che-Min Huang, Tsung-Te Liu, T. Chiueh
This paper presents a timing error resilient flip-flop (ERFF) circuit with high energy-efficiency. The proposed flip-flop design automatically corrects timing errors and therefore minimizes the performance degradation due to variations. The simulation results show that the proposed design can achieve better energy-efficiency in ISCAS'89 benchmark circuits and LEON3 integer-processing unit, when compared to other state-of-the-art timing error detection and correction methods.
{"title":"An energy-efficient resilient flip-flop circuit with built-in timing-error detection and correction","authors":"Che-Min Huang, Tsung-Te Liu, T. Chiueh","doi":"10.1109/VLSI-DAT.2015.7114574","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114574","url":null,"abstract":"This paper presents a timing error resilient flip-flop (ERFF) circuit with high energy-efficiency. The proposed flip-flop design automatically corrects timing errors and therefore minimizes the performance degradation due to variations. The simulation results show that the proposed design can achieve better energy-efficiency in ISCAS'89 benchmark circuits and LEON3 integer-processing unit, when compared to other state-of-the-art timing error detection and correction methods.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124933522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114525
Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, I. Baz, A. Schmid, Y. Leblebici
This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates a very high-quality depth map by merging two depth maps obtained from the center-left and center-right camera pairs. The T-AWDE hardware enhances disparity results by applying a double checking scheme which solves most of the occlusion problems existing in the AWDE implementation while providing correct disparity results even for objects located at left or right edge of the center image. The proposed T-AWDE hardware architecture enables handling 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for a 128 pixels disparity range.
{"title":"Trinocular adaptive window size disparity estimation algorithm and its real-time hardware","authors":"Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, I. Baz, A. Schmid, Y. Leblebici","doi":"10.1109/VLSI-DAT.2015.7114525","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114525","url":null,"abstract":"This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates a very high-quality depth map by merging two depth maps obtained from the center-left and center-right camera pairs. The T-AWDE hardware enhances disparity results by applying a double checking scheme which solves most of the occlusion problems existing in the AWDE implementation while providing correct disparity results even for objects located at left or right edge of the center image. The proposed T-AWDE hardware architecture enables handling 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for a 128 pixels disparity range.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121026701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114533
F. Altolaguirre, M. Ker
This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.
本文提出了一种新颖的输入ESD保护设计。通过将保护电阻器替换为主动开关，在ESD应力下隔离输入晶体管和焊盘，可以大大提高ESD稳健性。在40纳米CMOS工艺中，仅使用薄氧化物器件对所提出的设计进行了设计和验证，并成功通过了2 kv HBM和200 v MM典型工业ESD保护规范的ESD测试。
{"title":"Active ESD protection for input transistors in a 40-nm CMOS process","authors":"F. Altolaguirre, M. Ker","doi":"10.1109/VLSI-DAT.2015.7114533","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114533","url":null,"abstract":"This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128944221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114571
Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee
In this work, a design for diagnosability (DFD) method based on observation point (OP) insertion is proposed to improve the diagnosis resolution of transition faults in a circuit. The main objective is to minimize the number of observation points since this number will directly affect the area overhead of the circuit. We develop a novel algorithm to generate a set of OP candidates and then select a minimal number of OPs from this set which can distinguish all targeted fault pairs. An observation point insertion logic is also proposed that can efficiently reuse the output pins in the original circuit so as to reduce the number of extra output pins. In addition, a novel structural distance calculation method for synthesized circuits is proposed that considers the mixed structure of primitive gates and complicated gates, including AOI or OAI gates. Experimental results show that after applying the OP insertion method, all aborted fault pairs can be distinguished and the number of required observation points is quite small. We also use the observation points to distinguish those indistinguished far-away fault pairs. Experimental results show that all targeted fault pairs can be distinguished with a few observation points and a set of diagnosis patterns for ISCAS89 and ITC99 circuits.
{"title":"Improve transition fault diagnosability via observation point insertion","authors":"Cheng-Hung Wu, Yi-Da Wang, Kuen-Jong Lee","doi":"10.1109/VLSI-DAT.2015.7114571","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114571","url":null,"abstract":"In this work, a design for diagnosability (DFD) method based on observation point (OP) insertion is proposed to improve the diagnosis resolution of transition faults in a circuit. The main objective is to minimize the number of observation points since this number will directly affect the area overhead of the circuit. We develop a novel algorithm to generate a set of OP candidates and then select a minimal number of OPs from this set which can distinguish all targeted fault pairs. An observation point insertion logic is also proposed that can efficiently reuse the output pins in the original circuit so as to reduce the number of extra output pins. In addition, a novel structural distance calculation method for synthesized circuits is proposed that considers the mixed structure of primitive gates and complicated gates, including AOI or OAI gates. Experimental results show that after applying the OP insertion method, all aborted fault pairs can be distinguished and the number of required observation points is quite small. We also use the observation points to distinguish those indistinguished far-away fault pairs. Experimental results show that all targeted fault pairs can be distinguished with a few observation points and a set of diagnosis patterns for ISCAS89 and ITC99 circuits.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124423209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114494
Yi-Hang Chen, Yang-Wen Chen, Juinn-Dar Huang
The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.
{"title":"ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays","authors":"Yi-Hang Chen, Yang-Wen Chen, Juinn-Dar Huang","doi":"10.1109/VLSI-DAT.2015.7114494","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114494","url":null,"abstract":"The power dissipation has become a crucial issue for most electronic circuit and system designs nowadays when fabrication processes exploit even deeper submicron technology. In particular, leakage power is becoming a dominant source of power consumption. In recent years, the reconfigurable single-electron transistor (SET) array has been proposed as an emerging circuit design style for continuing Moore's Law due to its ultra-low power consumption. Several automated synthesis techniques for area minimization have been developed for the reconfigurable SET array in the past few years. Nevertheless, most of those existing methods focus on variable and product term reordering during SET mapping. In fact, minimizing the number of product terms can greatly reduce the area as well, which has not been well addressed before. In this paper, we propose a dynamic shifting based variable ordering algorithm that can minimize the number of disjoint sum-of-product terms extracted from the given ROBDD. Experimental results show that the proposed method can achieve an area reduction of up to 49% as compared to current state-of-the-art techniques.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132491891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114532
Albert Lee, Chien-Chen Lin, T. Yang, Meng-Fan Chang
This paper presents a Contact Resistive Random Access Memory (CRRAM) macro with an offset-compensated Sense amplifier for low-voltage operation. The proposed circuit aims to solve the variation and speed issues during low-voltage operations. A 256Kb test-chip was fabricated in TSMC 65nm technology. An improvement of 1.78x in read speed and 85.7% in offset was measured compared to conventional sensing methods, and the minimum operating voltage was as low as 0.3V.
{"title":"An embedded ReRAM using a small-offset sense amplifier for low-voltage operations","authors":"Albert Lee, Chien-Chen Lin, T. Yang, Meng-Fan Chang","doi":"10.1109/VLSI-DAT.2015.7114532","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114532","url":null,"abstract":"This paper presents a Contact Resistive Random Access Memory (CRRAM) macro with an offset-compensated Sense amplifier for low-voltage operation. The proposed circuit aims to solve the variation and speed issues during low-voltage operations. A 256Kb test-chip was fabricated in TSMC 65nm technology. An improvement of 1.78x in read speed and 85.7% in offset was measured compared to conventional sensing methods, and the minimum operating voltage was as low as 0.3V.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130377197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114566
Wu-Tung Cheng
Summary form only given. Due to various manufacture difficulties in nano-scale semiconductor devices, certain layout patterns cannot be manufactured properly and cause significant yield loss. Due to the time to run through complete lithography simulation, it is impossible to identify all of them before silicon manufacture. Therefore, post-silicon physical failure analysis is needed to find them one-by-one to improve yield iteratively with each re-spin. However, physical failure analysis is time-consuming such that each re-spin can take a long time. To speed-up yield ramp-up, we proposed to automatically identify as many layout patterns as possible by using volume diagnosis from post-silicon manufacture failure data. Typically volume diagnosis uses two procedures. First, responses from failing devices are analyzed using defect diagnosis tools. Next the results of diagnoses are analyzed using statistical, data mining and machine learning techniques to effectively determine the underlying problematic layout patterns. In this presentation, we will discuss the procedures and statistics methods for analyzing diagnosis data and put special attention to the link between defects and layout patterns.
{"title":"Identify problematic layout patterns through volume diagnosis","authors":"Wu-Tung Cheng","doi":"10.1109/VLSI-DAT.2015.7114566","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114566","url":null,"abstract":"Summary form only given. Due to various manufacture difficulties in nano-scale semiconductor devices, certain layout patterns cannot be manufactured properly and cause significant yield loss. Due to the time to run through complete lithography simulation, it is impossible to identify all of them before silicon manufacture. Therefore, post-silicon physical failure analysis is needed to find them one-by-one to improve yield iteratively with each re-spin. However, physical failure analysis is time-consuming such that each re-spin can take a long time. To speed-up yield ramp-up, we proposed to automatically identify as many layout patterns as possible by using volume diagnosis from post-silicon manufacture failure data. Typically volume diagnosis uses two procedures. First, responses from failing devices are analyzed using defect diagnosis tools. Next the results of diagnoses are analyzed using statistical, data mining and machine learning techniques to effectively determine the underlying problematic layout patterns. In this presentation, we will discuss the procedures and statistics methods for analyzing diagnosis data and put special attention to the link between defects and layout patterns.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：