Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114520
Zhengyuan Huang, Chin-Fong Chiu, C. Hsieh
Conventional TOF depth image sensors have suffered from the reset kBTC noise of required accumulation readout of multiple-phase signal without feasible correlated double sampling (CDS) operation. This paper presents a new TOF pixel circuit with kBTC reset noise cancellation by proposed equalized reset (ER) operation. Accompanied with the differential operation of phase modulation readout for depth calculation, ER pixel effective cancel out the reset noise and reduce fixed pattern noise as well. For background suppression, sub-integrating (SI) operation is also proposed to extend the dynamic range for various applications. A prototype chip with 64×128 pixel array and 3.3V operation has been designed and fabricated in 0.13μm CMOS image sensor (CIS) technology. The pixel pitch is 10×10 um2 with a fill factor of 24.9%; and the chip size is 2.5mm×2.2mm. The measurement result shows 67% reduction of pixel fixed-pattern-noise (FPN), 300uV cancellation of kTC noise, and 23.1dB SNR improvement compared to the counterpart without ER and SI operation.
{"title":"An in-pixel equalizer with kTC noise cancellation and FPN reduction for time-of-flight CMOS image sensor","authors":"Zhengyuan Huang, Chin-Fong Chiu, C. Hsieh","doi":"10.1109/VLSI-DAT.2015.7114520","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114520","url":null,"abstract":"Conventional TOF depth image sensors have suffered from the reset kBTC noise of required accumulation readout of multiple-phase signal without feasible correlated double sampling (CDS) operation. This paper presents a new TOF pixel circuit with kBTC reset noise cancellation by proposed equalized reset (ER) operation. Accompanied with the differential operation of phase modulation readout for depth calculation, ER pixel effective cancel out the reset noise and reduce fixed pattern noise as well. For background suppression, sub-integrating (SI) operation is also proposed to extend the dynamic range for various applications. A prototype chip with 64×128 pixel array and 3.3V operation has been designed and fabricated in 0.13μm CMOS image sensor (CIS) technology. The pixel pitch is 10×10 um2 with a fill factor of 24.9%; and the chip size is 2.5mm×2.2mm. The measurement result shows 67% reduction of pixel fixed-pattern-noise (FPN), 300uV cancellation of kTC noise, and 23.1dB SNR improvement compared to the counterpart without ER and SI operation.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"270 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115244691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114572
Xiaokun Zhao, Zheng Song, B. Chi
A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.
{"title":"A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver","authors":"Xiaokun Zhao, Zheng Song, B. Chi","doi":"10.1109/VLSI-DAT.2015.7114572","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114572","url":null,"abstract":"A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm2 die area and consumes 1.82mA (I and Q path) from a 1.7V supply.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125278177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114503
Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, C. Li
Some cell-internal defects can be modeled as small delay faults. This paper presents a timing-aware gate exhaustive transition fault (TARGET) ATPG for cell-internal defects. Our ATPG tries to launch gate output transitions from as many different gate input transitions as possible. We defined TARGET coverage and TARGET SDQL to evaluate the quality of our test sets. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional N-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.
{"title":"TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for cell-internal defects","authors":"Ang-Feng Lin, Kuan-Yu Liao, Kuan-Ying Chiang, C. Li","doi":"10.1109/VLSI-DAT.2015.7114503","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114503","url":null,"abstract":"Some cell-internal defects can be modeled as small delay faults. This paper presents a timing-aware gate exhaustive transition fault (TARGET) ATPG for cell-internal defects. Our ATPG tries to launch gate output transitions from as many different gate input transitions as possible. We defined TARGET coverage and TARGET SDQL to evaluate the quality of our test sets. TARGET does not require exhaustive SPICE simulation to characterize each library cell. Compared with traditional N-detect and timing-aware test patterns, the proposed TARGET test patterns have better TARGET coverage given the same test length.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124662058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114526
J. Lin, B. Lai
Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.
{"title":"BRAM efficient multi-ported memory on FPGA","authors":"J. Lin, B. Lai","doi":"10.1109/VLSI-DAT.2015.7114526","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114526","url":null,"abstract":"Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117206842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114504
Shyue-Kung Lu, Shu-Ling Lin, Hao Lin, M. Hashizume
Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability. Besides the traditional hardware redundancy techniques, fault masking features are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. The hybrid scrambling technique basically consists of the row scrambling and the column scrambling techniques. Therefore, instead of scrambling a memory row/column, a logical memory cell can be scrambled into any of the logical memory cell address. This greatly improves the flexibility of scrambling. A hybrid scrambling control word is used for the control of the scrambling. Since the codes to be programmed into the NROM chips are known before programming, selecting a suitable code for programming a faulty NROM chip is helpful to further mask the faulty effects. Based on the proposed technique, possibilities of fault masking can be maximized. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
{"title":"Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs","authors":"Shyue-Kung Lu, Shu-Ling Lin, Hao Lin, M. Hashizume","doi":"10.1109/VLSI-DAT.2015.7114504","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114504","url":null,"abstract":"Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability. Besides the traditional hardware redundancy techniques, fault masking features are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. The hybrid scrambling technique basically consists of the row scrambling and the column scrambling techniques. Therefore, instead of scrambling a memory row/column, a logical memory cell can be scrambled into any of the logical memory cell address. This greatly improves the flexibility of scrambling. A hybrid scrambling control word is used for the control of the scrambling. Since the codes to be programmed into the NROM chips are known before programming, selecting a suitable code for programming a faulty NROM chip is helpful to further mask the faulty effects. Based on the proposed technique, possibilities of fault masking can be maximized. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130359981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114527
Huai-Ting Li, Ding-Yuan Lee, Kun-Chih Chen, A. Wu
To fit into multiple communication standards, flexible Low-Density Parity-Check (LDPC) decoding is desirable to be implemented in a chip multiprocessor (CMP) system. However, reliability issues, such as soft errors and timing errors, are severer in future advanced CMP systems when CMOS technology scale. Therefore, enhancing error resilience for a CMP system becomes an important design issue. In this paper, we propose a design methodology to achieve a robust LDPC decoding based on algorithmic error-resilient method. We firstly analyze the performance degradation caused by the soft errors which occur in the computing units (check node units and bit node units), and then explore the inherent error-tolerant characteristic of LDPC decoding algorithm. In our proposed method, we exploit some characteristic distribution or behavior in the operations of the LDPC decoding algorithm to validate the computing results. The experimental results show that the proposed algorithmic error resilience can approach the error-free decoder while facing high injected soft-error rate of 10-3 in computing units, but with only 6.07% computational overhead. To the best of our knowledge, this is the first discussion about the LDPC decoding algorithm in terms of soft errors in computing units.
{"title":"An algorithmic error-resilient scheme for robust LDPC decoding","authors":"Huai-Ting Li, Ding-Yuan Lee, Kun-Chih Chen, A. Wu","doi":"10.1109/VLSI-DAT.2015.7114527","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114527","url":null,"abstract":"To fit into multiple communication standards, flexible Low-Density Parity-Check (LDPC) decoding is desirable to be implemented in a chip multiprocessor (CMP) system. However, reliability issues, such as soft errors and timing errors, are severer in future advanced CMP systems when CMOS technology scale. Therefore, enhancing error resilience for a CMP system becomes an important design issue. In this paper, we propose a design methodology to achieve a robust LDPC decoding based on algorithmic error-resilient method. We firstly analyze the performance degradation caused by the soft errors which occur in the computing units (check node units and bit node units), and then explore the inherent error-tolerant characteristic of LDPC decoding algorithm. In our proposed method, we exploit some characteristic distribution or behavior in the operations of the LDPC decoding algorithm to validate the computing results. The experimental results show that the proposed algorithmic error resilience can approach the error-free decoder while facing high injected soft-error rate of 10-3 in computing units, but with only 6.07% computational overhead. To the best of our knowledge, this is the first discussion about the LDPC decoding algorithm in terms of soft errors in computing units.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130559401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114562
Gene Li
Summary form only given. This presentation intends to reveal UMC's viewpoints on how loT will change the landscape of foundry service. The ever-evolving applications and requirements have substantially impacted chip specs and the supporting foundry technologies and IP's, accordingly. This talk will elaborate the interlocks from application specs, design needs, and process technologies and IP's adapting to new power/performance/cost requirements in loT era. In addition, the fragmented application nature in loT market requires comprehensive technology portfolio support from foundry house. Extensive new technology platform offerings, optimizing for ultralow power consumption and best C/P value, and services are to be introduced.
{"title":"Specialty technology for loT","authors":"Gene Li","doi":"10.1109/VLSI-DAT.2015.7114562","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114562","url":null,"abstract":"Summary form only given. This presentation intends to reveal UMC's viewpoints on how loT will change the landscape of foundry service. The ever-evolving applications and requirements have substantially impacted chip specs and the supporting foundry technologies and IP's, accordingly. This talk will elaborate the interlocks from application specs, design needs, and process technologies and IP's adapting to new power/performance/cost requirements in loT era. In addition, the fragmented application nature in loT market requires comprehensive technology portfolio support from foundry house. Extensive new technology platform offerings, optimizing for ultralow power consumption and best C/P value, and services are to be introduced.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114576
Yung-Hui Yu, Po-Hao Wang, S. Tsai, Tien-Fu Chen
The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault-tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.
{"title":"A latency-elastic and fault-tolerant cache for improving performance and reliability on low voltage operation","authors":"Yung-Hui Yu, Po-Hao Wang, S. Tsai, Tien-Fu Chen","doi":"10.1109/VLSI-DAT.2015.7114576","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114576","url":null,"abstract":"The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the performance and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a latency-elastic and fault-tolerant cache not only for fault-tolerant, but aiming at the performance issues. It varies the latency of cache access to achieve better-than-worst-case designs for improving performance.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114519
Ting-Yang Wang, Tai-Cheng Lee
This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.
{"title":"A 84.7-DR wide BW incremental ADC using CT structure","authors":"Ting-Yang Wang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT.2015.7114519","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114519","url":null,"abstract":"This work uses continuous-tome (CT) structure to make the sigma-delta modulator faster and consuming less power. A third-order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the paper. The modulator is operated at 100MHz sampling clock. It achieves dynamic range of 84.7 dB, peak SNDR of 73.82 dB within the 737-kHz bandwidth. This chip dissipates 6.6mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123037310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114553
W. Rhines
One of the great promises of the Internet of Things (IoT) is the extraordinarily large volume of semiconductor components that will be required for smart sensors and actuators, as well as for big digital chips to do the information processing. Yet the growing complexity that comes from shrinking design rules, ultra-low power mixed signal design and diverse packaging are threatening the traditional reduction in cost per transistor that has fueled semiconductor industry growth in the past. Dr. Rhines will analyze the evolution of semiconductor design and production costs to provide predictions of what designers will have to work with in the coming decade and what capabilities will be enabled.
{"title":"Cost challenges on the way to the Internet of Things","authors":"W. Rhines","doi":"10.1109/VLSI-DAT.2015.7114553","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114553","url":null,"abstract":"One of the great promises of the Internet of Things (IoT) is the extraordinarily large volume of semiconductor components that will be required for smart sensors and actuators, as well as for big digital chips to do the information processing. Yet the growing complexity that comes from shrinking design rules, ultra-low power mixed signal design and diverse packaging are threatening the traditional reduction in cost per transistor that has fueled semiconductor industry growth in the past. Dr. Rhines will analyze the evolution of semiconductor design and production costs to provide predictions of what designers will have to work with in the coming decade and what capabilities will be enabled.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115065607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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