Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114560
S. Kengeri
Summary form only given. The rapid evolution of applications in the consumer and mobile space coupled with the emergence of the Internet of Things (IoT) are driving foundries to diversify design-technology solutions. This talk will discuss innovations that are on the horizon to enable differentiation in power, performance, cost, and time-to-volume, while solving the issues with unprecedented integration of “user-experience” functions. Technology innovations in the areas of FDSOI, eNVM, MEMS, RF, Ultra-Low Vmin SRAM, 3D and Design innovations on DVFS, Post-Silicon tuning, Analog optimization will be reviewed.
{"title":"Design-technology innovations enabling differentiation in emerging applications","authors":"S. Kengeri","doi":"10.1109/VLSI-DAT.2015.7114560","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114560","url":null,"abstract":"Summary form only given. The rapid evolution of applications in the consumer and mobile space coupled with the emergence of the Internet of Things (IoT) are driving foundries to diversify design-technology solutions. This talk will discuss innovations that are on the horizon to enable differentiation in power, performance, cost, and time-to-volume, while solving the issues with unprecedented integration of “user-experience” functions. Technology innovations in the areas of FDSOI, eNVM, MEMS, RF, Ultra-Low Vmin SRAM, 3D and Design innovations on DVFS, Post-Silicon tuning, Analog optimization will be reviewed.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117235452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114545
F. Silveira, J. Oreggioni, Pablo Castro-Lisboa
Active implantable medical devices (AIMDs) are microsystems requiring ultra low energy operation, which is a characteristic increasingly shared by several other applications. On the other hand, AIMDs must comply with several specific constraints imposed by the medical implantable context. This paper first summarizes, from the point of view of the analog IC designer, the state of the art of AIMDs and their specific constraints. Then, some general design techniques for analog ICs for AIMDs are highlighted and an analog front-end for neural devices is presented to illustrate current circuit and architecture approaches.
{"title":"Constraints and design approaches in analog ICs forlmplantable medical devices","authors":"F. Silveira, J. Oreggioni, Pablo Castro-Lisboa","doi":"10.1109/VLSI-DAT.2015.7114545","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114545","url":null,"abstract":"Active implantable medical devices (AIMDs) are microsystems requiring ultra low energy operation, which is a characteristic increasingly shared by several other applications. On the other hand, AIMDs must comply with several specific constraints imposed by the medical implantable context. This paper first summarizes, from the point of view of the analog IC designer, the state of the art of AIMDs and their specific constraints. Then, some general design techniques for analog ICs for AIMDs are highlighted and an analog front-end for neural devices is presented to illustrate current circuit and architecture approaches.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116515635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114530
Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin
Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.
{"title":"Low-power gated clock tree optimization for three-dimensional integrated circuits","authors":"Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin","doi":"10.1109/VLSI-DAT.2015.7114530","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114530","url":null,"abstract":"Applying clock gating in three dimensional integrated circuits (3D ICs) is essential for reducing power consumption and improving circuit reliability. However, the previous works only present algorithms for 3D clock tree synthesis. None of them address gated clock tree in 3D ICs for dynamic power reduction. In this paper, we propose the first problem formulation in the literature for 3D gated clock network optimization. We consider both flip-flop switching activities and the timing constraint of enable signal paths at clock gating cells when constructing topological gated clock trees. Based on the topological gated clock trees, a zero-skew 3D clock routing tree is then generated. Experimental results show that, compared with conventional 3D clock tree synthesis, the proposed 3D gated clock tree synthesis can achieve much less power consumption with similar number of TSVs and clock tree wirelength.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-TSA.2015.7117541
T. Yamauchi
Embedded Flash (eFlash) is widely accepted by various applications because of reducing overall costs of system development, production and inventory. Continuous evolution of eFlash such as the split-gate charge-trapping memory has satisfied the most stringent quality requirement for automotive applications. Smart society for offering a better quality of life would diversify NV memory until the establishment of emerging memories. Add-on type eFlash with a few additional masks would replace the stand-alone data flash for adaptive tuning and security over the network. Towards the possible convergence of NV-memory in smart society, emerging memories such as ReRAM and STT-MRAM are progressing. Excellent features of smaller rewrite energy with the extending rewrite cycles could contribute to the outstanding energy saving such as normally-off systems.
{"title":"Prospect of embedded non-volatile memory in the smart society","authors":"T. Yamauchi","doi":"10.1109/VLSI-TSA.2015.7117541","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2015.7117541","url":null,"abstract":"Embedded Flash (eFlash) is widely accepted by various applications because of reducing overall costs of system development, production and inventory. Continuous evolution of eFlash such as the split-gate charge-trapping memory has satisfied the most stringent quality requirement for automotive applications. Smart society for offering a better quality of life would diversify NV memory until the establishment of emerging memories. Add-on type eFlash with a few additional masks would replace the stand-alone data flash for adaptive tuning and security over the network. Towards the possible convergence of NV-memory in smart society, emerging memories such as ReRAM and STT-MRAM are progressing. Excellent features of smaller rewrite energy with the extending rewrite cycles could contribute to the outstanding energy saving such as normally-off systems.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133959353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114538
Ping-Yuan Tsai, Yuyuan Chang, S. Hsu, Chen-Yi Lee
This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and (2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes - high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm2 chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.
{"title":"An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver","authors":"Ping-Yuan Tsai, Yuyuan Chang, S. Hsu, Chen-Yi Lee","doi":"10.1109/VLSI-DAT.2015.7114538","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114538","url":null,"abstract":"This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and (2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes - high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm2 chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131133318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114522
Yu-Lee Yen, C. Kuo, Ching-Feng Lee, Kevin Chen
This paper presents the design of a variable gain amplifier for the frontend circuitry of 5-GHz high-speed digital storage oscilloscopes. The design challenge includes wide bandwidth and low distortion over the frequency range from dc to 5 GHz. The Cherry-Hooper amplifier configuration is used to tackle the issue. The designed variable gain covers the specified range from -2 to 38 dB. The gain flatness carries out ripples less than 1 dB. To verify our approach, two versions of the amplifier circuits are fabricated. With four cascaded stages, the maximum gain achieves larger than 40 dB. The circuits are designed in 0.35 μm SiGe technology.
{"title":"DC-to-5-GHz variable gain amplifier for high speed DSO","authors":"Yu-Lee Yen, C. Kuo, Ching-Feng Lee, Kevin Chen","doi":"10.1109/VLSI-DAT.2015.7114522","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114522","url":null,"abstract":"This paper presents the design of a variable gain amplifier for the frontend circuitry of 5-GHz high-speed digital storage oscilloscopes. The design challenge includes wide bandwidth and low distortion over the frequency range from dc to 5 GHz. The Cherry-Hooper amplifier configuration is used to tackle the issue. The designed variable gain covers the specified range from -2 to 38 dB. The gain flatness carries out ripples less than 1 dB. To verify our approach, two versions of the amplifier circuits are fabricated. With four cascaded stages, the maximum gain achieves larger than 40 dB. The circuits are designed in 0.35 μm SiGe technology.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.
{"title":"A hybrid built-in self-test scheme for DRAMs","authors":"Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, D. Kwai, Yung-Fa Chou","doi":"10.1109/VLSI-DAT.2015.7114502","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114502","url":null,"abstract":"This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133514018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage (HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.
{"title":"A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications","authors":"An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo","doi":"10.1109/VLSI-DAT.2015.7114537","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114537","url":null,"abstract":"Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage (HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116422789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114573
J. Chiou, S. Hsu, Cheng-Kai Kuei, Tsung-Wei Wu
In this paper, an addressable UHF EPCGlobal Class1 Gen2 sensor IC for wireless intraocular pressure (IOP) monitoring on contact lens sensor device is proposed. The proposed sensor IC consists of RFID Analog/RF Front End, capacitive sensor readout circuit, and digital processing unit. RFID Analog/RF front end is used for power management and data transmission. Sensor Readout Circuit will convert the measured capacitor value to digital format for digital processing unit. Digital processing unit is used as processor not only for sensor value processing obtained from the sensor readout circuit, but also for bidirectional communication between RFID reader and sensor IC. This sensor IC architecture combined with specific sensor and corresponding sensor readout circuit can be widely used as noninvasive biomedical sensor devices and systems. Wireless communication and sensor data transmission are implemented with UHF RFID technology, providing much flexibility and can reduce self-developed firmware effort for this architecture in the future.
{"title":"An addressable UHF EPCGlobal Class1 Gen2 Sensor IC for wireless IOP monitoring on contact lens","authors":"J. Chiou, S. Hsu, Cheng-Kai Kuei, Tsung-Wei Wu","doi":"10.1109/VLSI-DAT.2015.7114573","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114573","url":null,"abstract":"In this paper, an addressable UHF EPCGlobal Class1 Gen2 sensor IC for wireless intraocular pressure (IOP) monitoring on contact lens sensor device is proposed. The proposed sensor IC consists of RFID Analog/RF Front End, capacitive sensor readout circuit, and digital processing unit. RFID Analog/RF front end is used for power management and data transmission. Sensor Readout Circuit will convert the measured capacitor value to digital format for digital processing unit. Digital processing unit is used as processor not only for sensor value processing obtained from the sensor readout circuit, but also for bidirectional communication between RFID reader and sensor IC. This sensor IC architecture combined with specific sensor and corresponding sensor readout circuit can be widely used as noninvasive biomedical sensor devices and systems. Wireless communication and sensor data transmission are implemented with UHF RFID technology, providing much flexibility and can reduce self-developed firmware effort for this architecture in the future.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121772575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114495
Chien-Hui Liao, Yu-Ze Lin, Charles H.-P. Wen
Thermal-constrained task scheduler for throughput optimization on 3D multi-core processors (3D-MCPs) has been studied extensively. Most task scheduler focused on thermal-aware task allocation to reduce hotspots, thereby maximizing throughput under thermal constraints. Rather than focusing on the thermal-aware task allocation as previous work does, this work targets on the voltage assignment. In this paper, dynamic voltage assignment is proposed to pre-emptively assign different voltage levels to cores frequently for reducing temperature increase in 3D-MCPs. Experimental results show that two previous task schedulers integrated with the proposed dynamic voltage assignment can lower hotspot occurrences by 62.31% and 59.09%, and improve throughput by 18.28% and 18.35%, respectively. As a result, task schedulers integrated with the proposed dynamic voltage assignment can be more effective to reduce occurrences of hotspots and optimize throughput for 3D-MCPs under thermal constraints.
{"title":"Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors","authors":"Chien-Hui Liao, Yu-Ze Lin, Charles H.-P. Wen","doi":"10.1109/VLSI-DAT.2015.7114495","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114495","url":null,"abstract":"Thermal-constrained task scheduler for throughput optimization on 3D multi-core processors (3D-MCPs) has been studied extensively. Most task scheduler focused on thermal-aware task allocation to reduce hotspots, thereby maximizing throughput under thermal constraints. Rather than focusing on the thermal-aware task allocation as previous work does, this work targets on the voltage assignment. In this paper, dynamic voltage assignment is proposed to pre-emptively assign different voltage levels to cores frequently for reducing temperature increase in 3D-MCPs. Experimental results show that two previous task schedulers integrated with the proposed dynamic voltage assignment can lower hotspot occurrences by 62.31% and 59.09%, and improve throughput by 18.28% and 18.35%, respectively. As a result, task schedulers integrated with the proposed dynamic voltage assignment can be more effective to reduce occurrences of hotspots and optimize throughput for 3D-MCPs under thermal constraints.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125885218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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