Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114568
Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, C. Liu
Because the bio-signals are often very weak, they can be influenced by noise easily and become hard to distinguish. In this paper, an automatic analog synthesis platform is presented for bio-acquisition systems to generate the required circuits from specification to layout with low-noise consideration. Process variations and layout effects are also simultaneously considered to generate the required circuits with high design yield. Furthermore, a user-friendly GUI is also provided to help users complete the design flow successfully and efficiently. As shown in the experimental results, this analog synthesis platform is able to generate the required circuits in seconds with low noise. The chip implementation result also verifies the capability of this tool to generate the required designs with fabricable quality.
{"title":"Low-noise analog synthesis platform for bio-signal acquisition system","authors":"Ying-Chi Lien, Ching-Mao Lee, Chih-Wei Li, Ban-Han Tsai, C. Liu","doi":"10.1109/VLSI-DAT.2015.7114568","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114568","url":null,"abstract":"Because the bio-signals are often very weak, they can be influenced by noise easily and become hard to distinguish. In this paper, an automatic analog synthesis platform is presented for bio-acquisition systems to generate the required circuits from specification to layout with low-noise consideration. Process variations and layout effects are also simultaneously considered to generate the required circuits with high design yield. Furthermore, a user-friendly GUI is also provided to help users complete the design flow successfully and efficiently. As shown in the experimental results, this analog synthesis platform is able to generate the required circuits in seconds with low noise. The chip implementation result also verifies the capability of this tool to generate the required designs with fabricable quality.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114524
Hong-Son Vu, Kuan-Hung Chen, Shih-Feng Sun, Tien-Mau Fong, Che-Wei Hsu, Lei Wang
Conventional active noise cancelling (ANC) headphones perform well in reducing the low-frequency noise and isolate high-frequency noise by earmuffs passively. These systems often use high-speed digital signal processors (DSPs) to cancel out the disturbing noise at such low frequencies, which result in a high-power dissipation for a commercial ANC headphone. This paper proposes a high-performance feedforward ANC architecture and implements a high-performance low power circuit design accordingly based on the filtered-x least mean square (FxLMS) adaptive algorithm. Experimental results show that the proposed high-performance circuit design can reduce disturbing noise of various frequency bands very well, and outperforms the existing works. After fabricating by using the TSMC 90nm CMOS technology, the proposed design can attenuate 15 dB for the broadband pink noise between 50-1500 Hz when operated at 10 MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.42 mW only.
{"title":"A power-efficient circuit design of feed-forward FxLMS active noise cancellation for in-ear headphones","authors":"Hong-Son Vu, Kuan-Hung Chen, Shih-Feng Sun, Tien-Mau Fong, Che-Wei Hsu, Lei Wang","doi":"10.1109/VLSI-DAT.2015.7114524","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114524","url":null,"abstract":"Conventional active noise cancelling (ANC) headphones perform well in reducing the low-frequency noise and isolate high-frequency noise by earmuffs passively. These systems often use high-speed digital signal processors (DSPs) to cancel out the disturbing noise at such low frequencies, which result in a high-power dissipation for a commercial ANC headphone. This paper proposes a high-performance feedforward ANC architecture and implements a high-performance low power circuit design accordingly based on the filtered-x least mean square (FxLMS) adaptive algorithm. Experimental results show that the proposed high-performance circuit design can reduce disturbing noise of various frequency bands very well, and outperforms the existing works. After fabricating by using the TSMC 90nm CMOS technology, the proposed design can attenuate 15 dB for the broadband pink noise between 50-1500 Hz when operated at 10 MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.42 mW only.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122530141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114563
C. Mao
Summary form only given. Green design becomes more important in these years. How to enhance the power efficiency is the mainstream of the SoC design. This work will talk about the challenges and possible solutions of each stage in the IC design flow, from the architecture level to the production level.
{"title":"Low-power IC design challenge","authors":"C. Mao","doi":"10.1109/VLSI-DAT.2015.7114563","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114563","url":null,"abstract":"Summary form only given. Green design becomes more important in these years. How to enhance the power efficiency is the mainstream of the SoC design. This work will talk about the challenges and possible solutions of each stage in the IC design flow, from the architecture level to the production level.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127767772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114500
J. Goh, Yen-Long Lee, Soon-Jyh Chang
This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.
{"title":"A dual-edge sampling CES delay-locked loop based clock and data recovery circuits","authors":"J. Goh, Yen-Long Lee, Soon-Jyh Chang","doi":"10.1109/VLSI-DAT.2015.7114500","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114500","url":null,"abstract":"This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm2 and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114529
Kai Chen, Young Hwan Kim
Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates. The proposed CSM consists of voltage-controlled current source, input and output parasitic capacitances, Miller capacitance and calibration input capacitance parallel to the characterized input capacitance. The calibration input capacitance helps to model the input node more accurately. In experiments, the proposed CSM outperformed the benchmark CSMs in the average root-mean squared error (RMSE) and the average 50%-to-50% gate delay error.
{"title":"Current source model of combinational logic gates for accurate gate-level circuit analysis and timing analysis","authors":"Kai Chen, Young Hwan Kim","doi":"10.1109/VLSI-DAT.2015.7114529","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114529","url":null,"abstract":"Many current source models (CSMs) have been proposed for the gate-level circuit analysis and timing analysis for sub-90-nm CMOS designs during the past decade. However, most of them may suffer from large delay errors for multiple-stages of combinational logic gates. This paper presents an extended CSM which can provide high accuracy in both single-stage and multiple-stage combinational logic gates. The proposed CSM consists of voltage-controlled current source, input and output parasitic capacitances, Miller capacitance and calibration input capacitance parallel to the characterized input capacitance. The calibration input capacitance helps to model the input node more accurately. In experiments, the proposed CSM outperformed the benchmark CSMs in the average root-mean squared error (RMSE) and the average 50%-to-50% gate delay error.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122101782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114577
Po-Yu Chien, Yuan-Hsiang Miao, Jiun-In Guo
This paper proposes a low-complexity design for 3D hand tracking, which can provide depth information and is able to work under critical backgrounds. This paper also proposes an effective way to segment hands out of entire image and also facilitates depth estimation of tracked hands in real-time by dualcamera systems. Multithreading and several techniques are applied to reduce computational complexity in proposed design. The final algorithm has been implemented both on PCs (with Intel Core i7 processor) and an embedded system (with ARM Cortex A9 processor). On PCs, it reaches 24 frames per second at VGA video. On the other hand, after reducing image size (i.e. QVGA video), it achieves the performance about 8 frames per second on PandaBoard embedded system.
{"title":"A 3D hand tracking design for gesture control in complex environments","authors":"Po-Yu Chien, Yuan-Hsiang Miao, Jiun-In Guo","doi":"10.1109/VLSI-DAT.2015.7114577","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114577","url":null,"abstract":"This paper proposes a low-complexity design for 3D hand tracking, which can provide depth information and is able to work under critical backgrounds. This paper also proposes an effective way to segment hands out of entire image and also facilitates depth estimation of tracked hands in real-time by dualcamera systems. Multithreading and several techniques are applied to reduce computational complexity in proposed design. The final algorithm has been implemented both on PCs (with Intel Core i7 processor) and an embedded system (with ARM Cortex A9 processor). On PCs, it reaches 24 frames per second at VGA video. On the other hand, after reducing image size (i.e. QVGA video), it achieves the performance about 8 frames per second on PandaBoard embedded system.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126550888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114509
J. Estupinan, A. Vachoux, J. Pascal
This paper focuses on the electro-thermal modeling of an electrical current sensor, based on the Rogowski Coil transducer. We exploit the multi-domain capabilities of VHDL-AMS together with geometrical Finite Element Analysis (FEA) to create a time-dependent parametrical model which is able to compute concurrently the thermal and electrical variables of the system. This is particularly convenient for evaluating the temperature effect in the analogue and digital signal processing of the sensor. Some key geometrical and inner material properties of the sensor and its environment, which are difficult, or even impossible to simulate dynamically in a classical lumped-element model, are taken into account in the proposed model. This modeling technique can be used to improve the accuracy in the design of the self-calibration circuit of the sensor.
{"title":"Electro-thermal modeling of a Rogowski coil sensor system","authors":"J. Estupinan, A. Vachoux, J. Pascal","doi":"10.1109/VLSI-DAT.2015.7114509","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114509","url":null,"abstract":"This paper focuses on the electro-thermal modeling of an electrical current sensor, based on the Rogowski Coil transducer. We exploit the multi-domain capabilities of VHDL-AMS together with geometrical Finite Element Analysis (FEA) to create a time-dependent parametrical model which is able to compute concurrently the thermal and electrical variables of the system. This is particularly convenient for evaluating the temperature effect in the analogue and digital signal processing of the sensor. Some key geometrical and inner material properties of the sensor and its environment, which are difficult, or even impossible to simulate dynamically in a classical lumped-element model, are taken into account in the proposed model. This modeling technique can be used to improve the accuracy in the design of the self-calibration circuit of the sensor.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123783212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One popular adaptive test approach is to reorder the test patterns according to their fault detection performance - by applying the more effective patterns first, the total test time can be significantly reduced. While very effective, the detection performance based approach fails to identify some high-quality test patterns and leaves them unused throughout the test application process. In this paper, we propose a test-application-count based learning technique to help identify high-quality test patterns. By ensuring that all patterns are applied for at least the specified number of times, the proposed technique finds more high-quality test patterns and moves them to the front of the test pattern list. Experimental results show that the proposed test-application-count based learning technique achieves 52% test time reduction (TTR) in average - a 12% improvement compared to the detection performance based approach.
{"title":"A test-application-count based learning technique for test time reduction","authors":"Guo-Yu Lin, Kun-Han Tsai, Jiun-Lang Huang, Wu-Tung Cheng","doi":"10.1109/VLSI-DAT.2015.7114507","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114507","url":null,"abstract":"One popular adaptive test approach is to reorder the test patterns according to their fault detection performance - by applying the more effective patterns first, the total test time can be significantly reduced. While very effective, the detection performance based approach fails to identify some high-quality test patterns and leaves them unused throughout the test application process. In this paper, we propose a test-application-count based learning technique to help identify high-quality test patterns. By ensuring that all patterns are applied for at least the specified number of times, the proposed technique finds more high-quality test patterns and moves them to the front of the test pattern list. Experimental results show that the proposed test-application-count based learning technique achieves 52% test time reduction (TTR) in average - a 12% improvement compared to the detection performance based approach.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131036352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114569
Song Jin, Songwei Pei, Yinhe Han, Huawei Li
Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multi-core chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or required per core voltage domain configuration. However, the former solution is difficult to find a single optimal VFI partition for diverse applications while the latter one suffers from high hardware cost. In this paper, we propose an energy optimization framework based on dynamically reconfigurable VFI (D-VFI). Our framework treats a small number of cores as dynamic cores (D-cores) and configures each of them with an independent voltage domain. At runtime, the D-cores can be pieced together with neighboring static VFIs. This can dynamically construct the optimal VFI partition for different kinds of applications, achieving more aggressive energy optimization under low cost. To identify the D-cores, we propose a D-VFI aware task scheduling and VFI partitioning algorithm. Moreover, we analyze all the VFI partitions to determine the optimal voltage scaling intervals which can accommodate performance degradation resulted from voltage scaling. Experimental results demonstrates that the effectiveness of the proposed scheme.
{"title":"On optimizing system energy of multi-core SoCs based on dynamically reconfigurable voltage-frequency island","authors":"Song Jin, Songwei Pei, Yinhe Han, Huawei Li","doi":"10.1109/VLSI-DAT.2015.7114569","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114569","url":null,"abstract":"Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multi-core chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or required per core voltage domain configuration. However, the former solution is difficult to find a single optimal VFI partition for diverse applications while the latter one suffers from high hardware cost. In this paper, we propose an energy optimization framework based on dynamically reconfigurable VFI (D-VFI). Our framework treats a small number of cores as dynamic cores (D-cores) and configures each of them with an independent voltage domain. At runtime, the D-cores can be pieced together with neighboring static VFIs. This can dynamically construct the optimal VFI partition for different kinds of applications, achieving more aggressive energy optimization under low cost. To identify the D-cores, we propose a D-VFI aware task scheduling and VFI partitioning algorithm. Moreover, we analyze all the VFI partitions to determine the optimal voltage scaling intervals which can accommodate performance degradation resulted from voltage scaling. Experimental results demonstrates that the effectiveness of the proposed scheme.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129232133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VLSI-DAT.2015.7114523
B. Kuo, B. Chen, Chia-Ming Tsai
This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265μm2.
{"title":"A 0.6V, 1.3GHz dynamic comparator with cross-coupled latches","authors":"B. Kuo, B. Chen, Chia-Ming Tsai","doi":"10.1109/VLSI-DAT.2015.7114523","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2015.7114523","url":null,"abstract":"This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265μm2.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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