Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550172
Sungwon Han, Kyung-Seob Kim, Chung-Hee Yu, M. Osterman, M. Pecht
This study evaluated the growth of tin whiskers on tin plated alloy 42 lead-frames and copper lead-frames stored in ambient conditions for 4 years, samples stored in ambient conditions after a post-bake treatment, and stored at 55plusmn1degC/85plusmn3% conditions for 3000 hours. Analysis was conducted to investigate the propensity and the mechanisms of growth.
{"title":"Observations of the spontaneous growth of tin whiskers in various reliability conditions","authors":"Sungwon Han, Kyung-Seob Kim, Chung-Hee Yu, M. Osterman, M. Pecht","doi":"10.1109/ECTC.2008.4550172","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550172","url":null,"abstract":"This study evaluated the growth of tin whiskers on tin plated alloy 42 lead-frames and copper lead-frames stored in ambient conditions for 4 years, samples stored in ambient conditions after a post-bake treatment, and stored at 55plusmn1degC/85plusmn3% conditions for 3000 hours. Analysis was conducted to investigate the propensity and the mechanisms of growth.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550149
S. Sosin, T. Zoumpoulidis, M. Bartek, L. Wang, R. Dekker, K. Jansen, L. Ernst
In this paper, development and characterization of a freestanding electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 mum is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a ~8 mum thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.
{"title":"Free-standing, parylene-sealed copper interconnect for stretchable silicon electronics","authors":"S. Sosin, T. Zoumpoulidis, M. Bartek, L. Wang, R. Dekker, K. Jansen, L. Ernst","doi":"10.1109/ECTC.2008.4550149","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550149","url":null,"abstract":"In this paper, development and characterization of a freestanding electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 mum is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a ~8 mum thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130537514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550178
H. Theuss, A. Koller, W. Kroninger, S. Schoenfelder, M. Petzold
We report on the development of a "dry" lasersingulation process for Si-wafers with back side metallization targeting small die sizes below 0.07 mm2. The dicing technology aims at improved manufacturing of diodes with thicknesses ranging from approx. 100 mum to 150 mum, die sizes down to 230 times 230 mum2 and metallized back side metallization layers used for solder die attach. We discuss the impact of the laser process on subsequent assembly processes as well as on the die itself. Particular emphasis is set on the laser induced modification of the mechanical properties within the wafer, e. g. the reduction of the die strength. For the wafer technology under evaluation, the laser process is considered to be superior to standard blade dicing approaches.
{"title":"Assessment of a lasersingulation process for Si-wafers with metallized back side and small die size","authors":"H. Theuss, A. Koller, W. Kroninger, S. Schoenfelder, M. Petzold","doi":"10.1109/ECTC.2008.4550178","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550178","url":null,"abstract":"We report on the development of a \"dry\" lasersingulation process for Si-wafers with back side metallization targeting small die sizes below 0.07 mm2. The dicing technology aims at improved manufacturing of diodes with thicknesses ranging from approx. 100 mum to 150 mum, die sizes down to 230 times 230 mum2 and metallized back side metallization layers used for solder die attach. We discuss the impact of the laser process on subsequent assembly processes as well as on the die itself. Particular emphasis is set on the laser induced modification of the mechanical properties within the wafer, e. g. the reduction of the die strength. For the wafer technology under evaluation, the laser process is considered to be superior to standard blade dicing approaches.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130920882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550235
J. Liao, Shengling Deng, K. Connor, V. Joyner, Z.R. Huang
In this paper, a dual split director quasi-yagi antenna is introduced for RF/FSO integration. Bare die laser diodes and photodetectors are assembled on the antenna directors on the duroid substrate. Coupling between RF and optical dual mode wireless communication system is analyzed.
{"title":"Antenna integration with laser diodes and photodetectors for a miniaturized dual-mode wireless transceiver","authors":"J. Liao, Shengling Deng, K. Connor, V. Joyner, Z.R. Huang","doi":"10.1109/ECTC.2008.4550235","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550235","url":null,"abstract":"In this paper, a dual split director quasi-yagi antenna is introduced for RF/FSO integration. Bare die laser diodes and photodetectors are assembled on the antenna directors on the duroid substrate. Coupling between RF and optical dual mode wireless communication system is analyzed.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131303784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549965
E. Davies-venn, T. Kamgaing
Two lumped element baluns designed using embedded inductors and capacitors are discussed in this paper. The structures designed for WiFi and mobile WiMAX applications have very small form-factors with surface area of 3 mm2 or less making them ideal for portable wireless communication devices such as mobile internet devices and ultra-mobile personal computers. The baluns, fabricated as part of a multi-layer FCBGA package substrate, also display very good electrical performance. The measured insertion loss and phase imbalances were lower than -0.85 dB and 3 degrees respectively for some implementations.
{"title":"LC-based WiFi and WiMAX Baluns embedded in a multilayer organic flip-chip ball grid array (FCBGA) package substrate","authors":"E. Davies-venn, T. Kamgaing","doi":"10.1109/ECTC.2008.4549965","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549965","url":null,"abstract":"Two lumped element baluns designed using embedded inductors and capacitors are discussed in this paper. The structures designed for WiFi and mobile WiMAX applications have very small form-factors with surface area of 3 mm2 or less making them ideal for portable wireless communication devices such as mobile internet devices and ultra-mobile personal computers. The baluns, fabricated as part of a multi-layer FCBGA package substrate, also display very good electrical performance. The measured insertion loss and phase imbalances were lower than -0.85 dB and 3 degrees respectively for some implementations.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550074
P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, Bernhard Wunderle, Bruno Michel, Herbert Reichl
3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.
{"title":"Through silicon via technology — processes and reliability for wafer-level 3D system integration","authors":"P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, Bernhard Wunderle, Bruno Michel, Herbert Reichl","doi":"10.1109/ECTC.2008.4550074","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550074","url":null,"abstract":"3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550255
W. Zhang, A. Matin, E. Beyne, W. Ruythooren
3D chip stacking technology requires repeated stacking of additional layers without remelting the bumps at lower levels of the stack. This can be achieved by transient liquid phase (TLP) bonding during which all solder is transformed into intermetallic compounds that have higher melting points than the solder itself. In this paper, we study Au/In reaction at different temperatures in order to develop a robust low temperature Au/In TLP bonding process. It is shown that the kinetics of intermetallic compound formation is diffusion-controlled, and the activation energy of Au/In reaction is temperature-dependent: 0.46 and 0.23 eV for temperatures above and below 150degC, respectively. Moreover, a thin Ti layer between Au and In is found to be an effective diffusion barrier at low temperature, while it does not inhibit intermetallic joint formation at elevated temperatures during flip-chip bonding. This allows us to control the intermetallic formation during the distinct stages of TLP bonding process. In addition, a minimal In thickness of 0.5 mum is required in order to enable TLP bonding. Finally, Au/In TLP joints of phi40 to phi60 mum are successfully fabricated at 180degC and with very small solder volume (1 mum thick). The shear strength of our phi40-60 mum joints is in the range of 6-20 MPa, and the electrical connection yield is 100% for the daisy chain containing 1380 bumps with a diameter of 60 mum.
{"title":"Optimizing Au and In micro-bumping for 3D chip stacking","authors":"W. Zhang, A. Matin, E. Beyne, W. Ruythooren","doi":"10.1109/ECTC.2008.4550255","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550255","url":null,"abstract":"3D chip stacking technology requires repeated stacking of additional layers without remelting the bumps at lower levels of the stack. This can be achieved by transient liquid phase (TLP) bonding during which all solder is transformed into intermetallic compounds that have higher melting points than the solder itself. In this paper, we study Au/In reaction at different temperatures in order to develop a robust low temperature Au/In TLP bonding process. It is shown that the kinetics of intermetallic compound formation is diffusion-controlled, and the activation energy of Au/In reaction is temperature-dependent: 0.46 and 0.23 eV for temperatures above and below 150degC, respectively. Moreover, a thin Ti layer between Au and In is found to be an effective diffusion barrier at low temperature, while it does not inhibit intermetallic joint formation at elevated temperatures during flip-chip bonding. This allows us to control the intermetallic formation during the distinct stages of TLP bonding process. In addition, a minimal In thickness of 0.5 mum is required in order to enable TLP bonding. Finally, Au/In TLP joints of phi40 to phi60 mum are successfully fabricated at 180degC and with very small solder volume (1 mum thick). The shear strength of our phi40-60 mum joints is in the range of 6-20 MPa, and the electrical connection yield is 100% for the daisy chain containing 1380 bumps with a diameter of 60 mum.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"104 S2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550046
A. Kundu, M. Megahed, D. Schmidt
We have investigated the existing integrated passive device (IPD) technologies for cost effective IPD solutions for discrete radio frequency (RF) module. Based upon the investigation in terms of cost, size, performance & technology maturity, it comes out that silicon, glass & LTCC are the suitable technologies. We have designed IPDs using these technologies having same foot print to satisfy Intel Wi-MAX specs. Have taped out, validated the samples and made an electrical performance and cost comparison among three technologies. Result shows that Si_IPD & Glass_IPD both have well enough electrical performance required for Wi_MAX solution at lower cost and equivalent size compared to LTCC.
{"title":"Comparison and analysis of integrated passive device technologies for wireless radio frequency module","authors":"A. Kundu, M. Megahed, D. Schmidt","doi":"10.1109/ECTC.2008.4550046","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550046","url":null,"abstract":"We have investigated the existing integrated passive device (IPD) technologies for cost effective IPD solutions for discrete radio frequency (RF) module. Based upon the investigation in terms of cost, size, performance & technology maturity, it comes out that silicon, glass & LTCC are the suitable technologies. We have designed IPDs using these technologies having same foot print to satisfy Intel Wi-MAX specs. Have taped out, validated the samples and made an electrical performance and cost comparison among three technologies. Result shows that Si_IPD & Glass_IPD both have well enough electrical performance required for Wi_MAX solution at lower cost and equivalent size compared to LTCC.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121086840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549993
M. Ahmad, K.C. Liu, C.J. Lee, J. Priest, S. Pak, S. Narasimhan, M. Nagar, J. Xue
A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.
{"title":"Impact of system level thermal solution on the interconnect reliability of high performance and high heat dissipating CSP package","authors":"M. Ahmad, K.C. Liu, C.J. Lee, J. Priest, S. Pak, S. Narasimhan, M. Nagar, J. Xue","doi":"10.1109/ECTC.2008.4549993","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549993","url":null,"abstract":"A custom SRAM was developed for high performance and high reliability network switching applications using 90 nm low-k silicon technology. It is a 13.6 mm x 18.4 mm flip chip chip scale package (CSP) with a 11.12 mm x 16.36 mm die. The package has 838 BGA balls at 0.5 mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high aspect ratio of the die-to-package area leaves very little room for underfill dispensing and no room for a stiffener ring attachment. In addition, the high heat dissipation of the device requires the use of a metal heatspreader flip chip package as opposed to an overmolded flip chip package solution. The package design coupled with a large die and high I/O count presents significant challenges in the package assembly process and interconnect reliability. A lower glass transition (Tg) underfill material is typically preferred to reduce package warpage and to reduce the stress in the low-k dielectric caused by CTE mismatch between the silicon die and package materials. However, for high power applications where the operating temperature is very close to the underfill Tg, the system level thermal solution must be optimized for improved cooling while at the same time ensuring that the interconnect and package reliability at the system application level is not compromised. In this paper, both Experimental and Finite Element analyses were performed to investigate the key system level thermal solution design parameters that impact package interconnect reliability. The effect of heatsink compressive loading on the thermal excursions, the underfill material, and the interconnect metallurgy was evaluated. In addition to the compressive loading effect, the effect of the heatsink attachment method on interconnect reliability was also investigated. Three dimensional fatigue analyses were performed to derive the hysteresis loops for different test cases, to understand the interaction between the heatsink attachment method and the package material and design variables. The finite element model data was benchmarked against experimental data to determine the optimal design conditions for effective thermal cooling without compromising interconnect reliability. Real time pressure measurement and failure analysis were also performed to understand the potential failure modes and failure rates occurring in the system level design. Finally, recommendations are provided on ways to mitigate critical failure modes in the thermal and interconnect design of such complex flip chip CSP packages at the system level.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126626907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550101
E. Wolak, K. Kuppuswamy, J. Harrison, Xu Jin, Hanxuan Li, B. Fidric, R. Miller, P. Cross, T. Towe, T. Truchan, Hoa Nguyen, C. Edirisinghe
This paper describes reliability data for multi-stripe arrays of laser diodes with limited emitter count. The empirical behavior of these arrays is compared with a model based on independent random failures of the individual stripes in a multi-element array operating in an ensemble mode. Such reliability data is of particular interest for multi-mode multi- stripe laser pump modules operating in the 910 nm to 990 nm wavelength range.
{"title":"Highly reliable multi stripe laser diodes","authors":"E. Wolak, K. Kuppuswamy, J. Harrison, Xu Jin, Hanxuan Li, B. Fidric, R. Miller, P. Cross, T. Towe, T. Truchan, Hoa Nguyen, C. Edirisinghe","doi":"10.1109/ECTC.2008.4550101","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550101","url":null,"abstract":"This paper describes reliability data for multi-stripe arrays of laser diodes with limited emitter count. The empirical behavior of these arrays is compared with a model based on independent random failures of the individual stripes in a multi-element array operating in an ensemble mode. Such reliability data is of particular interest for multi-mode multi- stripe laser pump modules operating in the 910 nm to 990 nm wavelength range.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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