Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550273
Xiaohui Song, Sheng Liu, Han Yan, Z. Gan
An ab initio approach of Car-Parrinello molecular dynamics is used to study the chemisorption of a single oxygen atom on outer surface of zigzag single-wall carbon nanotubes under various uniaxial strains and bending deformation. The effect of mechanical deformation on adsorption of oxygen atom on CNT is demonstrated by linking the chemical reactivity and structural deformation. The adsorption energy Eb and pyramidalization angle thetasP are obtained by structural relaxation calculations, and ground- state electronic structures are described according to density functional theory (DFT) within a plane-wave pseudopotential framework. Our results show that the surface reactivity of CNT is mostly determined by its pyramidalization angle of carbon atom. For bending SWCNT, both Eb and thetasP vary with adsorption sites, the Eb is higher at sites with larger pyramidalization angle. An approximate linear relation of strain and adsorption energy can be obtained. It is indicated that the structure of CNT is crucial for its surface reactivity, and the mechanical deformation can be a method for controlling the surface reactivity of CNT and offering adsorption site selectivity as the adsorption is facilitated on the sites with higher pyramidalization angle.
{"title":"Effects of mechanical deformation on outer surface reactivity of carbon nanotubes","authors":"Xiaohui Song, Sheng Liu, Han Yan, Z. Gan","doi":"10.1109/ECTC.2008.4550273","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550273","url":null,"abstract":"An ab initio approach of Car-Parrinello molecular dynamics is used to study the chemisorption of a single oxygen atom on outer surface of zigzag single-wall carbon nanotubes under various uniaxial strains and bending deformation. The effect of mechanical deformation on adsorption of oxygen atom on CNT is demonstrated by linking the chemical reactivity and structural deformation. The adsorption energy Eb and pyramidalization angle thetasP are obtained by structural relaxation calculations, and ground- state electronic structures are described according to density functional theory (DFT) within a plane-wave pseudopotential framework. Our results show that the surface reactivity of CNT is mostly determined by its pyramidalization angle of carbon atom. For bending SWCNT, both Eb and thetasP vary with adsorption sites, the Eb is higher at sites with larger pyramidalization angle. An approximate linear relation of strain and adsorption energy can be obtained. It is indicated that the structure of CNT is crucial for its surface reactivity, and the mechanical deformation can be a method for controlling the surface reactivity of CNT and offering adsorption site selectivity as the adsorption is facilitated on the sites with higher pyramidalization angle.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114906209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550175
B. Dang, D. Shih, Stephen Buchwalter, Cornelia Tsang, Chirag S. Patel, J. Knickerbocker, P. Gruber, Sarah Knickerbocker, J. Garant, Krystyna Semkow, K. Ruhmer, E. Hughlett
Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.
{"title":"50μm pitch Pb-free micro-bumps by C4NP technology","authors":"B. Dang, D. Shih, Stephen Buchwalter, Cornelia Tsang, Chirag S. Patel, J. Knickerbocker, P. Gruber, Sarah Knickerbocker, J. Garant, Krystyna Semkow, K. Ruhmer, E. Hughlett","doi":"10.1109/ECTC.2008.4550175","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550175","url":null,"abstract":"Controlled collapse chip connection new process (C4NP) is currently used in IBM manufacturing for all 300 mm Pb-free wafer bumping for flip chip packages. In this study, the extendibility of C4NP technology to ultra fine pitch applications has been explored. Reusable C4NP glass molds were fabricated and characterized for 50 mum pitch application. Mold fill and wafer transfer with Pb-free solders have been demonstrated using both 200 mm and 300 mm wafers in a manufacturing environment. Significant improvement in bump yield was achieved for these early demonstrations of fine pitch interconnections through process optimization and contamination control. Challenge in wafer inspection metrology is discussed for the 50 mum pitch micro-bumps. Mechanical strength of the C4NP micro-bumps has been characterized using test dies with a full area array of micro-bumps.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"65 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123549415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549980
T. Shibata, A. Takahashi
We propose a flexible opto-electronic circuit board (FOECB) for in-device interconnection, which is combined with a flexible printed circuit (FPC) with flexible optical waveguides having 45deg mirrors for 90deg beam turning using adhesive film. The fabricated prototype shows total optical loss of 3.7 dB, and the prototype, which mounted a 4-ch vertical-cavity surface-emitting laser (VCSEL) array and a 4-ch photodiode (PD) array, successfully demonstrated optical signal transmission at a data rate of 10 Gbps/ch. These results show that the proposed prototype has considerable potential to realize practical FOECB for in-device interconnection.
{"title":"Flexible opto-electronic circuit board for in-device interconnection","authors":"T. Shibata, A. Takahashi","doi":"10.1109/ECTC.2008.4549980","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549980","url":null,"abstract":"We propose a flexible opto-electronic circuit board (FOECB) for in-device interconnection, which is combined with a flexible printed circuit (FPC) with flexible optical waveguides having 45deg mirrors for 90deg beam turning using adhesive film. The fabricated prototype shows total optical loss of 3.7 dB, and the prototype, which mounted a 4-ch vertical-cavity surface-emitting laser (VCSEL) array and a 4-ch photodiode (PD) array, successfully demonstrated optical signal transmission at a data rate of 10 Gbps/ch. These results show that the proposed prototype has considerable potential to realize practical FOECB for in-device interconnection.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550255
W. Zhang, A. Matin, E. Beyne, W. Ruythooren
3D chip stacking technology requires repeated stacking of additional layers without remelting the bumps at lower levels of the stack. This can be achieved by transient liquid phase (TLP) bonding during which all solder is transformed into intermetallic compounds that have higher melting points than the solder itself. In this paper, we study Au/In reaction at different temperatures in order to develop a robust low temperature Au/In TLP bonding process. It is shown that the kinetics of intermetallic compound formation is diffusion-controlled, and the activation energy of Au/In reaction is temperature-dependent: 0.46 and 0.23 eV for temperatures above and below 150degC, respectively. Moreover, a thin Ti layer between Au and In is found to be an effective diffusion barrier at low temperature, while it does not inhibit intermetallic joint formation at elevated temperatures during flip-chip bonding. This allows us to control the intermetallic formation during the distinct stages of TLP bonding process. In addition, a minimal In thickness of 0.5 mum is required in order to enable TLP bonding. Finally, Au/In TLP joints of phi40 to phi60 mum are successfully fabricated at 180degC and with very small solder volume (1 mum thick). The shear strength of our phi40-60 mum joints is in the range of 6-20 MPa, and the electrical connection yield is 100% for the daisy chain containing 1380 bumps with a diameter of 60 mum.
{"title":"Optimizing Au and In micro-bumping for 3D chip stacking","authors":"W. Zhang, A. Matin, E. Beyne, W. Ruythooren","doi":"10.1109/ECTC.2008.4550255","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550255","url":null,"abstract":"3D chip stacking technology requires repeated stacking of additional layers without remelting the bumps at lower levels of the stack. This can be achieved by transient liquid phase (TLP) bonding during which all solder is transformed into intermetallic compounds that have higher melting points than the solder itself. In this paper, we study Au/In reaction at different temperatures in order to develop a robust low temperature Au/In TLP bonding process. It is shown that the kinetics of intermetallic compound formation is diffusion-controlled, and the activation energy of Au/In reaction is temperature-dependent: 0.46 and 0.23 eV for temperatures above and below 150degC, respectively. Moreover, a thin Ti layer between Au and In is found to be an effective diffusion barrier at low temperature, while it does not inhibit intermetallic joint formation at elevated temperatures during flip-chip bonding. This allows us to control the intermetallic formation during the distinct stages of TLP bonding process. In addition, a minimal In thickness of 0.5 mum is required in order to enable TLP bonding. Finally, Au/In TLP joints of phi40 to phi60 mum are successfully fabricated at 180degC and with very small solder volume (1 mum thick). The shear strength of our phi40-60 mum joints is in the range of 6-20 MPa, and the electrical connection yield is 100% for the daisy chain containing 1380 bumps with a diameter of 60 mum.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"104 S2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550074
P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, Bernhard Wunderle, Bruno Michel, Herbert Reichl
3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.
{"title":"Through silicon via technology — processes and reliability for wafer-level 3D system integration","authors":"P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, Bernhard Wunderle, Bruno Michel, Herbert Reichl","doi":"10.1109/ECTC.2008.4550074","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550074","url":null,"abstract":"3D integration is a rapidly growing topic in the semiconductor industry that encompasses different types of technologies. The paper addresses one of the most promising technologies which uses through silicon vias (TSV) for interconnecting stacked devices on wafer-level to perform high density interconnects with a good electrical performance at the smallest form factor for 3D architectures. Fraunhofer IZM developed a post frontend 3D integration process, the so- called ICV-SLID technology based on metal bonding using solid-liquid-interdiffusion (SLID) soldering. The SLID metal system provides the mechanical and the electrical connection, both in one single step. The ICV-SLID fabrication process is well suited for the cost-effective production of both, high- performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems. The latter preferably in combination with wafer-level die stacking, as e.g. Thin Chip Integration (TCI) or SnAg-microbump technologies. The fabrication of distributed wireless sensor systems (e. g. e-CUBESreg) is a typical example for the need of such mixed approaches.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550084
D. Shi, Xuejun Fan, B. Xie
In order to devise an equivalent accelerated moisture sensitivity test, the JEDEC specification J-STD-020C has recommended an accelerated preconditioning time of 40 hrs exposure under 60degC / 60% RH, which is considered equivalent to the standard moisture sensitivity level 3 (MSL-3) of 216 hrs soak time under 30degC / 60% RH. However, the existing methodology for the accelerated moisture sensitivity test was developed based on the equivalency of local moisture concentration at the interest of location for leaded packages only. The failure mechanism is restricted to the potential delamination between mold compound and leadframe. In addition, such an equivalency requires the activation energy of molding compound for moisture diffusion in the range of 0.4 - 0.48 eV. This paper introduces a new method to accelerate JEDEC/IPC moisture sensitivity level testing. The methodology is developed based on the equivalency of both local moisture concentration and overall moisture distribution of packages. The local moisture concentration equivalency ensures identical adhesion strength and vapor pressure at interfaces of the interest, and the overall moisture distribution equivalency results in the same condition of applied driving forces, such as thermal and hygroscopic stresses, during reflow. In our previous study (Xie et al., 2007), this methodology was applied to a molded matrix array package, and an accelerated soak time subjected to 60degC / 60% RH was established. In this paper, the further reduction of soak time using 85degC / 60% RH is investigated. An ultra-thin stacked-die chip scale package (CSP) is used as the test vehicle. Extensive experiments have been carried out to obtain the failure rate as function of soak time under various environmental conditions. Finite element analysis was performed to obtain the equivalency conditions. According to finite element modeling results, it has been found that, at 70hrs under 60degC / 60% RH and 45 hrs under 85degC / 60% RH, respectively, both the local moisture concentration at critical interface and overall moisture distribution of package become identical to that under the standard MSL-3. Such an equivalency of the new accelerated test conditions has been proven by the test results. Failure site and failure mode indicates that the proposed accelerated tests are well correlated with the standard MSL-3. The new methodology can be extended to other packages.
{"title":"A new method for equivalent acceleration of JEDEC moisture sensitivity levels","authors":"D. Shi, Xuejun Fan, B. Xie","doi":"10.1109/ECTC.2008.4550084","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550084","url":null,"abstract":"In order to devise an equivalent accelerated moisture sensitivity test, the JEDEC specification J-STD-020C has recommended an accelerated preconditioning time of 40 hrs exposure under 60degC / 60% RH, which is considered equivalent to the standard moisture sensitivity level 3 (MSL-3) of 216 hrs soak time under 30degC / 60% RH. However, the existing methodology for the accelerated moisture sensitivity test was developed based on the equivalency of local moisture concentration at the interest of location for leaded packages only. The failure mechanism is restricted to the potential delamination between mold compound and leadframe. In addition, such an equivalency requires the activation energy of molding compound for moisture diffusion in the range of 0.4 - 0.48 eV. This paper introduces a new method to accelerate JEDEC/IPC moisture sensitivity level testing. The methodology is developed based on the equivalency of both local moisture concentration and overall moisture distribution of packages. The local moisture concentration equivalency ensures identical adhesion strength and vapor pressure at interfaces of the interest, and the overall moisture distribution equivalency results in the same condition of applied driving forces, such as thermal and hygroscopic stresses, during reflow. In our previous study (Xie et al., 2007), this methodology was applied to a molded matrix array package, and an accelerated soak time subjected to 60degC / 60% RH was established. In this paper, the further reduction of soak time using 85degC / 60% RH is investigated. An ultra-thin stacked-die chip scale package (CSP) is used as the test vehicle. Extensive experiments have been carried out to obtain the failure rate as function of soak time under various environmental conditions. Finite element analysis was performed to obtain the equivalency conditions. According to finite element modeling results, it has been found that, at 70hrs under 60degC / 60% RH and 45 hrs under 85degC / 60% RH, respectively, both the local moisture concentration at critical interface and overall moisture distribution of package become identical to that under the standard MSL-3. Such an equivalency of the new accelerated test conditions has been proven by the test results. Failure site and failure mode indicates that the proposed accelerated tests are well correlated with the standard MSL-3. The new methodology can be extended to other packages.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128202718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4549965
E. Davies-venn, T. Kamgaing
Two lumped element baluns designed using embedded inductors and capacitors are discussed in this paper. The structures designed for WiFi and mobile WiMAX applications have very small form-factors with surface area of 3 mm2 or less making them ideal for portable wireless communication devices such as mobile internet devices and ultra-mobile personal computers. The baluns, fabricated as part of a multi-layer FCBGA package substrate, also display very good electrical performance. The measured insertion loss and phase imbalances were lower than -0.85 dB and 3 degrees respectively for some implementations.
{"title":"LC-based WiFi and WiMAX Baluns embedded in a multilayer organic flip-chip ball grid array (FCBGA) package substrate","authors":"E. Davies-venn, T. Kamgaing","doi":"10.1109/ECTC.2008.4549965","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4549965","url":null,"abstract":"Two lumped element baluns designed using embedded inductors and capacitors are discussed in this paper. The structures designed for WiFi and mobile WiMAX applications have very small form-factors with surface area of 3 mm2 or less making them ideal for portable wireless communication devices such as mobile internet devices and ultra-mobile personal computers. The baluns, fabricated as part of a multi-layer FCBGA package substrate, also display very good electrical performance. The measured insertion loss and phase imbalances were lower than -0.85 dB and 3 degrees respectively for some implementations.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128918545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550149
S. Sosin, T. Zoumpoulidis, M. Bartek, L. Wang, R. Dekker, K. Jansen, L. Ernst
In this paper, development and characterization of a freestanding electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 mum is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a ~8 mum thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.
{"title":"Free-standing, parylene-sealed copper interconnect for stretchable silicon electronics","authors":"S. Sosin, T. Zoumpoulidis, M. Bartek, L. Wang, R. Dekker, K. Jansen, L. Ernst","doi":"10.1109/ECTC.2008.4550149","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550149","url":null,"abstract":"In this paper, development and characterization of a freestanding electroplated copper interconnect for applications in flexible and stretchable electronics is presented. The copper layer with typical thickness of 5 mum is plated into a photoresist mould realizing meander and mesh-like patterns. These are subsequently released resulting in a free-standing electrical interconnect that is optionally conformally coated by a ~8 mum thick Parylene N layer. Parylene sealing provides electrical insulation and increases rigidity of the structures. Tensile tests on fabricated samples have shown the elongation capability up to 300% for the mesh design and more than 1000% for the meander design. The Parylene coated samples showed increased rigidity but about 50% reduced elongation. Furthermore, parameterized FEM simulations were performed in order to estimate stress levels for different geometries under tensile stress.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130537514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550178
H. Theuss, A. Koller, W. Kroninger, S. Schoenfelder, M. Petzold
We report on the development of a "dry" lasersingulation process for Si-wafers with back side metallization targeting small die sizes below 0.07 mm2. The dicing technology aims at improved manufacturing of diodes with thicknesses ranging from approx. 100 mum to 150 mum, die sizes down to 230 times 230 mum2 and metallized back side metallization layers used for solder die attach. We discuss the impact of the laser process on subsequent assembly processes as well as on the die itself. Particular emphasis is set on the laser induced modification of the mechanical properties within the wafer, e. g. the reduction of the die strength. For the wafer technology under evaluation, the laser process is considered to be superior to standard blade dicing approaches.
{"title":"Assessment of a lasersingulation process for Si-wafers with metallized back side and small die size","authors":"H. Theuss, A. Koller, W. Kroninger, S. Schoenfelder, M. Petzold","doi":"10.1109/ECTC.2008.4550178","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550178","url":null,"abstract":"We report on the development of a \"dry\" lasersingulation process for Si-wafers with back side metallization targeting small die sizes below 0.07 mm2. The dicing technology aims at improved manufacturing of diodes with thicknesses ranging from approx. 100 mum to 150 mum, die sizes down to 230 times 230 mum2 and metallized back side metallization layers used for solder die attach. We discuss the impact of the laser process on subsequent assembly processes as well as on the die itself. Particular emphasis is set on the laser induced modification of the mechanical properties within the wafer, e. g. the reduction of the die strength. For the wafer technology under evaluation, the laser process is considered to be superior to standard blade dicing approaches.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130920882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-27DOI: 10.1109/ECTC.2008.4550027
N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Zhang Wu, Yang Rui, L. Ebin
Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.
{"title":"Development of 3D silicon module with TSV for system in packaging","authors":"N. Khan, V. S. Rao, S. Lim, H. We, V. Lee, Zhang Wu, Yang Rui, L. Ebin","doi":"10.1109/ECTC.2008.4550027","DOIUrl":"https://doi.org/10.1109/ECTC.2008.4550027","url":null,"abstract":"Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. Multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5 GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (- 40/125degC) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500 G & 0.5 ms pulse duration. Thermal cycle test results showed no solder joint failure.","PeriodicalId":378788,"journal":{"name":"2008 58th Electronic Components and Technology Conference","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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