Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452175
Liu Ji-zhi, Zhang Qunhao, Yang Kai, Zeng Yaohui, Liu Zhiwei
The trigger voltage of the HBT device is important for ESD protection. A method of adjusting the trigger voltage of SiGe Heterojunction Bipolar Transistor (HBT) device is proposed in this paper. The simulation and experiment results show that the trigger voltage of HBT can be simply adjusted by varying the emitter junction area.
{"title":"A Simple Method of Adjusting Trigger Voltage of HBT Device for ESD Protection","authors":"Liu Ji-zhi, Zhang Qunhao, Yang Kai, Zeng Yaohui, Liu Zhiwei","doi":"10.1109/IPFA.2018.8452175","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452175","url":null,"abstract":"The trigger voltage of the HBT device is important for ESD protection. A method of adjusting the trigger voltage of SiGe Heterojunction Bipolar Transistor (HBT) device is proposed in this paper. The simulation and experiment results show that the trigger voltage of HBT can be simply adjusted by varying the emitter junction area.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123889416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452614
Ghil-geun Oh, Si-Jeong Kim, Kyeong-Ju Jin, Shin- Young Jung, Brandon Lee
SCAN failure analysis that occurred only in the high voltage region was analyzed through in-circuit probing using laser voltage probing (LVP) technique in 10nm process. LVP results provided that high wire resistance of 4th metal layer had lead hold violation between launch and capture clock paths. This implies the importance of Back-End-Of-Line (BEOL) information that is monitored in mass production and design phase in high scaled process.
{"title":"Impact of Wire RC Based on High Voltage SCAN Failure Analysis in 10nm Process","authors":"Ghil-geun Oh, Si-Jeong Kim, Kyeong-Ju Jin, Shin- Young Jung, Brandon Lee","doi":"10.1109/IPFA.2018.8452614","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452614","url":null,"abstract":"SCAN failure analysis that occurred only in the high voltage region was analyzed through in-circuit probing using laser voltage probing (LVP) technique in 10nm process. LVP results provided that high wire resistance of 4th metal layer had lead hold violation between launch and capture clock paths. This implies the importance of Back-End-Of-Line (BEOL) information that is monitored in mass production and design phase in high scaled process.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114229731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452577
Lee Wei Cheat, Lim Saw Sing
Here we report a novel approach on how to differentiate the copper oxidation state based on their colors. A series of analyses are carried out in order to determine the correlation between the state of copper oxides and their colors by using X-ray photoelectron spectroscopy (XPS). Our analysis results reveal that the light and dark brownish colored copper areas are formed by different copper oxide compositions whereby dark colored copper area consisted a mixture of Cu2o and CuO, whilst the light colored copper area is dominated by Cu2o with trace of CuO.
{"title":"Copper Discoloration: Correlation Between Copper Oxidation States and Their Colors","authors":"Lee Wei Cheat, Lim Saw Sing","doi":"10.1109/IPFA.2018.8452577","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452577","url":null,"abstract":"Here we report a novel approach on how to differentiate the copper oxidation state based on their colors. A series of analyses are carried out in order to determine the correlation between the state of copper oxides and their colors by using X-ray photoelectron spectroscopy (XPS). Our analysis results reveal that the light and dark brownish colored copper areas are formed by different copper oxide compositions whereby dark colored copper area consisted a mixture of Cu2o and CuO, whilst the light colored copper area is dominated by Cu2o with trace of CuO.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116182067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452541
Rupa Kamoji, A. Oberai
The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 2.5D and 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die packages. The high level of functional integration and the complex package architecture in these, pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. Various FA tools available the industry provide key data for the fault isolation in packages. Very often, one need to correlate the package level results from tool across the entire system for accurate fault isolation. This means, the results must be taken across the system and perform analysis at each level in the system. In this paper, we are presenting case studies for different methods to perform analysis across the system for accurate fault isolation.
{"title":"Fault Isolation of 2.5D and 3D Packages through Analysis Across Entire System","authors":"Rupa Kamoji, A. Oberai","doi":"10.1109/IPFA.2018.8452541","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452541","url":null,"abstract":"The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 2.5D and 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die packages. The high level of functional integration and the complex package architecture in these, pose a significant challenge for conventional Fault Isolation (FI) and Failure analysis (FA) methods. Various FA tools available the industry provide key data for the fault isolation in packages. Very often, one need to correlate the package level results from tool across the entire system for accurate fault isolation. This means, the results must be taken across the system and perform analysis at each level in the system. In this paper, we are presenting case studies for different methods to perform analysis across the system for accurate fault isolation.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452173
J. Bi, Yuan Duan, Feng Zhang, Ming Liu
Total ionizing dose (TID) induced upset errors in Hf02-based resistive-random-access-memory (RRAM) with 1T1R storage cell structure are investigated. Radiation-induced leakage current in the access transistors on the same bit-lines causes a read decision failure and bit errors observed during TID irradiation experiments. This is verified by testkeys and HSPICE simulations based on the actual circuit structure of the 1 Mb RRAM.
{"title":"Total Ionizing Dose Effects of 1 Mb RfO2-based Resistive-Random-Access-Memory","authors":"J. Bi, Yuan Duan, Feng Zhang, Ming Liu","doi":"10.1109/IPFA.2018.8452173","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452173","url":null,"abstract":"Total ionizing dose (TID) induced upset errors in Hf02-based resistive-random-access-memory (RRAM) with 1T1R storage cell structure are investigated. Radiation-induced leakage current in the access transistors on the same bit-lines causes a read decision failure and bit errors observed during TID irradiation experiments. This is verified by testkeys and HSPICE simulations based on the actual circuit structure of the 1 Mb RRAM.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452525
Y.-H. Huang, P. Liao, Y. Lee, M. J. Chen, T. Ho, Lucy Chang
Hot-carrier-injection (HCI) effect is expected to well correlate with substrate current $(mathrm{I}_{mathrm{SUB}})$. However, in high-voltage (HV) device which features extended lightly-doped drain region (Ndrift), two $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peaks are frequently observed and found to have different HCI degradation. Our data showed that the worst-case HCI after long term stress doesn't necessarily occur at largest $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ which is usually found at full VG operation due to Kirk-effect. The HCI dependence on $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peak location in HV device is further investigated through TCAD simulation. Our study proved the changes in impact ionization location under 2nd$mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peak by Kirk-effect, thus leads to less $mathrm{Id}_{mathrm{lin}}$ degradation in long term stress. Nit generation at pinch-off point is found to alter IIG (impact-ionization generation) location at HV high resistance drift region and could be explained through IIG simulation by TCAD.
{"title":"Investigation of Kirk-Effect Induced Hot-Carrier-Injection in High-Voltage Power Devices","authors":"Y.-H. Huang, P. Liao, Y. Lee, M. J. Chen, T. Ho, Lucy Chang","doi":"10.1109/IPFA.2018.8452525","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452525","url":null,"abstract":"Hot-carrier-injection (HCI) effect is expected to well correlate with substrate current $(mathrm{I}_{mathrm{SUB}})$. However, in high-voltage (HV) device which features extended lightly-doped drain region (Ndrift), two $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peaks are frequently observed and found to have different HCI degradation. Our data showed that the worst-case HCI after long term stress doesn't necessarily occur at largest $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ which is usually found at full VG operation due to Kirk-effect. The HCI dependence on $mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peak location in HV device is further investigated through TCAD simulation. Our study proved the changes in impact ionization location under 2nd$mathrm{I}_{mathrm{S}mathrm{U}mathrm{B}}$ peak by Kirk-effect, thus leads to less $mathrm{Id}_{mathrm{lin}}$ degradation in long term stress. Nit generation at pinch-off point is found to alter IIG (impact-ionization generation) location at HV high resistance drift region and could be explained through IIG simulation by TCAD.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134559961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452503
Y. Shen, Ye Chen, Kok Wah Lee, Jie Zhu, Z. Mo
In this work we reported a work flow of de-layering method by using glancing angle FIB milling for IC failure analysis. This method doesn't require cleaving the sample cross-section which increases risk of damaging target structure. Instead, a combination of precise laser ablation and FIB milling is used to create a large viewing window before glancing angle FIB milling. Our results demonstrated that the method can become useful alternative of conventional mechanical and/or chemical polishing and were successfully applied in several case studies for analyzing embedded defect or passive voltage contrast (PVC) fault isolation.
{"title":"Glancing Angle FIB De-layering for Embedded Defect and PVC Fault Isolation Analysis","authors":"Y. Shen, Ye Chen, Kok Wah Lee, Jie Zhu, Z. Mo","doi":"10.1109/IPFA.2018.8452503","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452503","url":null,"abstract":"In this work we reported a work flow of de-layering method by using glancing angle FIB milling for IC failure analysis. This method doesn't require cleaving the sample cross-section which increases risk of damaging target structure. Instead, a combination of precise laser ablation and FIB milling is used to create a large viewing window before glancing angle FIB milling. Our results demonstrated that the method can become useful alternative of conventional mechanical and/or chemical polishing and were successfully applied in several case studies for analyzing embedded defect or passive voltage contrast (PVC) fault isolation.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131570356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452519
A. Teo, A. G. Boon, N. H. Peng, Chen Chang Qing, Xu Nai Yun, N. Dayanand, Tam Yong Seng, Mai Zhi Hong, J. Lam
In this paper, a low yield case relating to IDD leakage at active mode due to the systematic breakdown signature consistently at the top MIM edge was studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP probing, layout path tracing, FIB circuit edit, SEM XTEM and top down PFA methodology together with Fab investigation are used to understand the root cause as well as failure mechanism. This paper highlights that there are 2 types of leakage (high leakage in mA and low leakage in uA). The high leakage dies revealed spot directly at the MIM cap and anomaly can be observed at the MIM edge. However, for the low level leakage, hotspot was seen at the PMOS transistor and NOT at the MIM Cap. Besides layout tracing that enable to pinpoint the suspected MIM cap, 2 types of simulation (Intentionally induced damage and FIB Circuit Edit) were performed to prove and validate the MIM defect is the only root cause for this low yield issue and the RF circuitry has no contribution to it. Additionally, top down PFA methodology was engaged to reveal the physical evidence of the damage at the edge of the MIM. This confirmed that both type of leakage are due to similar MIM breakdown issue.
{"title":"Failure Analysis Methodology on Systematic MIM failure in Wafer Fabrication","authors":"A. Teo, A. G. Boon, N. H. Peng, Chen Chang Qing, Xu Nai Yun, N. Dayanand, Tam Yong Seng, Mai Zhi Hong, J. Lam","doi":"10.1109/IPFA.2018.8452519","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452519","url":null,"abstract":"In this paper, a low yield case relating to IDD leakage at active mode due to the systematic breakdown signature consistently at the top MIM edge was studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP probing, layout path tracing, FIB circuit edit, SEM XTEM and top down PFA methodology together with Fab investigation are used to understand the root cause as well as failure mechanism. This paper highlights that there are 2 types of leakage (high leakage in mA and low leakage in uA). The high leakage dies revealed spot directly at the MIM cap and anomaly can be observed at the MIM edge. However, for the low level leakage, hotspot was seen at the PMOS transistor and NOT at the MIM Cap. Besides layout tracing that enable to pinpoint the suspected MIM cap, 2 types of simulation (Intentionally induced damage and FIB Circuit Edit) were performed to prove and validate the MIM defect is the only root cause for this low yield issue and the RF circuitry has no contribution to it. Additionally, top down PFA methodology was engaged to reveal the physical evidence of the damage at the edge of the MIM. This confirmed that both type of leakage are due to similar MIM breakdown issue.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452592
Zhang Haipeng, Geng Lu, Lin Mi, Zhan Zhonghai, Lu Weifeng, Wang Xiaoyuan, Wang Ying, Zhang Qiang, B. Jianling, Wang Dejun
A novel high voltage InGaN/GaN/AlGaN RTD was proposed for ESD protection of GaN/InGaN-based devices and ICs. The proposed RTD consists of a sandwiched $text{In}_{0.21}text{Ga}_{0.79}mathrm{N}/text{GaN}/text{In}_{0.14}text{Ga}_{0.86}mathrm{N}/mathrm{A}1_{0.1}text{Ga}_{0.9}mathrm{N}$ DBS structure on a GaN/InGaN substrate with N-original surface. Simulation experiments indicated that the proposed RTD samples are characterized of high forward block voltages at about 7.38 V, low leakage forward currents less than $10^{-38}mathrm{A}/mu mathrm{m}^{2}$ and $10^{-39}mathrm{A}/mu mathrm{m}^{2}$ and high reverse current densities up to the order of $10^{-5}mathrm{A}/mu mathrm{m}^{2}$ at about −2.55 V bias voltage and beyond $10^{-4}mathrm{A}/mu mathrm{m}^{2}$ at about −2.8 V bias voltage respectively. Analysis on HBM mode ESD circuits indicated that they can be simplified into ideal one order RC loop. This is because that the resistance of the proposed high voltage (HV) RTD pair at on-state is ignorable relative to discharging resistance R1 whether considering its parasitic capacitance or not. As a result, the sample 1 with junction area of $120times 120mu mathrm{m}^{2}$ is large enough to protect the chip from ESD damaging up to $pm 2000$ V ESV swash in ideal 840 ns. As for sample 2, its junction area of $380times 380mu mathrm{m}^{2}$ is capable of providing the same strength of ESD protection as that of sample 1. As the parasitic capacitance of sample 2 was considered through analyses of charge variations in emitter region, quantum well region and collector region with bias voltage, the results indicate that the big signal differential parasitic floating capacitance of quantum region is about -0.178/-0.174 pF/cm2, which is negligible comparing with stand ESV capacitance of HBM mode ESD protection applications. Its function is to shielding the influence of applied voltage on the potential of the quantum well. Its attenuation factor of voltage is not more than −23.6 dB.
{"title":"High Voltage InGaN/GaN/AlGaN RTD Suitable for ESD Protection Applications of GaN/InGaN-based Devices and ICs Validated by Simulation Results","authors":"Zhang Haipeng, Geng Lu, Lin Mi, Zhan Zhonghai, Lu Weifeng, Wang Xiaoyuan, Wang Ying, Zhang Qiang, B. Jianling, Wang Dejun","doi":"10.1109/IPFA.2018.8452592","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452592","url":null,"abstract":"A novel high voltage InGaN/GaN/AlGaN RTD was proposed for ESD protection of GaN/InGaN-based devices and ICs. The proposed RTD consists of a sandwiched $text{In}_{0.21}text{Ga}_{0.79}mathrm{N}/text{GaN}/text{In}_{0.14}text{Ga}_{0.86}mathrm{N}/mathrm{A}1_{0.1}text{Ga}_{0.9}mathrm{N}$ DBS structure on a GaN/InGaN substrate with N-original surface. Simulation experiments indicated that the proposed RTD samples are characterized of high forward block voltages at about 7.38 V, low leakage forward currents less than $10^{-38}mathrm{A}/mu mathrm{m}^{2}$ and $10^{-39}mathrm{A}/mu mathrm{m}^{2}$ and high reverse current densities up to the order of $10^{-5}mathrm{A}/mu mathrm{m}^{2}$ at about −2.55 V bias voltage and beyond $10^{-4}mathrm{A}/mu mathrm{m}^{2}$ at about −2.8 V bias voltage respectively. Analysis on HBM mode ESD circuits indicated that they can be simplified into ideal one order RC loop. This is because that the resistance of the proposed high voltage (HV) RTD pair at on-state is ignorable relative to discharging resistance R1 whether considering its parasitic capacitance or not. As a result, the sample 1 with junction area of $120times 120mu mathrm{m}^{2}$ is large enough to protect the chip from ESD damaging up to $pm 2000$ V ESV swash in ideal 840 ns. As for sample 2, its junction area of $380times 380mu mathrm{m}^{2}$ is capable of providing the same strength of ESD protection as that of sample 1. As the parasitic capacitance of sample 2 was considered through analyses of charge variations in emitter region, quantum well region and collector region with bias voltage, the results indicate that the big signal differential parasitic floating capacitance of quantum region is about -0.178/-0.174 pF/cm2, which is negligible comparing with stand ESV capacitance of HBM mode ESD protection applications. Its function is to shielding the influence of applied voltage on the potential of the quantum well. Its attenuation factor of voltage is not more than −23.6 dB.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-07-01DOI: 10.1109/IPFA.2018.8452550
K. Peng, Kim Hsu, Finn Ger, Tsung-Chang Tsai
A novel approach for failure analysis with in situ TEM method is proposed and demonstrated in this work. With an ingenious sample preparation scheme, the approach allows us to perform both plan-view and cross-sectional TEM inspections on the same failure sites in a chip in an efficient way. The sample preparation is not difficult and can be processed with conventional tools. In the beginning, a large-area lamella for plane-view analysis is prepared and the condition of the SEM inspection is appropriately adjusted to enhance the voltage contrast revealed by the failure sites. Then the lamella is further processed by means of FIB milling to enable further examination with the cross-sectional TEM. As compared with the traditional way of preparing TEM P-V samples, this method can save time by more than 70%.
{"title":"A Novel Solution for Efficient in Situ TEM Cross-Section and Plan-View Analyses with An Advanced Sample Preparation Scheme","authors":"K. Peng, Kim Hsu, Finn Ger, Tsung-Chang Tsai","doi":"10.1109/IPFA.2018.8452550","DOIUrl":"https://doi.org/10.1109/IPFA.2018.8452550","url":null,"abstract":"A novel approach for failure analysis with in situ TEM method is proposed and demonstrated in this work. With an ingenious sample preparation scheme, the approach allows us to perform both plan-view and cross-sectional TEM inspections on the same failure sites in a chip in an efficient way. The sample preparation is not difficult and can be processed with conventional tools. In the beginning, a large-area lamella for plane-view analysis is prepared and the condition of the SEM inspection is appropriately adjusted to enhance the voltage contrast revealed by the failure sites. Then the lamella is further processed by means of FIB milling to enable further examination with the cross-sectional TEM. As compared with the traditional way of preparing TEM P-V samples, this method can save time by more than 70%.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131108025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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