Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902913
F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber
This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.
{"title":"28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications","authors":"F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber","doi":"10.1109/ESSCIRC.2019.8902913","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902913","url":null,"abstract":"This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121852766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902490
F. Kuo, Zhirui Zong, H. Chen, Lan-chou Cho, C. Jou, Mark Chen, R. Staszewski
This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range, fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5–28 GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits -97 dBc/Hz at 1 MHz offset from 77 GHz, while fully satisfying metal density rules. It occupies 0.07 mm2, thus demonstrating both 43% power and 47% area reductions. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 1.8 dB and 0.2 dB, respectively, compared to state-of-the-art.
{"title":"A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic","authors":"F. Kuo, Zhirui Zong, H. Chen, Lan-chou Cho, C. Jou, Mark Chen, R. Staszewski","doi":"10.1109/ESSCIRC.2019.8902490","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902490","url":null,"abstract":"This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range, fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5–28 GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits -97 dBc/Hz at 1 MHz offset from 77 GHz, while fully satisfying metal density rules. It occupies 0.07 mm2, thus demonstrating both 43% power and 47% area reductions. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 1.8 dB and 0.2 dB, respectively, compared to state-of-the-art.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124317306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902621
Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, S. Chiang
An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.
{"title":"An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch","authors":"Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, S. Chiang","doi":"10.1109/ESSCIRC.2019.8902621","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902621","url":null,"abstract":"An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"2 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120991828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902664
Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, D. Jeong
This paper presents an always-on mutual-capacitive touchscreen controller (TSC) with a reconfigurable power consumption of 0.53–13.4 mW, frame rate of 1–120 Hz, and an SNR of 40.0-46.2 dB to support not only a normal sensing mode but also a low-power (LP) and an ultra-low-power (ULP) modes. For the LP and ULP modes, the power-frame rate scalability is realized by a frame rate controller, which turns off analog front-end (AFE) transmitter (TX) and receiver (RX) periodically. Moreover, the TSC improves an out-of-band noise attenuation by utilizing a sixth-order current-mode band-pass filter and second-order incremental hybrid delta-sigma (ΔΣ) modulator, providing an SNR up to 45.8 dB when the display on. The prototype TSC is fabricated in an 80-nm high-voltage CMOS technology with an active area of 4.873 mm2.
{"title":"An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC","authors":"Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, D. Jeong","doi":"10.1109/ESSCIRC.2019.8902664","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902664","url":null,"abstract":"This paper presents an always-on mutual-capacitive touchscreen controller (TSC) with a reconfigurable power consumption of 0.53–13.4 mW, frame rate of 1–120 Hz, and an SNR of 40.0-46.2 dB to support not only a normal sensing mode but also a low-power (LP) and an ultra-low-power (ULP) modes. For the LP and ULP modes, the power-frame rate scalability is realized by a frame rate controller, which turns off analog front-end (AFE) transmitter (TX) and receiver (RX) periodically. Moreover, the TSC improves an out-of-band noise attenuation by utilizing a sixth-order current-mode band-pass filter and second-order incremental hybrid delta-sigma (ΔΣ) modulator, providing an SNR up to 45.8 dB when the display on. The prototype TSC is fabricated in an 80-nm high-voltage CMOS technology with an active area of 4.873 mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129737419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902872
Nishit Shah, P. Lajevardi, K. Wojciechowski, Christoph Lang, B. Murmann
This letter presents an energy harvester using conventional 4-T CMOS image sensor pixels in 0.13-µm CMOS. Its 320 240 pixel array can be time multiplexed to capture images or harvest energy. Among reported pixels with energy harvesting capability, we achieve the highest fill factor of 60.4% at a pitch of 5 µm. Auxiliary photodiodes that are placed outside the imager array generate a supply rail that enables cold start at incident light levels as low as 25 lux. A switched-capacitor (SC) boost converter steps up the harvested energy from 0.25–0.4 V to 1.8-V analog and 0.6-V digital supplies. The design achieves a peak power efficiency of 52.4% at an output power of 266 nW, while its analog maximum input power point tracking control circuit maintains over 96% tracking efficiency across all lighting conditions.
{"title":"An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency","authors":"Nishit Shah, P. Lajevardi, K. Wojciechowski, Christoph Lang, B. Murmann","doi":"10.1109/ESSCIRC.2019.8902872","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902872","url":null,"abstract":"This letter presents an energy harvester using conventional 4-T CMOS image sensor pixels in 0.13-µm CMOS. Its 320 240 pixel array can be time multiplexed to capture images or harvest energy. Among reported pixels with energy harvesting capability, we achieve the highest fill factor of 60.4% at a pitch of 5 µm. Auxiliary photodiodes that are placed outside the imager array generate a supply rail that enables cold start at incident light levels as low as 25 lux. A switched-capacitor (SC) boost converter steps up the harvested energy from 0.25–0.4 V to 1.8-V analog and 0.6-V digital supplies. The design achieves a peak power efficiency of 52.4% at an output power of 266 nW, while its analog maximum input power point tracking control circuit maintains over 96% tracking efficiency across all lighting conditions.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902871
P. Harpe, Hanyue Li, Yuting Shen
With the development of mobile devices and Internet-of-Things, the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work, we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations, it can be shown why sometimes very different approaches are used to minimize power consumption. Various state-of-the-art examples will be shown to illustrate the diversity of techniques and ideas within the field. Next, an outlook to the future is given by discussing various unsolved challenges and new opportunities.
{"title":"Low-power SAR ADCs: trends, examples and future","authors":"P. Harpe, Hanyue Li, Yuting Shen","doi":"10.1109/ESSCIRC.2019.8902871","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902871","url":null,"abstract":"With the development of mobile devices and Internet-of-Things, the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work, we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations, it can be shown why sometimes very different approaches are used to minimize power consumption. Various state-of-the-art examples will be shown to illustrate the diversity of techniques and ideas within the field. Next, an outlook to the future is given by discussing various unsolved challenges and new opportunities.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127274958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902880
John Bell, M. Flynn
This letter presents a new class of ΔΣ modulator that combines any set of traditional NTF shapes in a single modulator. The prototype multiband ΔΣ modulator (MB-ΔΣM) demonstrates two simultaneous bands—one baseband and one bandpass. These two bands are separated by 500 MHz, have an aggregate bandwidth of 90 MHz, with up to 55-dB measured SNDR. In addition to reducing the number of ADCs, this new approach promises further system-level power savings by simplifying the RF frontend. The system-level power savings from requiring fewer analog mixers, LNAs, filters, and ADC drivers can be even more than the ADC power reduction.
{"title":"A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS","authors":"John Bell, M. Flynn","doi":"10.1109/ESSCIRC.2019.8902880","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902880","url":null,"abstract":"This letter presents a new class of ΔΣ modulator that combines any set of traditional NTF shapes in a single modulator. The prototype multiband ΔΣ modulator (MB-ΔΣM) demonstrates two simultaneous bands—one baseband and one bandpass. These two bands are separated by 500 MHz, have an aggregate bandwidth of 90 MHz, with up to 55-dB measured SNDR. In addition to reducing the number of ADCs, this new approach promises further system-level power savings by simplifying the RF frontend. The system-level power savings from requiring fewer analog mixers, LNAs, filters, and ADC drivers can be even more than the ADC power reduction.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129118206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902905
R. Kleczek, P. Kmon, P. Maj, R. Szczygiel, P. Grybos, Y. Nakaye, Takuto Sakumura, T. Takeyoshi
We report on design and measurements of the integrated circuit in CMOS 130 nm for readout of hybrid pixel detector operating in a single photon counting (SPC) mode. A core of IC contains a matrix of 128 × 176 square shaped pixels of 75 µm pitch. Each readout pixel consists of charge sensitive amplifier (CSA), shaper, two discriminators and two 14-bit counters. The novel CSA feedback, with the effective resistance of 0.6 GΩ and sets of switches, allows for sensor leakage current compensation up to tens of nA, fast return to the CSA output baseline even in the case of the high frequency of input pulses, and low noise operation. The measured equivalent noise charge is only 60 e- rms, while an offset spread is 9.4 e- rms. These parameters allow to count and distinguish photons in each pixel independently, even if the difference between photons’ energies is only 0.86 keV. Having in mind future synchrotron applications, the several readout schemes of the pixel matrix are implemented. The continuous readout mode allows for 70 kfps frame rate. The power consumption per single pixel is about 37 µW.
{"title":"SPC Pixel IC with 9.4 e− rms Offset Spread, 60 e− rms ENC and 70 kfps Frame Rate","authors":"R. Kleczek, P. Kmon, P. Maj, R. Szczygiel, P. Grybos, Y. Nakaye, Takuto Sakumura, T. Takeyoshi","doi":"10.1109/ESSCIRC.2019.8902905","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902905","url":null,"abstract":"We report on design and measurements of the integrated circuit in CMOS 130 nm for readout of hybrid pixel detector operating in a single photon counting (SPC) mode. A core of IC contains a matrix of 128 × 176 square shaped pixels of 75 µm pitch. Each readout pixel consists of charge sensitive amplifier (CSA), shaper, two discriminators and two 14-bit counters. The novel CSA feedback, with the effective resistance of 0.6 GΩ and sets of switches, allows for sensor leakage current compensation up to tens of nA, fast return to the CSA output baseline even in the case of the high frequency of input pulses, and low noise operation. The measured equivalent noise charge is only 60 e- rms, while an offset spread is 9.4 e- rms. These parameters allow to count and distinguish photons in each pixel independently, even if the difference between photons’ energies is only 0.86 keV. Having in mind future synchrotron applications, the several readout schemes of the pixel matrix are implemented. The continuous readout mode allows for 70 kfps frame rate. The power consumption per single pixel is about 37 µW.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902687
Peishuo Li, Tom R. Molderez, F. Ceyssens, K. Rabaey, M. Verhelst
Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility.
{"title":"A 64-channel, 1.1-pA-accurate On-chip Potentiostat for Parallel Electrochemical Monitoring","authors":"Peishuo Li, Tom R. Molderez, F. Ceyssens, K. Rabaey, M. Verhelst","doi":"10.1109/ESSCIRC.2019.8902687","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902687","url":null,"abstract":"Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902926
Yu Zou, M. Gottardi, M. Lecca, M. Perenzoni
This paper presents a micropower VGA event-based vision sensor for IoT applications, achieving a low rate of false positives also in noisy outdoor scenarios. The embedded programmable pixel-wise, double-threshold, motion detection algorithm, applied on a under-sampled array of 160 × 120 pixels, allows to address a wide spectrum of applications. The sensor typically works in detection mode, consuming 344µW at 8fps, analysing the image, suppressing noise in the scene and looking for moving targets to generate an alert which triggers a processor for high-level vision tasks. After the alert is asserted, the sensor switches to the imaging mode delivering full resolution gray-scale images together with their motion bitmaps at 1.35mW. The 4µm pixel sensor is fabricated in a 110nm CMOS and occupies an area of 25 mm2.
{"title":"A Low-Power VGA Vision Sensor with Event Detection through Motion Computation based on Pixel-Wise Double-Threshold Background Subtraction and Local Binary Pattern Coding","authors":"Yu Zou, M. Gottardi, M. Lecca, M. Perenzoni","doi":"10.1109/ESSCIRC.2019.8902926","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902926","url":null,"abstract":"This paper presents a micropower VGA event-based vision sensor for IoT applications, achieving a low rate of false positives also in noisy outdoor scenarios. The embedded programmable pixel-wise, double-threshold, motion detection algorithm, applied on a under-sampled array of 160 × 120 pixels, allows to address a wide spectrum of applications. The sensor typically works in detection mode, consuming 344µW at 8fps, analysing the image, suppressing noise in the scene and looking for moving targets to generate an alert which triggers a processor for high-level vision tasks. After the alert is asserted, the sensor switches to the imaging mode delivering full resolution gray-scale images together with their motion bitmaps at 1.35mW. The 4µm pixel sensor is fabricated in a 110nm CMOS and occupies an area of 25 mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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