Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902490
F. Kuo, Zhirui Zong, H. Chen, Lan-chou Cho, C. Jou, Mark Chen, R. Staszewski
This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range, fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5–28 GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits -97 dBc/Hz at 1 MHz offset from 77 GHz, while fully satisfying metal density rules. It occupies 0.07 mm2, thus demonstrating both 43% power and 47% area reductions. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 1.8 dB and 0.2 dB, respectively, compared to state-of-the-art.
{"title":"A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic","authors":"F. Kuo, Zhirui Zong, H. Chen, Lan-chou Cho, C. Jou, Mark Chen, R. Staszewski","doi":"10.1109/ESSCIRC.2019.8902490","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902490","url":null,"abstract":"This paper presents a digitally controlled frequency generator for dual frequency-band radar system that is optimized for 16 nm FinFET CMOS. It is based on a 21% wide tuning range, fine-resolution DCO with only switchable metal capacitors. A third-harmonic boosting DCO simultaneously generates 22.5–28 GHz and sufficiently strong 68–84 GHz signals to satisfy short-range radar (SRR) and medium/long range radar (M/LRR) requirements. The 20.2 mW DCO emits -97 dBc/Hz at 1 MHz offset from 77 GHz, while fully satisfying metal density rules. It occupies 0.07 mm2, thus demonstrating both 43% power and 47% area reductions. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 1.8 dB and 0.2 dB, respectively, compared to state-of-the-art.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124317306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902905
R. Kleczek, P. Kmon, P. Maj, R. Szczygiel, P. Grybos, Y. Nakaye, Takuto Sakumura, T. Takeyoshi
We report on design and measurements of the integrated circuit in CMOS 130 nm for readout of hybrid pixel detector operating in a single photon counting (SPC) mode. A core of IC contains a matrix of 128 × 176 square shaped pixels of 75 µm pitch. Each readout pixel consists of charge sensitive amplifier (CSA), shaper, two discriminators and two 14-bit counters. The novel CSA feedback, with the effective resistance of 0.6 GΩ and sets of switches, allows for sensor leakage current compensation up to tens of nA, fast return to the CSA output baseline even in the case of the high frequency of input pulses, and low noise operation. The measured equivalent noise charge is only 60 e- rms, while an offset spread is 9.4 e- rms. These parameters allow to count and distinguish photons in each pixel independently, even if the difference between photons’ energies is only 0.86 keV. Having in mind future synchrotron applications, the several readout schemes of the pixel matrix are implemented. The continuous readout mode allows for 70 kfps frame rate. The power consumption per single pixel is about 37 µW.
{"title":"SPC Pixel IC with 9.4 e− rms Offset Spread, 60 e− rms ENC and 70 kfps Frame Rate","authors":"R. Kleczek, P. Kmon, P. Maj, R. Szczygiel, P. Grybos, Y. Nakaye, Takuto Sakumura, T. Takeyoshi","doi":"10.1109/ESSCIRC.2019.8902905","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902905","url":null,"abstract":"We report on design and measurements of the integrated circuit in CMOS 130 nm for readout of hybrid pixel detector operating in a single photon counting (SPC) mode. A core of IC contains a matrix of 128 × 176 square shaped pixels of 75 µm pitch. Each readout pixel consists of charge sensitive amplifier (CSA), shaper, two discriminators and two 14-bit counters. The novel CSA feedback, with the effective resistance of 0.6 GΩ and sets of switches, allows for sensor leakage current compensation up to tens of nA, fast return to the CSA output baseline even in the case of the high frequency of input pulses, and low noise operation. The measured equivalent noise charge is only 60 e- rms, while an offset spread is 9.4 e- rms. These parameters allow to count and distinguish photons in each pixel independently, even if the difference between photons’ energies is only 0.86 keV. Having in mind future synchrotron applications, the several readout schemes of the pixel matrix are implemented. The continuous readout mode allows for 70 kfps frame rate. The power consumption per single pixel is about 37 µW.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129828040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902716
F. Fary, L. Mangiagalli, E. Vallicelli, M. Matteis, A. Baschirotto
This paper presents the design and the experimental validation of a 6th-order continuous-time low-pass filter in 28 nm bulk-CMOS, based on the cascade of 3 Rauch biquadratic cells. Each cell exploits a broad-bandwidth Operational Transconductance Amplifier (OTA), without Miller compensation scheme for differential Loop Gain stability. This maximizes the OTA unity gain bandwidth, with no power increase w.r.t classical compensation schemes, and improves both frequency response accuracy and linearity over the filter pass-band. This aggressive design choice is sustained by the higher 28 nm CMOS transistor’s transition frequency and by the intrinsic feature of the Rauch cell, whose R-C feedback/direct path nets introduce two poles and two zeros that self-compensate the differential loop-gain. On the other hand, the proposed OTA only exploits a compensation scheme for the common-mode signal stability, which does not affect the differential signal. The prototype synthesizes 50 MHz low-pass frequency response at 3.3 mA current consumption from a single 1.1 V supply and performs 18 dBm and 16.5 dBm Input IP3 for 10&11 MHz and 40&41 MHz input tones, equalizing the linearity performance over the filter pass-band, just thanks to the OTA wider bandwidth. This finally allows 153 dBJ-1 and 158 dBJ-1 Figure-of-Merit at 10&11 MHz and 40&41 MHz input tones.
{"title":"A 28nm bulk-CMOS 50MHz 18 dBm-IIP3 Active-RC Analog Filter based on 7 GHz UGB OTA","authors":"F. Fary, L. Mangiagalli, E. Vallicelli, M. Matteis, A. Baschirotto","doi":"10.1109/ESSCIRC.2019.8902716","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902716","url":null,"abstract":"This paper presents the design and the experimental validation of a 6th-order continuous-time low-pass filter in 28 nm bulk-CMOS, based on the cascade of 3 Rauch biquadratic cells. Each cell exploits a broad-bandwidth Operational Transconductance Amplifier (OTA), without Miller compensation scheme for differential Loop Gain stability. This maximizes the OTA unity gain bandwidth, with no power increase w.r.t classical compensation schemes, and improves both frequency response accuracy and linearity over the filter pass-band. This aggressive design choice is sustained by the higher 28 nm CMOS transistor’s transition frequency and by the intrinsic feature of the Rauch cell, whose R-C feedback/direct path nets introduce two poles and two zeros that self-compensate the differential loop-gain. On the other hand, the proposed OTA only exploits a compensation scheme for the common-mode signal stability, which does not affect the differential signal. The prototype synthesizes 50 MHz low-pass frequency response at 3.3 mA current consumption from a single 1.1 V supply and performs 18 dBm and 16.5 dBm Input IP3 for 10&11 MHz and 40&41 MHz input tones, equalizing the linearity performance over the filter pass-band, just thanks to the OTA wider bandwidth. This finally allows 153 dBJ-1 and 158 dBJ-1 Figure-of-Merit at 10&11 MHz and 40&41 MHz input tones.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116631527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902880
John Bell, M. Flynn
This letter presents a new class of ΔΣ modulator that combines any set of traditional NTF shapes in a single modulator. The prototype multiband ΔΣ modulator (MB-ΔΣM) demonstrates two simultaneous bands—one baseband and one bandpass. These two bands are separated by 500 MHz, have an aggregate bandwidth of 90 MHz, with up to 55-dB measured SNDR. In addition to reducing the number of ADCs, this new approach promises further system-level power savings by simplifying the RF frontend. The system-level power savings from requiring fewer analog mixers, LNAs, filters, and ADC drivers can be even more than the ADC power reduction.
{"title":"A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS","authors":"John Bell, M. Flynn","doi":"10.1109/ESSCIRC.2019.8902880","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902880","url":null,"abstract":"This letter presents a new class of ΔΣ modulator that combines any set of traditional NTF shapes in a single modulator. The prototype multiband ΔΣ modulator (MB-ΔΣM) demonstrates two simultaneous bands—one baseband and one bandpass. These two bands are separated by 500 MHz, have an aggregate bandwidth of 90 MHz, with up to 55-dB measured SNDR. In addition to reducing the number of ADCs, this new approach promises further system-level power savings by simplifying the RF frontend. The system-level power savings from requiring fewer analog mixers, LNAs, filters, and ADC drivers can be even more than the ADC power reduction.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129118206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902879
Paul Stärke, Xin Xu, C. Carta, F. Ellinger
This work presents an integrated mm-wave transmitter front-end with independent in-phase and quadrature paths for carrier frequencies around 180 GHz. The up-conversion units consist of a double-balanced active mixer with baseband (IF) buffer, local oscillator (LO) driver and RF power amplifier (PA). A passive 90° hybrid generates the quadrature LO signal and a power combiner joins the PA outputs. The IF-to-RF conversion gain is 10 dB, with an RF bandwidth of 80 GHz. The design supports binary and higher order modulation schemes and exhibits an IF input referred 1-dB compression point of −11 dBm. The saturated output power is 3.5 dBm per path and an LO level of −5 dBm is sufficient for an optimal operation. The total power consumption is 151 mW per path. The final chip occupies an area of 1.4 mm2 and is fabricated in a 130 nm SiGe BiCMOS process with a maximum oscillation frequency of 450 GHz. The main application of this circuit is ultra-wideband short-range communication with data rates beyond 100 Gbit/s.
{"title":"Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe","authors":"Paul Stärke, Xin Xu, C. Carta, F. Ellinger","doi":"10.1109/ESSCIRC.2019.8902879","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902879","url":null,"abstract":"This work presents an integrated mm-wave transmitter front-end with independent in-phase and quadrature paths for carrier frequencies around 180 GHz. The up-conversion units consist of a double-balanced active mixer with baseband (IF) buffer, local oscillator (LO) driver and RF power amplifier (PA). A passive 90° hybrid generates the quadrature LO signal and a power combiner joins the PA outputs. The IF-to-RF conversion gain is 10 dB, with an RF bandwidth of 80 GHz. The design supports binary and higher order modulation schemes and exhibits an IF input referred 1-dB compression point of −11 dBm. The saturated output power is 3.5 dBm per path and an LO level of −5 dBm is sufficient for an optimal operation. The total power consumption is 151 mW per path. The final chip occupies an area of 1.4 mm2 and is fabricated in a 130 nm SiGe BiCMOS process with a maximum oscillation frequency of 450 GHz. The main application of this circuit is ultra-wideband short-range communication with data rates beyond 100 Gbit/s.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123536862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902919
G. Vlachogiannakis, Charis Basetas, G. Tsirimokou, C. Vassou, Konstantinos Vastarouchas, A. Georgiadou, Ioulia Sotiriou, Timothea Korfiati, S. Sgourenas
This paper presents a fractional-N PLL frequency synthesizer with self-calibration digital loop engines for fast frequency acquisition and noise-driven optimization of loop filter bandwidth, VCO frequency and amplitude control. The PLL is implemented in a 28nm FDSOI CMOS technology and its noise performance is optimized by employing a dual-edge PFD architecture, charge pump linearization, and bias sampling and a spur-less, single-stage multiple feedback sigma delta modulator to achieve a typical rms jitter of 175 fs, while drawing 21 mA from a 1.8-V supply.
{"title":"A Self-Calibrated Fractional-N PLL for WiFi 6 / 802.11ax in 28nm FDSOI CMOS","authors":"G. Vlachogiannakis, Charis Basetas, G. Tsirimokou, C. Vassou, Konstantinos Vastarouchas, A. Georgiadou, Ioulia Sotiriou, Timothea Korfiati, S. Sgourenas","doi":"10.1109/ESSCIRC.2019.8902919","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902919","url":null,"abstract":"This paper presents a fractional-N PLL frequency synthesizer with self-calibration digital loop engines for fast frequency acquisition and noise-driven optimization of loop filter bandwidth, VCO frequency and amplitude control. The PLL is implemented in a 28nm FDSOI CMOS technology and its noise performance is optimized by employing a dual-edge PFD architecture, charge pump linearization, and bias sampling and a spur-less, single-stage multiple feedback sigma delta modulator to achieve a typical rms jitter of 175 fs, while drawing 21 mA from a 1.8-V supply.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128448394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902926
Yu Zou, M. Gottardi, M. Lecca, M. Perenzoni
This paper presents a micropower VGA event-based vision sensor for IoT applications, achieving a low rate of false positives also in noisy outdoor scenarios. The embedded programmable pixel-wise, double-threshold, motion detection algorithm, applied on a under-sampled array of 160 × 120 pixels, allows to address a wide spectrum of applications. The sensor typically works in detection mode, consuming 344µW at 8fps, analysing the image, suppressing noise in the scene and looking for moving targets to generate an alert which triggers a processor for high-level vision tasks. After the alert is asserted, the sensor switches to the imaging mode delivering full resolution gray-scale images together with their motion bitmaps at 1.35mW. The 4µm pixel sensor is fabricated in a 110nm CMOS and occupies an area of 25 mm2.
{"title":"A Low-Power VGA Vision Sensor with Event Detection through Motion Computation based on Pixel-Wise Double-Threshold Background Subtraction and Local Binary Pattern Coding","authors":"Yu Zou, M. Gottardi, M. Lecca, M. Perenzoni","doi":"10.1109/ESSCIRC.2019.8902926","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902926","url":null,"abstract":"This paper presents a micropower VGA event-based vision sensor for IoT applications, achieving a low rate of false positives also in noisy outdoor scenarios. The embedded programmable pixel-wise, double-threshold, motion detection algorithm, applied on a under-sampled array of 160 × 120 pixels, allows to address a wide spectrum of applications. The sensor typically works in detection mode, consuming 344µW at 8fps, analysing the image, suppressing noise in the scene and looking for moving targets to generate an alert which triggers a processor for high-level vision tasks. After the alert is asserted, the sensor switches to the imaging mode delivering full resolution gray-scale images together with their motion bitmaps at 1.35mW. The 4µm pixel sensor is fabricated in a 110nm CMOS and occupies an area of 25 mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902871
P. Harpe, Hanyue Li, Yuting Shen
With the development of mobile devices and Internet-of-Things, the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work, we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations, it can be shown why sometimes very different approaches are used to minimize power consumption. Various state-of-the-art examples will be shown to illustrate the diversity of techniques and ideas within the field. Next, an outlook to the future is given by discussing various unsolved challenges and new opportunities.
{"title":"Low-power SAR ADCs: trends, examples and future","authors":"P. Harpe, Hanyue Li, Yuting Shen","doi":"10.1109/ESSCIRC.2019.8902871","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902871","url":null,"abstract":"With the development of mobile devices and Internet-of-Things, the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work, we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations, it can be shown why sometimes very different approaches are used to minimize power consumption. Various state-of-the-art examples will be shown to illustrate the diversity of techniques and ideas within the field. Next, an outlook to the future is given by discussing various unsolved challenges and new opportunities.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127274958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902872
Nishit Shah, P. Lajevardi, K. Wojciechowski, Christoph Lang, B. Murmann
This letter presents an energy harvester using conventional 4-T CMOS image sensor pixels in 0.13-µm CMOS. Its 320 240 pixel array can be time multiplexed to capture images or harvest energy. Among reported pixels with energy harvesting capability, we achieve the highest fill factor of 60.4% at a pitch of 5 µm. Auxiliary photodiodes that are placed outside the imager array generate a supply rail that enables cold start at incident light levels as low as 25 lux. A switched-capacitor (SC) boost converter steps up the harvested energy from 0.25–0.4 V to 1.8-V analog and 0.6-V digital supplies. The design achieves a peak power efficiency of 52.4% at an output power of 266 nW, while its analog maximum input power point tracking control circuit maintains over 96% tracking efficiency across all lighting conditions.
{"title":"An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency","authors":"Nishit Shah, P. Lajevardi, K. Wojciechowski, Christoph Lang, B. Murmann","doi":"10.1109/ESSCIRC.2019.8902872","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902872","url":null,"abstract":"This letter presents an energy harvester using conventional 4-T CMOS image sensor pixels in 0.13-µm CMOS. Its 320 240 pixel array can be time multiplexed to capture images or harvest energy. Among reported pixels with energy harvesting capability, we achieve the highest fill factor of 60.4% at a pitch of 5 µm. Auxiliary photodiodes that are placed outside the imager array generate a supply rail that enables cold start at incident light levels as low as 25 lux. A switched-capacitor (SC) boost converter steps up the harvested energy from 0.25–0.4 V to 1.8-V analog and 0.6-V digital supplies. The design achieves a peak power efficiency of 52.4% at an output power of 266 nW, while its analog maximum input power point tracking control circuit maintains over 96% tracking efficiency across all lighting conditions.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126984713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902687
Peishuo Li, Tom R. Molderez, F. Ceyssens, K. Rabaey, M. Verhelst
Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility.
{"title":"A 64-channel, 1.1-pA-accurate On-chip Potentiostat for Parallel Electrochemical Monitoring","authors":"Peishuo Li, Tom R. Molderez, F. Ceyssens, K. Rabaey, M. Verhelst","doi":"10.1109/ESSCIRC.2019.8902687","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902687","url":null,"abstract":"Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126420142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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