Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902925
Q. Fan, Jinghong Chen
This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.
{"title":"A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology","authors":"Q. Fan, Jinghong Chen","doi":"10.1109/ESSCIRC.2019.8902925","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902925","url":null,"abstract":"This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127530726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902902
Omar Abdelatty, Henry L. Bishop, Yao Shi, Xing Chen, A. Alghaihab, B. Calhoun, D. Wentzloff
This paper presents a low power, fully-integrated Bluetooth Low-Energy (BLE) transmitter (TX) for Internet-of-Things (IoT) applications. The complete BLE TX achieves a total energy per bit of 3.5nJ in an open-loop transmission scheme due to the ultra-low startup energy of the system. The overall system architecture of the BLE TX includes an RF front-end, a 16 MHz crystal oscillator (XO), a GFSK modulator, and a digital baseband including a SPI interface. An enhanced capacitively loaded three-stage inverter chain XO is proposed, featuring a 10.2nJ startup-energy, a 150μs startup time, and a 70μW steady-state power. The steady-state frequency inaccuracy of the XO is 14 ppm with less than 26ps cycle-to-cycle jitter. The BLE TX is fabricated in 65nm CMOS technology and it consumes an average power of 2.17mW to transmit an advertisement packet consisting of 368 bits entirely over 600μs including the startup time. Duty-cycling operation is implemented through power gating achieving an average power consumption of 3.72μW (1.86× sleep power) when transmitting a BLE advertising message every 753ms. In our target application, by using these techniques, we are able to extend a common coin battery’s lifetime to more than 20 years.
{"title":"A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator","authors":"Omar Abdelatty, Henry L. Bishop, Yao Shi, Xing Chen, A. Alghaihab, B. Calhoun, D. Wentzloff","doi":"10.1109/ESSCIRC.2019.8902902","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902902","url":null,"abstract":"This paper presents a low power, fully-integrated Bluetooth Low-Energy (BLE) transmitter (TX) for Internet-of-Things (IoT) applications. The complete BLE TX achieves a total energy per bit of 3.5nJ in an open-loop transmission scheme due to the ultra-low startup energy of the system. The overall system architecture of the BLE TX includes an RF front-end, a 16 MHz crystal oscillator (XO), a GFSK modulator, and a digital baseband including a SPI interface. An enhanced capacitively loaded three-stage inverter chain XO is proposed, featuring a 10.2nJ startup-energy, a 150μs startup time, and a 70μW steady-state power. The steady-state frequency inaccuracy of the XO is 14 ppm with less than 26ps cycle-to-cycle jitter. The BLE TX is fabricated in 65nm CMOS technology and it consumes an average power of 2.17mW to transmit an advertisement packet consisting of 368 bits entirely over 600μs including the startup time. Duty-cycling operation is implemented through power gating achieving an average power consumption of 3.72μW (1.86× sleep power) when transmitting a BLE advertising message every 753ms. In our target application, by using these techniques, we are able to extend a common coin battery’s lifetime to more than 20 years.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129936680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902706
Q. Fan, Runxi Zhang, P. Bikkina, E. Mikkola, Jinghong Chen
This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.
{"title":"A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator","authors":"Q. Fan, Runxi Zhang, P. Bikkina, E. Mikkola, Jinghong Chen","doi":"10.1109/ESSCIRC.2019.8902706","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902706","url":null,"abstract":"This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126600816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902498
G. Pini, D. Manstretta, R. Castello
A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show alternate channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply.
{"title":"A 260-MHz RF Bandwidth Mixer-First Receiver With Third-Order Current-Mode Filtering TIA","authors":"G. Pini, D. Manstretta, R. Castello","doi":"10.1109/ESSCIRC.2019.8902498","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902498","url":null,"abstract":"A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show alternate channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902620
Q. Fan, Jinghong Chen
A power-efficient 2.4 GS/s 10-bit time-interleaved SAR ADC is presented. To reduce the power consumption, several conversion cycles are skipped as the input signal falls within a predefined bypass window. To enhance the operation speed, two alternate comparators are adopted in each ADC channel. The comparator offset is calibrated only when the bit bypass is triggered. This eliminates the need of a dedicated calibration cycle and the conversion rate degradation is avoided. The reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without introduction of power-hungry distributed reference buffers. Fabricated in a 28 nm FDSOI process, the proposed ADC achieves 49.02 dB SNDR and a Nyquist Walden FOM of 17.7 fJ/conv.-step at 2.4 GS/s.
{"title":"A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration","authors":"Q. Fan, Jinghong Chen","doi":"10.1109/ESSCIRC.2019.8902620","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902620","url":null,"abstract":"A power-efficient 2.4 GS/s 10-bit time-interleaved SAR ADC is presented. To reduce the power consumption, several conversion cycles are skipped as the input signal falls within a predefined bypass window. To enhance the operation speed, two alternate comparators are adopted in each ADC channel. The comparator offset is calibrated only when the bit bypass is triggered. This eliminates the need of a dedicated calibration cycle and the conversion rate degradation is avoided. The reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without introduction of power-hungry distributed reference buffers. Fabricated in a 28 nm FDSOI process, the proposed ADC achieves 49.02 dB SNDR and a Nyquist Walden FOM of 17.7 fJ/conv.-step at 2.4 GS/s.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122489469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902895
Thije Rooijers, J. Huijsing, K. Makinwa
This paper presents an input-current trimming scheme for auto-zero amplifiers. Since their input current is mainly due to charge injection, the scheme operates by trimming the clock swing, and hence the charge injection, of two dummy input switches. At room temperature, the trimming scheme reduces the maximum input current of an auto-zero stabilized voltage buffer from 1pA to 0.2pA (13 samples) over its full input voltage range (0 to 1.3V). This increases to 0.4pA over temperature (0 to 85°C), which is well below the leakage of typical ESD diodes, and is the lowest input current ever reported for an auto-zero amplifier.
{"title":"An Auto-Zero Stabilized Voltage Buffer with a Trimmed Input Current of 0.2pA","authors":"Thije Rooijers, J. Huijsing, K. Makinwa","doi":"10.1109/ESSCIRC.2019.8902895","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902895","url":null,"abstract":"This paper presents an input-current trimming scheme for auto-zero amplifiers. Since their input current is mainly due to charge injection, the scheme operates by trimming the clock swing, and hence the charge injection, of two dummy input switches. At room temperature, the trimming scheme reduces the maximum input current of an auto-zero stabilized voltage buffer from 1pA to 0.2pA (13 samples) over its full input voltage range (0 to 1.3V). This increases to 0.4pA over temperature (0 to 85°C), which is well below the leakage of typical ESD diodes, and is the lowest input current ever reported for an auto-zero amplifier.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133242086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902752
Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.
{"title":"C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing","authors":"Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok","doi":"10.1109/ESSCIRC.2019.8902752","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902752","url":null,"abstract":"This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134370829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902869
Rehman Akbar, E. Klumperink, N. Tervo, M. Javed, K. Stadius, T. Rahkonen, A. Pärssinen
Large-scale phased arrays need to combine weighted signals from multiple sub-arrays either in analog or in digital domain. Sub-arrays are preferably implemented modularly with integrated circuits placed next to the associated antennas. In order to enable flexible and scalable combining networks of several mmWave sub-arrays, this paper presents a wideband receiver module that provides the cartesian combining of beamforming weights for one sub-array at IF. Furthermore, it allows interference cancellation between sub-arrays or combining multiple sub-arrays. It also provides filtering before ADCs to support current and foreseeable 5G channel bandwidths up to 800MHz. The receiver is operating at 2-4GHz IF frequency range and has more than 400MHz baseband bandwidth, a noise-figure of 5.5dB, -6dBm 1dB compression point and +3dBm in-band IIP3. In addition, over-the-air measurements are performed, showing 26dB of interference cancellation between the sub-arrays. The prototype is implemented using 45nm CMOS PDSOI.
{"title":"A Wideband IF Receiver Module for Flexibly Scalable mmWave Beamforming Combining and Interference Cancellation","authors":"Rehman Akbar, E. Klumperink, N. Tervo, M. Javed, K. Stadius, T. Rahkonen, A. Pärssinen","doi":"10.1109/ESSCIRC.2019.8902869","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902869","url":null,"abstract":"Large-scale phased arrays need to combine weighted signals from multiple sub-arrays either in analog or in digital domain. Sub-arrays are preferably implemented modularly with integrated circuits placed next to the associated antennas. In order to enable flexible and scalable combining networks of several mmWave sub-arrays, this paper presents a wideband receiver module that provides the cartesian combining of beamforming weights for one sub-array at IF. Furthermore, it allows interference cancellation between sub-arrays or combining multiple sub-arrays. It also provides filtering before ADCs to support current and foreseeable 5G channel bandwidths up to 800MHz. The receiver is operating at 2-4GHz IF frequency range and has more than 400MHz baseband bandwidth, a noise-figure of 5.5dB, -6dBm 1dB compression point and +3dBm in-band IIP3. In addition, over-the-air measurements are performed, showing 26dB of interference cancellation between the sub-arrays. The prototype is implemented using 45nm CMOS PDSOI.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902923
Mohamed A. Mokhtar, P. Vogelmann, Michael Haas, M. Ortmanns
This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm2. The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.
{"title":"A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback","authors":"Mohamed A. Mokhtar, P. Vogelmann, Michael Haas, M. Ortmanns","doi":"10.1109/ESSCIRC.2019.8902923","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902923","url":null,"abstract":"This letter presents a high-resolution continuous-time incremental delta–sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm2. The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122272688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902868
Cheng-Hsueh Tsai, F. Pepe, G. Mangraviti, Zhiwei Zong, J. Craninckx, P. Wambacq
We present a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm, scaling up the PLL bandwidth for faster settling, and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO), based on transformer feedback with a tunable source-bridged capacitor, exhibits low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoMT of −191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its settling time improves from 780 to 45 µs with our gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.
{"title":"A 22.5–27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter","authors":"Cheng-Hsueh Tsai, F. Pepe, G. Mangraviti, Zhiwei Zong, J. Craninckx, P. Wambacq","doi":"10.1109/ESSCIRC.2019.8902868","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902868","url":null,"abstract":"We present a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for mm-wave communication. The fast lock is achieved with the help of the proposed gear-shift algorithm, scaling up the PLL bandwidth for faster settling, and orderly reducing it for jitter performance. A digitally controlled oscillator (DCO), based on transformer feedback with a tunable source-bridged capacitor, exhibits low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoMT of −191 dBc/Hz). The PLL occupies 0.09-mm2 core area and exhibits 220-fs RMS jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its settling time improves from 780 to 45 µs with our gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channel frequencies of IEEE-802.11ad and is capable of supporting 128 QAM and beyond.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129267371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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