Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902511
Yasu Lu, Feng Chen, P. Mok
This paper presents a single-controller-four-output analog-assisted digital LDO which can regulate four output voltage domains by sharing only one digital controller with an adaptive-time-multiplexing control scheme. The area of the digital controller is 62% smaller compared to the sum of the digital controller area of four independent LDOs. An analog-assisted loop and a push-pull auxiliary loop are used to take over the control in steady state to save quiescent power, reduce output ripple and enhance the response speed. A prototype is fabricated in a 65nm CMOS process. An undershoot voltage of 100mV is measured with a 47mA/20ns load step, resulting a figure-of-merit as low as 0.12ps.
{"title":"A Single-Controller-Four-Output Analog-Assisted Digital LDO with Adaptive-Time-Multiplexing Control in 65-nm CMOS","authors":"Yasu Lu, Feng Chen, P. Mok","doi":"10.1109/ESSCIRC.2019.8902511","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902511","url":null,"abstract":"This paper presents a single-controller-four-output analog-assisted digital LDO which can regulate four output voltage domains by sharing only one digital controller with an adaptive-time-multiplexing control scheme. The area of the digital controller is 62% smaller compared to the sum of the digital controller area of four independent LDOs. An analog-assisted loop and a push-pull auxiliary loop are used to take over the control in steady state to save quiescent power, reduce output ripple and enhance the response speed. A prototype is fabricated in a 65nm CMOS process. An undershoot voltage of 100mV is measured with a 47mA/20ns load step, resulting a figure-of-merit as low as 0.12ps.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125609144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902847
M. Kucharski, H. Ng, D. Kissinger
This paper presents a 4-way power amplifier (PA) using a T-junction network for efficient power combining. The circuit was implemented using a 130 nm SiGe BiCMOS technology with fT/fMAX= 300/500 GHz. The PA achieves 30.2 dB peak linear gain at 170 GHz and more than 27.2 dB in 155-180 GHz range. At 170 GHz the circuit delivers up to 18 dBm saturated output power (P SAT) with output referred 1 dB compression point (OP 1dB) at 15.6 dBm, which to the best author’s knowledge, are the highest among other previously reported silicon-based PAs above 140 GHz.
{"title":"An 18 dBm 155-180 GHz SiGe Power Amplifier Using a 4-Way T-Junction Combining Network","authors":"M. Kucharski, H. Ng, D. Kissinger","doi":"10.1109/ESSCIRC.2019.8902847","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902847","url":null,"abstract":"This paper presents a 4-way power amplifier (PA) using a T-junction network for efficient power combining. The circuit was implemented using a 130 nm SiGe BiCMOS technology with fT/fMAX= 300/500 GHz. The PA achieves 30.2 dB peak linear gain at 170 GHz and more than 27.2 dB in 155-180 GHz range. At 170 GHz the circuit delivers up to 18 dBm saturated output power (P SAT) with output referred 1 dB compression point (OP 1dB) at 15.6 dBm, which to the best author’s knowledge, are the highest among other previously reported silicon-based PAs above 140 GHz.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114944540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a physically tightly coupled, logically loosely coupled, near-memory binary neural network accelerator (PTLL-BNN) is designed and fabricated. Both architecture-level and circuit-level optimizations are presented. From the perspective of processor architecture, the PTLL-BNN includes two new design choices. First, the proposed BNN accelerator is placed close to the SRAM of the embedded processors (i.e., physically tightly coupled and near-memory); thus, the extra SRAM cost that is incurred by the accelerator is as low as 0.5 KB. Second, the accelerator is a memory-mapped IO (MMIO) device (i.e., logically loosely coupled), so all embedded processors can be equipped with the proposed accelerator without the burden of changing their compilers and pipelines. From the circuit perspective, this work employs four techniques to optimize the power and costs of the accelerator. First, this design adopts a unified input-kernel-output memory instead of separate ones, which many previous works adopt. Second, the data layout that this work chooses increases the sequentiality of the SRAM accesses and reduces the buffer size of storing the intermediate values. Third, this work innovatively proposes to fuse the max-pooling, batch-normalization, and binarization layers of the BNNs to significantly reduce the hardware complexity. Finally, a novel methodology of generating the scheduler hardware of the accelerator is included. We fabricate the accelerator using the TSMC 180 nm technology. The chip measurement results reach 91 GOP/s on average (307 GOP/s at peak) at 200 MHz. The achieved GOP/s per million logic gates and GOP/s per KB SRAM are 2.6 to 237 times greater than that of previous works, respectively. We also realize an FPGA system to demonstrate the recognition of CIFAR-10/100 images using the fabricated accelerator.
{"title":"Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)","authors":"Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, Ren-Shuo Liu","doi":"10.1109/ESSCIRC.2019.8902909","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902909","url":null,"abstract":"In this paper, a physically tightly coupled, logically loosely coupled, near-memory binary neural network accelerator (PTLL-BNN) is designed and fabricated. Both architecture-level and circuit-level optimizations are presented. From the perspective of processor architecture, the PTLL-BNN includes two new design choices. First, the proposed BNN accelerator is placed close to the SRAM of the embedded processors (i.e., physically tightly coupled and near-memory); thus, the extra SRAM cost that is incurred by the accelerator is as low as 0.5 KB. Second, the accelerator is a memory-mapped IO (MMIO) device (i.e., logically loosely coupled), so all embedded processors can be equipped with the proposed accelerator without the burden of changing their compilers and pipelines. From the circuit perspective, this work employs four techniques to optimize the power and costs of the accelerator. First, this design adopts a unified input-kernel-output memory instead of separate ones, which many previous works adopt. Second, the data layout that this work chooses increases the sequentiality of the SRAM accesses and reduces the buffer size of storing the intermediate values. Third, this work innovatively proposes to fuse the max-pooling, batch-normalization, and binarization layers of the BNNs to significantly reduce the hardware complexity. Finally, a novel methodology of generating the scheduler hardware of the accelerator is included. We fabricate the accelerator using the TSMC 180 nm technology. The chip measurement results reach 91 GOP/s on average (307 GOP/s at peak) at 200 MHz. The achieved GOP/s per million logic gates and GOP/s per KB SRAM are 2.6 to 237 times greater than that of previous works, respectively. We also realize an FPGA system to demonstrate the recognition of CIFAR-10/100 images using the fabricated accelerator.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115235329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902920
M. M. Pirbazari, F. Pepe, A. Mazzanti
This paper presents a novel frequency tripler circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a 55nm SiGe-BiCMOS technology and consuming 13.6mA from 1.7V, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% factional bandwidth and robustness to power variation of the driving signal over a 15dB range.
{"title":"40GHz Frequency Tripler with High Fundamental and Harmonics Rejection in 55nm SiGe-BiCMOS","authors":"M. M. Pirbazari, F. Pepe, A. Mazzanti","doi":"10.1109/ESSCIRC.2019.8902920","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902920","url":null,"abstract":"This paper presents a novel frequency tripler circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a 55nm SiGe-BiCMOS technology and consuming 13.6mA from 1.7V, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% factional bandwidth and robustness to power variation of the driving signal over a 15dB range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121720873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-17DOI: 10.1109/ESSCIRC.2019.8902916
M. Shehata, M. Keaveney, R. Staszewski
A rotary traveling-wave oscillator (RTWO) has an ability to generate multiple phases at millimeter-wave (mmW) frequencies while achieving low phase noise (PN). Unfortunately, due to transmission line (TL) dispersion, RTWOs suffer from flicker noise upconversion. In this letter, we propose a "distributed stubs" technique to mitigate this mechanism. To cancel out phase shifts due to the TL dispersion, we intentionally generate a phase difference between TL modes. The proposed 26.2–30 GHz RTWO is implemented in 22-nm FD-SOI CMOS. At 30 GHz, it achieves PN of − 107 and −128.1 dBc/Hz at 1 and MHz 10 offsets, respectively. This translates into figure-of-merits (FoM) of 183.5 and 184.6 dBc/Hz, respectively. The proposed architecture consumes 20 mW from 0.8-V supply. It achieves a flicker noise corner of 100 kHz, which is an order-of-magnitude better than currently achievable by state-of-the-art mmW RTWOs.
{"title":"A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI","authors":"M. Shehata, M. Keaveney, R. Staszewski","doi":"10.1109/ESSCIRC.2019.8902916","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902916","url":null,"abstract":"A rotary traveling-wave oscillator (RTWO) has an ability to generate multiple phases at millimeter-wave (mmW) frequencies while achieving low phase noise (PN). Unfortunately, due to transmission line (TL) dispersion, RTWOs suffer from flicker noise upconversion. In this letter, we propose a \"distributed stubs\" technique to mitigate this mechanism. To cancel out phase shifts due to the TL dispersion, we intentionally generate a phase difference between TL modes. The proposed 26.2–30 GHz RTWO is implemented in 22-nm FD-SOI CMOS. At 30 GHz, it achieves PN of − 107 and −128.1 dBc/Hz at 1 and MHz 10 offsets, respectively. This translates into figure-of-merits (FoM) of 183.5 and 184.6 dBc/Hz, respectively. The proposed architecture consumes 20 mW from 0.8-V supply. It achieves a flicker noise corner of 100 kHz, which is an order-of-magnitude better than currently achievable by state-of-the-art mmW RTWOs.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115340248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-10DOI: 10.1109/ESSCIRC.2019.8902513
G. Nikandish, R. Staszewski, A. Zhu
In this letter, we present a design technique for broadband linearized fully integrated GaN power amplifiers (PAs). The minimum inductor bandpass filter structure is used as the output matching network to achieve low loss and high out-of-band attenuation. Two parallel transistors with unbalanced gate biases are used to mitigate nonlinearity of their transconductance and input capacitance, and consequently, compensate AM–PM distortion of the PA. A fully integrated GaN PA prototype provides 35.1–38.9-dBm output power and 40%–55% power-added efficiency (PAE) in 2.0–4.0 GHz. For a 64-QAM signal with 8-dB peak-to-average power ratio (PAPR) and 100-MHz bandwidth at 2.4 GHz, average output power of 32.7 dBm and average PAE of 31% are measured with −30.2-dB error vector magnitude (EVM).
{"title":"Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM–PM Compensation","authors":"G. Nikandish, R. Staszewski, A. Zhu","doi":"10.1109/ESSCIRC.2019.8902513","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902513","url":null,"abstract":"In this letter, we present a design technique for broadband linearized fully integrated GaN power amplifiers (PAs). The minimum inductor bandpass filter structure is used as the output matching network to achieve low loss and high out-of-band attenuation. Two parallel transistors with unbalanced gate biases are used to mitigate nonlinearity of their transconductance and input capacitance, and consequently, compensate AM–PM distortion of the PA. A fully integrated GaN PA prototype provides 35.1–38.9-dBm output power and 40%–55% power-added efficiency (PAE) in 2.0–4.0 GHz. For a 64-QAM signal with 8-dB peak-to-average power ratio (PAPR) and 100-MHz bandwidth at 2.4 GHz, average output power of 32.7 dBm and average PAE of 31% are measured with −30.2-dB error vector magnitude (EVM).","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121386284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-10DOI: 10.1109/ESSCIRC.2019.8902671
Yifan Lyu, F. Tavernier
This letter presents a single-channel high-speed hybrid voltage–time two-step analog to digital converter (ADC). Two time-based converters (TBCs) are pipelined by a capacitive DAC (CDAC) and a residue amplifier (RA). The proposed hybrid architecture minimizes the impact of the TBCs nonlinearity while maintaining a low-power consumption for a high sample rate. A unipolar voltage to time converter (VTC) and a ring oscillator (RO)-based time to digital converter (TDC) with feed-forward and 2× interpolation is used as TBC which ensures high-speed and low-power operation. The prototype ADC is fabricated in 28-nm CMOS. At 4-GS/s and a Nyquist input frequency, it achieves 39.9-dB SNDR and 47.8-dB SFDR for a power consumption of 11.7 mW. The FOMW and FOMS are 36.2 fJ/conv-step and 152.2 dB, respectively.
{"title":"A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs","authors":"Yifan Lyu, F. Tavernier","doi":"10.1109/ESSCIRC.2019.8902671","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902671","url":null,"abstract":"This letter presents a single-channel high-speed hybrid voltage–time two-step analog to digital converter (ADC). Two time-based converters (TBCs) are pipelined by a capacitive DAC (CDAC) and a residue amplifier (RA). The proposed hybrid architecture minimizes the impact of the TBCs nonlinearity while maintaining a low-power consumption for a high sample rate. A unipolar voltage to time converter (VTC) and a ring oscillator (RO)-based time to digital converter (TDC) with feed-forward and 2× interpolation is used as TBC which ensures high-speed and low-power operation. The prototype ADC is fabricated in 28-nm CMOS. At 4-GS/s and a Nyquist input frequency, it achieves 39.9-dB SNDR and 47.8-dB SFDR for a power consumption of 11.7 mW. The FOMW and FOMS are 36.2 fJ/conv-step and 152.2 dB, respectively.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115660973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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