Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902664
Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, D. Jeong
This paper presents an always-on mutual-capacitive touchscreen controller (TSC) with a reconfigurable power consumption of 0.53–13.4 mW, frame rate of 1–120 Hz, and an SNR of 40.0-46.2 dB to support not only a normal sensing mode but also a low-power (LP) and an ultra-low-power (ULP) modes. For the LP and ULP modes, the power-frame rate scalability is realized by a frame rate controller, which turns off analog front-end (AFE) transmitter (TX) and receiver (RX) periodically. Moreover, the TSC improves an out-of-band noise attenuation by utilizing a sixth-order current-mode band-pass filter and second-order incremental hybrid delta-sigma (ΔΣ) modulator, providing an SNR up to 45.8 dB when the display on. The prototype TSC is fabricated in an 80-nm high-voltage CMOS technology with an active area of 4.873 mm2.
{"title":"An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC","authors":"Young-Ha Hwang, Jonghyun Oh, Jiheon Park, Yoonho Song, Jung-Hun Park, Jun-Eun Park, D. Jeong","doi":"10.1109/ESSCIRC.2019.8902664","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902664","url":null,"abstract":"This paper presents an always-on mutual-capacitive touchscreen controller (TSC) with a reconfigurable power consumption of 0.53–13.4 mW, frame rate of 1–120 Hz, and an SNR of 40.0-46.2 dB to support not only a normal sensing mode but also a low-power (LP) and an ultra-low-power (ULP) modes. For the LP and ULP modes, the power-frame rate scalability is realized by a frame rate controller, which turns off analog front-end (AFE) transmitter (TX) and receiver (RX) periodically. Moreover, the TSC improves an out-of-band noise attenuation by utilizing a sixth-order current-mode band-pass filter and second-order incremental hybrid delta-sigma (ΔΣ) modulator, providing an SNR up to 45.8 dB when the display on. The prototype TSC is fabricated in an 80-nm high-voltage CMOS technology with an active area of 4.873 mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129737419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902874
M. Bassi, Giovanni Boi, F. Padovan, J. Fritzin, Stefano Di Martino, Daniel Knauder, A. Bevilacqua
The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.
{"title":"A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS","authors":"M. Bassi, Giovanni Boi, F. Padovan, J. Fritzin, Stefano Di Martino, Daniel Knauder, A. Bevilacqua","doi":"10.1109/ESSCIRC.2019.8902874","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902874","url":null,"abstract":"The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131239098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902650
Yongtae Lee, Woojun Choi, Taewoong Kim, Seungwoo Song, K. Makinwa, Youngcheol Chae
This letter describes a compact resistor-based temperature sensor intended for the thermal monitoring of microprocessors and DRAMs. It consists of an RC poly phase filter (PPF) that is read out by a frequency-locked loop (FLL) based on a dual zero-crossing (ZC) detection scheme. The sensor, fabricated in 65-nm CMOS, occupies 5800 μm2 and achieves moderate accuracy [±1.2 °C (3σ)] over a wide temperature range (−50 °C to 105 °C) after a one-point trim. This is 2× better than the previous compact resistor-based sensors. Operating from 0.85 to 1.3-V supplies, it consumes 32.5-μA and achieves 2.8-mK resolution in a 1-ms conversion time, which corresponds to a resolution FoM of 0.26 pJ•K2.
{"title":"A 5800-μm2 Resistor-Based Temperature Sensor With a One-Point Trimmed Inaccuracy of ±1.2 °C (3σ) From −50 °C to 105 °C in 65-nm CMOS","authors":"Yongtae Lee, Woojun Choi, Taewoong Kim, Seungwoo Song, K. Makinwa, Youngcheol Chae","doi":"10.1109/ESSCIRC.2019.8902650","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902650","url":null,"abstract":"This letter describes a compact resistor-based temperature sensor intended for the thermal monitoring of microprocessors and DRAMs. It consists of an RC poly phase filter (PPF) that is read out by a frequency-locked loop (FLL) based on a dual zero-crossing (ZC) detection scheme. The sensor, fabricated in 65-nm CMOS, occupies 5800 μm2 and achieves moderate accuracy [±1.2 °C (3σ)] over a wide temperature range (−50 °C to 105 °C) after a one-point trim. This is 2× better than the previous compact resistor-based sensors. Operating from 0.85 to 1.3-V supplies, it consumes 32.5-μA and achieves 2.8-mK resolution in a 1-ms conversion time, which corresponds to a resolution FoM of 0.26 pJ•K2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133891702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902621
Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, S. Chiang
An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.
{"title":"An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch","authors":"Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, S. Chiang","doi":"10.1109/ESSCIRC.2019.8902621","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902621","url":null,"abstract":"An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"2 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120991828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902887
Farshad Piri, Elham Rahimi, M. Bassi, F. Svelto, A. Mazzanti
A low-power quadrature local oscillator (LO) generation scheme embedded in a direct-conversion E-band transmitter (TX) is presented. A single-stage polyphase filter is closed in a loop and continuously tuned by means of a quadrature phase detector to maintain precise I/Q signals independently from LO frequency and component variations, thus making the solution wideband and robust against process, supply, and temperature variations. The analog phase detector, realized with fully balanced analog multipliers, is critical to reach high accuracy. Careful circuit analysis and simple design solutions are proposed to avoid systematic phase errors and to maintain high detector gain despite the high operating frequency. The TX, realized in BiCMOS 55-nm technology, delivers a maximum linear output power of 20.5 dBm at 80 GHz with 14% power efficiency. The LO buffers consumes 115 mW from 2.3-V supply while the LO calibration circuits need 16 mW only and allows to maintain a remarkable image rejection ratio of 40 dB or better over 70–90 GHz.
{"title":"70–90-GHz Self-Tuned Polyphase Filter for Wideband I/Q LO Generation in a 55-nm BiCMOS Transmitter","authors":"Farshad Piri, Elham Rahimi, M. Bassi, F. Svelto, A. Mazzanti","doi":"10.1109/ESSCIRC.2019.8902887","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902887","url":null,"abstract":"A low-power quadrature local oscillator (LO) generation scheme embedded in a direct-conversion E-band transmitter (TX) is presented. A single-stage polyphase filter is closed in a loop and continuously tuned by means of a quadrature phase detector to maintain precise I/Q signals independently from LO frequency and component variations, thus making the solution wideband and robust against process, supply, and temperature variations. The analog phase detector, realized with fully balanced analog multipliers, is critical to reach high accuracy. Careful circuit analysis and simple design solutions are proposed to avoid systematic phase errors and to maintain high detector gain despite the high operating frequency. The TX, realized in BiCMOS 55-nm technology, delivers a maximum linear output power of 20.5 dBm at 80 GHz with 14% power efficiency. The LO buffers consumes 115 mW from 2.3-V supply while the LO calibration circuits need 16 mW only and allows to maintain a remarkable image rejection ratio of 40 dB or better over 70–90 GHz.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129535602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902875
W. Diels, M. Steyaert, F. Tavernier
This paper presents a fully-integrated optical receiver in 28nm bulk CMOS for 1310 and 1550nm light, suitable for single-mode fiber communication. The fill factor of the Schottky photodiodes is maximized and the transimpedance amplifier is based of a voltage amplifier with high gain. This technique reduces the input-referred noise current for a given bandwidth. The receiver has a core area of 145x185µm2, while consuming 42mW. The circuit achieves data rates up to 3Gb/s at a BER of 3e-8 and a sensitivity of 0.1dBm for 1310nm light, and up to 1Gb/s at a BER of 4.8e-9 and sensitivity of 0.5dBm for 1550nm light.
{"title":"Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS","authors":"W. Diels, M. Steyaert, F. Tavernier","doi":"10.1109/ESSCIRC.2019.8902875","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902875","url":null,"abstract":"This paper presents a fully-integrated optical receiver in 28nm bulk CMOS for 1310 and 1550nm light, suitable for single-mode fiber communication. The fill factor of the Schottky photodiodes is maximized and the transimpedance amplifier is based of a voltage amplifier with high gain. This technique reduces the input-referred noise current for a given bandwidth. The receiver has a core area of 145x185µm2, while consuming 42mW. The circuit achieves data rates up to 3Gb/s at a BER of 3e-8 and a sensitivity of 0.1dBm for 1310nm light, and up to 1Gb/s at a BER of 4.8e-9 and sensitivity of 0.5dBm for 1550nm light.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125141700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902912
Y. Palaskas, P. Plechinger, A. Ravi, O. Degani, R. Banin, E. Gordon, Z. Boos, P. Madoglio, J. Angel, J. Tomasik, S. Hampel, P. Schubert, P. Preyler, T. Mayer, T. Bauernfeind
A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) to enable high-efficiency polar RFDAC for multiband and wide-channel applications. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with DCO tuning range of only 7.3–8.7 GHz (±8.7%). The TX was fabricated in 14-nm FinFET and achieves noise of −153/−150 dBc/Hz for LTE5/LTE20 in Band1 with DTC power dissipation of 27 mW. The DTC was implemented using digital Automatic-Place-and-Route tools, requiring very limited analog layout resources.
{"title":"A Cellular Multiband DTC-Based Digital Polar Transmitter With −153 dBc/Hz Noise in 14-nm FinFET","authors":"Y. Palaskas, P. Plechinger, A. Ravi, O. Degani, R. Banin, E. Gordon, Z. Boos, P. Madoglio, J. Angel, J. Tomasik, S. Hampel, P. Schubert, P. Preyler, T. Mayer, T. Bauernfeind","doi":"10.1109/ESSCIRC.2019.8902912","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902912","url":null,"abstract":"A digital polar transmitter is presented that uses a digital-to-time-converter (DTC) to enable high-efficiency polar RFDAC for multiband and wide-channel applications. The transmitter uses coarse division inherent in DTC operation to generate TX output frequencies from 0.7 to 2.2 GHz with DCO tuning range of only 7.3–8.7 GHz (±8.7%). The TX was fabricated in 14-nm FinFET and achieves noise of −153/−150 dBc/Hz for LTE5/LTE20 in Band1 with DTC power dissipation of 27 mW. The DTC was implemented using digital Automatic-Place-and-Route tools, requiring very limited analog layout resources.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123895808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902813
Alessandro Franceschin, P. Andreani, F. Padovan, M. Bassi, R. Nonis, A. Bevilacqua
Class-C operation is leveraged to implement a K-band CMOS VCO where the upconversion of the 1/f noise from the core transistors is robustly contained at a minimal level. Implemented in a bulk 28 nm CMOS technology, the VCO shows a phase noise as low as -108.5 dBc/Hz at 1 MHz offset (-83 dBc/Hz at 100 kHz offset) from the 19.5 GHz carrier, while consuming 14.4 mW and featuring a 12% tuning range.
{"title":"A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion","authors":"Alessandro Franceschin, P. Andreani, F. Padovan, M. Bassi, R. Nonis, A. Bevilacqua","doi":"10.1109/ESSCIRC.2019.8902813","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902813","url":null,"abstract":"Class-C operation is leveraged to implement a K-band CMOS VCO where the upconversion of the 1/f noise from the core transistors is robustly contained at a minimal level. Implemented in a bulk 28 nm CMOS technology, the VCO shows a phase noise as low as -108.5 dBc/Hz at 1 MHz offset (-83 dBc/Hz at 100 kHz offset) from the 19.5 GHz carrier, while consuming 14.4 mW and featuring a 12% tuning range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131582558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902896
E. Charbon
Quantum computers hold the promise to solve some of the most complex problems of today. The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits are fragile and their state needs to be corrected in real time by a classical controller. Today, the control of qubits is done at room temperature by racks of instruments, while qubits operate at several tens of milli-Kelvin. To ensure compactness, and eventually scalability, we have proposed the use of controllers operating at a few Kelvin, so as to reduce the length of control cables, while potentially enabling superconductive interconnects, which enable virtually zero resistance and low thermal conductivity. We have chosen CMOS to achieve this functionality due to its scalable nature and overall miniaturization opportunities. Cryogenic CMOS, or cryo-CMOS, circuits and systems need to be carefully designed, so as to ensure low noise and high bandwidth, while operating at strict power budgets of a few milliwatts per qubit. In this paper, we outline the requirements of a classical controller and we show examples of such circuits and systems. Results and perspectives are presented discussing a roadmap for the future.
{"title":"Cryo-CMOS Electronics for Quantum Computing Applications","authors":"E. Charbon","doi":"10.1109/ESSCIRC.2019.8902896","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902896","url":null,"abstract":"Quantum computers hold the promise to solve some of the most complex problems of today. The core of a quantum computer is a quantum processor, which is composed of quantum bits (qubits). Qubits are fragile and their state needs to be corrected in real time by a classical controller. Today, the control of qubits is done at room temperature by racks of instruments, while qubits operate at several tens of milli-Kelvin. To ensure compactness, and eventually scalability, we have proposed the use of controllers operating at a few Kelvin, so as to reduce the length of control cables, while potentially enabling superconductive interconnects, which enable virtually zero resistance and low thermal conductivity. We have chosen CMOS to achieve this functionality due to its scalable nature and overall miniaturization opportunities. Cryogenic CMOS, or cryo-CMOS, circuits and systems need to be carefully designed, so as to ensure low noise and high bandwidth, while operating at strict power budgets of a few milliwatts per qubit. In this paper, we outline the requirements of a classical controller and we show examples of such circuits and systems. Results and perspectives are presented discussing a roadmap for the future.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125301248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902789
B. Erbagci, N. E. C. Akkaya, Cagri Erbagci, K. Mai
We present an inherently secure FPGA that uses PUF-based hardware-entanglement of the configuration data and a side-channel resistant, self-timed logic style. The 3.14mm x 2.47mm testchip is fabricated in 9-metal 65nm bulk CMOS, contains the secure 10x10 tile FPGA fabric (six 6-input LUTs each), and runs at 290MHz at nominal 1V VDD and room temperature. The 38,400 PUF bits exhibit high uniqueness, randomness, and a BER < 8.1*10−12.
我们提出了一种固有安全的FPGA，它使用基于puf的硬件纠缠配置数据和抗侧信道、自定时逻辑风格。3.14mm x 2.47mm测试芯片采用9金属65nm体CMOS制造，包含安全的10x10瓦FPGA结构(每个6个6输入lut)，在标称1V VDD和室温下运行290MHz。38400位PUF具有较高的唯一性和随机性，误码率< 8.1*10−12。
{"title":"An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS","authors":"B. Erbagci, N. E. C. Akkaya, Cagri Erbagci, K. Mai","doi":"10.1109/ESSCIRC.2019.8902789","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902789","url":null,"abstract":"We present an inherently secure FPGA that uses PUF-based hardware-entanglement of the configuration data and a side-channel resistant, self-timed logic style. The 3.14mm x 2.47mm testchip is fabricated in 9-metal 65nm bulk CMOS, contains the secure 10x10 tile FPGA fabric (six 6-input LUTs each), and runs at 290MHz at nominal 1V VDD and room temperature. The 38,400 PUF bits exhibit high uniqueness, randomness, and a BER < 8.1*10−12.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125315871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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