Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902862
Alberto Gatti, G. Spiazzi, A. Gerosa, A. Neviani, A. Bevilacqua
This letter presents a dc–dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.
{"title":"A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications","authors":"Alberto Gatti, G. Spiazzi, A. Gerosa, A. Neviani, A. Bevilacqua","doi":"10.1109/ESSCIRC.2019.8902862","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902862","url":null,"abstract":"This letter presents a dc–dc converter realized in a 130-nm CMOS technology that features the same conversion gain as a standard boost converter, but it is able to process a dual polarity input with a magnitude down to 60 mV. The circuit prototypes feature a regulated output voltage of 1.2 V, an efficiency up to 88% and a maximum output power of 6 mW, while limiting the number of required off-chip components to two capacitors and one inductor.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131947614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902863
Qin Kuai, Qiping Wan, P. Mok
A single-inductor dual-input dual-output interface based on a Buck-Boost converter is proposed for thermoelectric energy harvesting. Triple operation modes involving energy harvesting and recycling make the interface qualified for a wide range of load power from zero to a few milliwatts. A dual-frequency operation allows high efficiencies for all the modes. Parameters optimization also reduces the total loss within the system. A novel zero-current switching technique is utilized to realize an accurate switching with little overhead. The proposed interface is implemented in a 0.13-µm CMOS process. The input voltage ranges from 30 mV to 440 mV. The peak efficiency for energy harvesting is 82.9% for 791 µW available power. Higher than 70% efficiency is achieved over the available power range of 26 µW to 914 µW. The power consumption of the control circuits is 308 nW.
{"title":"A Dual-Frequency Dual-Input-Dual-Output Interface for Thermoelectric Energy Harvesting and Recycling With 82.9% Efficiency","authors":"Qin Kuai, Qiping Wan, P. Mok","doi":"10.1109/ESSCIRC.2019.8902863","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902863","url":null,"abstract":"A single-inductor dual-input dual-output interface based on a Buck-Boost converter is proposed for thermoelectric energy harvesting. Triple operation modes involving energy harvesting and recycling make the interface qualified for a wide range of load power from zero to a few milliwatts. A dual-frequency operation allows high efficiencies for all the modes. Parameters optimization also reduces the total loss within the system. A novel zero-current switching technique is utilized to realize an accurate switching with little overhead. The proposed interface is implemented in a 0.13-µm CMOS process. The input voltage ranges from 30 mV to 440 mV. The peak efficiency for energy harvesting is 82.9% for 791 µW available power. Higher than 70% efficiency is achieved over the available power range of 26 µW to 914 µW. The power consumption of the control circuits is 308 nW.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133546369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902914
M. Rajabzadeh, Matthias Häberle, Ankesh Jain, M. Ortmanns
This work presents a current input continuous-time sigma-delta modulator (C-CTΣ∆M) for biomedical application such as electrochemical impedance spectroscopy. Low noise and low area current input digitizers are required to implement high spatial resolution multi electrode arrays. In this work, the use of a switched capacitor with resistor D/A converter (SCR-DAC) for the C-CTΣ∆M is proposed for this purpose. SCR-DACs offer the realization of large resistances on small area, which leads to a very small area consumption combined with good noise performance. A C-CTΣ∆M with an SCR-DAC prototype is fabricated in a 180-nm CMOS process. The implemented ADC occupies an area of only 120 × 200 µm2. In order to increase the dynamic range (DR) of the C-CTΣ∆M, two modes have been implemented. In the low noise configuration an integrated in band noise of 157-pArms in the signal band width of 100 kHz with a peak SNDR of 62 dB is achieved. In the high DR configuration a peak SNDR of 72 dB with an MSA of -4.1 dB corresponding to 9.1 µA is measured. The complete C-CTΣ∆M consumes 2 mW from a 3-V supply and achieves a total DR of 95 dB.
{"title":"An Integrated Readout for Current Sensing based on a Σ∆ Modulator with Switched Capacitor Feedback","authors":"M. Rajabzadeh, Matthias Häberle, Ankesh Jain, M. Ortmanns","doi":"10.1109/ESSCIRC.2019.8902914","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902914","url":null,"abstract":"This work presents a current input continuous-time sigma-delta modulator (C-CTΣ∆M) for biomedical application such as electrochemical impedance spectroscopy. Low noise and low area current input digitizers are required to implement high spatial resolution multi electrode arrays. In this work, the use of a switched capacitor with resistor D/A converter (SCR-DAC) for the C-CTΣ∆M is proposed for this purpose. SCR-DACs offer the realization of large resistances on small area, which leads to a very small area consumption combined with good noise performance. A C-CTΣ∆M with an SCR-DAC prototype is fabricated in a 180-nm CMOS process. The implemented ADC occupies an area of only 120 × 200 µm2. In order to increase the dynamic range (DR) of the C-CTΣ∆M, two modes have been implemented. In the low noise configuration an integrated in band noise of 157-pArms in the signal band width of 100 kHz with a peak SNDR of 62 dB is achieved. In the high DR configuration a peak SNDR of 72 dB with an MSA of -4.1 dB corresponding to 9.1 µA is measured. The complete C-CTΣ∆M consumes 2 mW from a 3-V supply and achieves a total DR of 95 dB.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134166266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902894
M. Scholl, R. Wunderlich, S. Heinen, Tobias Saalfeld, Christoph Beyerstedt, Fabian Speicher, Jonas Meier, Michael Hanhart, Leo Rolff, V. Bonehi, M. Schrey
This work presents a fast start-up 32 MHz crystal oscillator for low power wireless transceivers. A highly efficient start-up technique combining dithered frequency injection and a negative resistance boost is proposed to reduce start-up time while maintaining low start-up energy. In measurements the proposed technique achieves a start-up time of 32.7 μs with 31.7 nJ startup energy enabling low power consumption in latency-driven applications. In steady state operation the oscillator has a power consumption of 181.6 μW. The circuit area of the proposed crystal oscillator is 0.058 mm2 in a 130 nm RF CMOS technology.
{"title":"A 32 MHz Crystal Oscillator with Fast Start-Up Using Dithered Injection and Negative Resistance Boost","authors":"M. Scholl, R. Wunderlich, S. Heinen, Tobias Saalfeld, Christoph Beyerstedt, Fabian Speicher, Jonas Meier, Michael Hanhart, Leo Rolff, V. Bonehi, M. Schrey","doi":"10.1109/ESSCIRC.2019.8902894","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902894","url":null,"abstract":"This work presents a fast start-up 32 MHz crystal oscillator for low power wireless transceivers. A highly efficient start-up technique combining dithered frequency injection and a negative resistance boost is proposed to reduce start-up time while maintaining low start-up energy. In measurements the proposed technique achieves a start-up time of 32.7 μs with 31.7 nJ startup energy enabling low power consumption in latency-driven applications. In steady state operation the oscillator has a power consumption of 181.6 μW. The circuit area of the proposed crystal oscillator is 0.058 mm2 in a 130 nm RF CMOS technology.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125607701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed 6.78-MHz Class-E receiver features a soft-switching and temperature-compensated GaN-based active diode (GAD) rectifier design. Using the temperature dependence of the relationship between the driving voltage and the on-resistance of the switch, the gate-source control voltage of GaN can be adjusted to mitigate efficiency variations based on temperature effects. Moreover, a phase shift comparator activation controller is based on the direct relationship between the phase delay on the gate drive signals and the output power. The temperature dependency voltage offset of the comparator is alleviated with auto-zeroing. GAD rectifier ensures energy transfer up to 61 W and 6.8 A, high efficiency of 92%, and low harmonic distortion of 2.1%.
{"title":"A Temperature Compensated 61-W Class-E Soft-Switching GaN-Based Active Diode Rectifier for Wireless Power Transfer Applications","authors":"Shang-Hsien Yang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai","doi":"10.1109/ESSCIRC.2019.8902866","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902866","url":null,"abstract":"The proposed 6.78-MHz Class-E receiver features a soft-switching and temperature-compensated GaN-based active diode (GAD) rectifier design. Using the temperature dependence of the relationship between the driving voltage and the on-resistance of the switch, the gate-source control voltage of GaN can be adjusted to mitigate efficiency variations based on temperature effects. Moreover, a phase shift comparator activation controller is based on the direct relationship between the phase delay on the gate drive signals and the output power. The temperature dependency voltage offset of the comparator is alleviated with auto-zeroing. GAD rectifier ensures energy transfer up to 61 W and 6.8 A, high efficiency of 92%, and low harmonic distortion of 2.1%.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128983092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902892
Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
Ring amplifier has been shown as an alternative to an OTA for its low power consumption and large output swing in low-voltage, deep nanoscale CMOS processes. The robustness of the ring amplifier is an important consideration for its application in products. A transient amplification analysis in this paper reveals the difference between the DC gain and the effective gain of the ring amplifier at different output voltages. This non-linear gain error varies with process corner, supply voltage and temperature (PVT) variation. To compensate this gain error, a calibration method is proposed based on the code density analysis of the output data from the back-end stages. Designed in a 1 V 28 nm CMOS process, a prototype SAR assisted pipeline ADC is proposed with a quick-start ring amplifier. The 12-bit ADC achieves 59.3 dB SNDR and 74.4 dB SFDR with a 6 MHz input and a sample rate up to 625 MS/s. The ADC has measured SNDR and SFDR of 57.2 dB and 67.8 dB, respectively, for a Nyquist frequency input and consumes 13.2mW. The measured SNDR and SFDR remains above 53.5 dB and 66.3 dB for a -6dBFs 50 MHz input with supply voltage and temperature variation.
环形放大器在低电压、深纳米级CMOS工艺中具有低功耗和大输出摆幅的优点，已被证明是OTA的替代品。环形放大器的鲁棒性是其在实际应用中的重要考虑因素。本文通过瞬态放大分析，揭示了环形放大器在不同输出电压下的直流增益与有效增益之间的差异。该非线性增益误差随工艺转角、电源电压和温度(PVT)的变化而变化。为了补偿增益误差，提出了一种基于后端输出数据码密度分析的校正方法。采用1 V 28 nm CMOS工艺设计了一种带快速启动环形放大器的SAR辅助流水线ADC样机。12位ADC可实现59.3 dB SNDR和74.4 dB SFDR，输入频率为6mhz，采样率高达625 MS/s。对于奈奎斯特频率输入，ADC的SNDR和SFDR分别为57.2 dB和67.8 dB，功耗为13.2mW。在电源电压和温度变化的-6dBFs 50mhz输入下，测量到的SNDR和SFDR分别保持在53.5 dB和66.3 dB以上。
{"title":"A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps","authors":"Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren","doi":"10.1109/ESSCIRC.2019.8902892","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902892","url":null,"abstract":"Ring amplifier has been shown as an alternative to an OTA for its low power consumption and large output swing in low-voltage, deep nanoscale CMOS processes. The robustness of the ring amplifier is an important consideration for its application in products. A transient amplification analysis in this paper reveals the difference between the DC gain and the effective gain of the ring amplifier at different output voltages. This non-linear gain error varies with process corner, supply voltage and temperature (PVT) variation. To compensate this gain error, a calibration method is proposed based on the code density analysis of the output data from the back-end stages. Designed in a 1 V 28 nm CMOS process, a prototype SAR assisted pipeline ADC is proposed with a quick-start ring amplifier. The 12-bit ADC achieves 59.3 dB SNDR and 74.4 dB SFDR with a 6 MHz input and a sample rate up to 625 MS/s. The ADC has measured SNDR and SFDR of 57.2 dB and 67.8 dB, respectively, for a Nyquist frequency input and consumes 13.2mW. The measured SNDR and SFDR remains above 53.5 dB and 66.3 dB for a -6dBFs 50 MHz input with supply voltage and temperature variation.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902825
Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang
In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.
{"title":"An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications","authors":"Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang","doi":"10.1109/ESSCIRC.2019.8902825","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902825","url":null,"abstract":"In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131376230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902571
Enrico Manuzzato, E. Gioscio, I. Mattei, R. Mirabelli, V. Patera, A. Sarti, A. Schiavi, A. Sciubba, S. M. Valle, G. Traini, M. Marafini, L. Gasparini, M. Perenzoni, Yu Zou, L. Parmesan, G. Battistoni, M. D. Simoni, Y. Dong, M. Fischetti
This letter describes a 16 × 8-pixel array based on single-photon avalanche diodes (SPADs) optimized for the readout of a tracking detector based on plastic scintillation fibers targeting ultra-fast neutrons. Each pixel of 125 × 250 µm2 size contains 30 SPADs, an 80-ps 10-b time-to-digital converter (TDC), a 5-b intensity counter, a finite state machine (FSM) that manages the recording of data and a three-word-deep FIFO memory for parallel acquisition and readout, achieving 32.1% pixel fill factor. A combined, programmable current-based local, and global triggering mechanism correlates the photon detection activity in time to distinguish asynchronous charged particle trace events from background noise even with a poor SNR.
{"title":"A 16 × 8 Digital-SiPM Array With Distributed Trigger Generator for Low SNR Particle Tracking","authors":"Enrico Manuzzato, E. Gioscio, I. Mattei, R. Mirabelli, V. Patera, A. Sarti, A. Schiavi, A. Sciubba, S. M. Valle, G. Traini, M. Marafini, L. Gasparini, M. Perenzoni, Yu Zou, L. Parmesan, G. Battistoni, M. D. Simoni, Y. Dong, M. Fischetti","doi":"10.1109/ESSCIRC.2019.8902571","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902571","url":null,"abstract":"This letter describes a 16 × 8-pixel array based on single-photon avalanche diodes (SPADs) optimized for the readout of a tracking detector based on plastic scintillation fibers targeting ultra-fast neutrons. Each pixel of 125 × 250 µm2 size contains 30 SPADs, an 80-ps 10-b time-to-digital converter (TDC), a 5-b intensity counter, a finite state machine (FSM) that manages the recording of data and a three-word-deep FIFO memory for parallel acquisition and readout, achieving 32.1% pixel fill factor. A combined, programmable current-based local, and global triggering mechanism correlates the photon detection activity in time to distinguish asynchronous charged particle trace events from background noise even with a poor SNR.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902928
M. Eberlein, H. Pretl
We present a simple, yet robust architecture to achieve accurate temperature sensing without the need for costly calibration. For the first time, the active bulk diode of a standard CMOS process is utilized in replacement of BJT devices. Two such diodes are forward biased by a charge pump, which periodically discharges two sampling capacitors across the diodes. The sampled voltages are then combined to generate PTAT and CTAT signals. A passive charge-balancing scheme creates a digital output, which only requires a comparator, an 8-bit capacitive divider and SAR logic. Occupying 2500 µm2 active area in 16-nm FinFET, the sensor operates down to 0.85 V and features intrinsic supply robustness. It achieves an uncalibrated accuracy of +1.5/−2.0 °C (min/max) across the consumer temperature range, and dissipates 230 pJ in a 12.8 µs conversion time. Due to the simplicity and low analog content of this concept, it is insensitive to future scaling and well suited for use at multiple locations in SoCs.
{"title":"A No-Trim, Scaling-Friendly Thermal Sensor in 16nm FinFET Using Bulk Diodes as Sensing Elements","authors":"M. Eberlein, H. Pretl","doi":"10.1109/ESSCIRC.2019.8902928","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902928","url":null,"abstract":"We present a simple, yet robust architecture to achieve accurate temperature sensing without the need for costly calibration. For the first time, the active bulk diode of a standard CMOS process is utilized in replacement of BJT devices. Two such diodes are forward biased by a charge pump, which periodically discharges two sampling capacitors across the diodes. The sampled voltages are then combined to generate PTAT and CTAT signals. A passive charge-balancing scheme creates a digital output, which only requires a comparator, an 8-bit capacitive divider and SAR logic. Occupying 2500 µm2 active area in 16-nm FinFET, the sensor operates down to 0.85 V and features intrinsic supply robustness. It achieves an uncalibrated accuracy of +1.5/−2.0 °C (min/max) across the consumer temperature range, and dissipates 230 pJ in a 12.8 µs conversion time. Due to the simplicity and low analog content of this concept, it is insensitive to future scaling and well suited for use at multiple locations in SoCs.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116644128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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