Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902869
Rehman Akbar, E. Klumperink, N. Tervo, M. Javed, K. Stadius, T. Rahkonen, A. Pärssinen
Large-scale phased arrays need to combine weighted signals from multiple sub-arrays either in analog or in digital domain. Sub-arrays are preferably implemented modularly with integrated circuits placed next to the associated antennas. In order to enable flexible and scalable combining networks of several mmWave sub-arrays, this paper presents a wideband receiver module that provides the cartesian combining of beamforming weights for one sub-array at IF. Furthermore, it allows interference cancellation between sub-arrays or combining multiple sub-arrays. It also provides filtering before ADCs to support current and foreseeable 5G channel bandwidths up to 800MHz. The receiver is operating at 2-4GHz IF frequency range and has more than 400MHz baseband bandwidth, a noise-figure of 5.5dB, -6dBm 1dB compression point and +3dBm in-band IIP3. In addition, over-the-air measurements are performed, showing 26dB of interference cancellation between the sub-arrays. The prototype is implemented using 45nm CMOS PDSOI.
{"title":"A Wideband IF Receiver Module for Flexibly Scalable mmWave Beamforming Combining and Interference Cancellation","authors":"Rehman Akbar, E. Klumperink, N. Tervo, M. Javed, K. Stadius, T. Rahkonen, A. Pärssinen","doi":"10.1109/ESSCIRC.2019.8902869","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902869","url":null,"abstract":"Large-scale phased arrays need to combine weighted signals from multiple sub-arrays either in analog or in digital domain. Sub-arrays are preferably implemented modularly with integrated circuits placed next to the associated antennas. In order to enable flexible and scalable combining networks of several mmWave sub-arrays, this paper presents a wideband receiver module that provides the cartesian combining of beamforming weights for one sub-array at IF. Furthermore, it allows interference cancellation between sub-arrays or combining multiple sub-arrays. It also provides filtering before ADCs to support current and foreseeable 5G channel bandwidths up to 800MHz. The receiver is operating at 2-4GHz IF frequency range and has more than 400MHz baseband bandwidth, a noise-figure of 5.5dB, -6dBm 1dB compression point and +3dBm in-band IIP3. In addition, over-the-air measurements are performed, showing 26dB of interference cancellation between the sub-arrays. The prototype is implemented using 45nm CMOS PDSOI.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124137945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902809
Deepak Kadetotad, Visar Berisha, C. Chakrabarti, Jae-sun Seo
Long short-term memory (LSTM) networks are widely used for speech applications but pose difficulties for efficient implementation on hardware due to large weight storage requirements. We present an energy-efficient LSTM recurrent neural network (RNN) accelerator, featuring an algorithm-hardware co-optimized memory compression technique called hierarchical coarse-grain sparsity (HCGS). Aided by HCGS-based block-wise recursive weight compression, we demonstrate LSTM networks with up to 16× fewer weights while achieving minimal accuracy loss. The prototype chip fabricated in 65-nm LP CMOS achieves 8.93/7.22 TOPS/W for 2-/3-layer LSTM RNNs trained with HCGS for TIMIT/TED-LIUM corpora.
{"title":"A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip","authors":"Deepak Kadetotad, Visar Berisha, C. Chakrabarti, Jae-sun Seo","doi":"10.1109/ESSCIRC.2019.8902809","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902809","url":null,"abstract":"Long short-term memory (LSTM) networks are widely used for speech applications but pose difficulties for efficient implementation on hardware due to large weight storage requirements. We present an energy-efficient LSTM recurrent neural network (RNN) accelerator, featuring an algorithm-hardware co-optimized memory compression technique called hierarchical coarse-grain sparsity (HCGS). Aided by HCGS-based block-wise recursive weight compression, we demonstrate LSTM networks with up to 16× fewer weights while achieving minimal accuracy loss. The prototype chip fabricated in 65-nm LP CMOS achieves 8.93/7.22 TOPS/W for 2-/3-layer LSTM RNNs trained with HCGS for TIMIT/TED-LIUM corpora.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902347
Dongfang Pan, Zongming Duan, Liguo Sun, Shita Guo, Lin Cheng, P. Gui
This paper presents a 77 GHz power amplifier (PA) for multiple-input-multiple-output (MIMO) automotive radar with high output power, reconfigurable gain, and 0/180º phase shifting capability, by using TSMC 65 nm CMOS general purpose (GP) technology. The PA has a variable gain amplifier (VGA) design merged with a phase shifter, a power splitter, two-way double-neutralized PA cell, and a balun-based power combiner. Measurement results show that the saturation output power (PSAT) is 16.1 dBm with maximum PAE of 12.8% at 79 GHz, a peak power gain of -5-25 dB is tunable at 77 GHz, and 0/180º phase shifter is achieved over 76-81 GHz. The power consumption of the PA is 356 mW.
{"title":"A 76-81 GHz CMOS PA with 16-dBm PSAT and 30-dB Amplitude Control for MIMO Automotive Radars","authors":"Dongfang Pan, Zongming Duan, Liguo Sun, Shita Guo, Lin Cheng, P. Gui","doi":"10.1109/ESSCIRC.2019.8902347","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902347","url":null,"abstract":"This paper presents a 77 GHz power amplifier (PA) for multiple-input-multiple-output (MIMO) automotive radar with high output power, reconfigurable gain, and 0/180º phase shifting capability, by using TSMC 65 nm CMOS general purpose (GP) technology. The PA has a variable gain amplifier (VGA) design merged with a phase shifter, a power splitter, two-way double-neutralized PA cell, and a balun-based power combiner. Measurement results show that the saturation output power (PSAT) is 16.1 dBm with maximum PAE of 12.8% at 79 GHz, a peak power gain of -5-25 dB is tunable at 77 GHz, and 0/180º phase shifter is achieved over 76-81 GHz. The power consumption of the PA is 356 mW.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"115 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126376505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902881
M. Solé, A. Bischof, Lorenzo Bergamini, P. Dallemagne, S. Emery, Komail M. H. Badami, Jiang Deng, T. Mavrogordatos, E. Azarkhish, Loïc Zahnd, C. Cosentino, M. Augustyniak, Y. Zha
This work introduces a highly integrated and a power-efficient SoC with 20 EMG sensing channels, a 32b RISC core with a host of peripherals and a companion RF transceiver chip in the 55 nm CMOS technology to enable real-time Osseo-integrated prosthesis control and is aimed at recovery of hand function after amputation. The EMG processing channels include temperature compensated pseudo-resistors in highly programmable gain stages, a 4th order Chebyshev low-pass filter with enhanced linearity and 12b SAR ADC operating in the programmable range of 1.2MS/s to 125kS/s for multichannel EMG signal digitization. The digital back-end includes an EMG pre-processing accelerator and a 32b RISC processor that optimizes the power-consumption of the companion RF transceiver to improve the power-efficiency of the the prosthesis control system.
这项工作介绍了一个高集成和低功耗的SoC，具有20个肌电信号传感通道，一个32b的RISC内核和一系列外围设备，以及一个55纳米CMOS技术的射频收发器芯片，以实现实时骨集成假肢控制，旨在截肢后手部功能的恢复。EMG处理通道包括高度可编程增益级的温度补偿伪电阻，增强线性度的4阶切比雪夫低通滤波器和12b SAR ADC，工作在1.2MS/s至125kS/s的可编程范围内，用于多通道EMG信号数字化。数字后端包括一个肌电信号预处理加速器和一个32b RISC处理器，该处理器优化了配套射频收发器的功耗，以提高假肢控制系统的功率效率。
{"title":"A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control","authors":"M. Solé, A. Bischof, Lorenzo Bergamini, P. Dallemagne, S. Emery, Komail M. H. Badami, Jiang Deng, T. Mavrogordatos, E. Azarkhish, Loïc Zahnd, C. Cosentino, M. Augustyniak, Y. Zha","doi":"10.1109/ESSCIRC.2019.8902881","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902881","url":null,"abstract":"This work introduces a highly integrated and a power-efficient SoC with 20 EMG sensing channels, a 32b RISC core with a host of peripherals and a companion RF transceiver chip in the 55 nm CMOS technology to enable real-time Osseo-integrated prosthesis control and is aimed at recovery of hand function after amputation. The EMG processing channels include temperature compensated pseudo-resistors in highly programmable gain stages, a 4th order Chebyshev low-pass filter with enhanced linearity and 12b SAR ADC operating in the programmable range of 1.2MS/s to 125kS/s for multichannel EMG signal digitization. The digital back-end includes an EMG pre-processing accelerator and a 32b RISC processor that optimizes the power-consumption of the companion RF transceiver to improve the power-efficiency of the the prosthesis control system.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902752
Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok
This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.
{"title":"C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing","authors":"Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok","doi":"10.1109/ESSCIRC.2019.8902752","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902752","url":null,"abstract":"This letter presents C3SRAM, an in-memory-computing SRAM macro, which utilizes analog-mixed-signal capacitive-coupling computing to perform XNOR-and-accumulate operations for binary deep neural networks. The 256 × 64 C3SRAM macro asserts all 256 rows simultaneously and equips one ADC per column, realizing fully parallel vector-matrix multiplication in one cycle. C3SRAM demonstrates 672 TOPS/W and 1638 GOPS, and achieves 98.3% accuracy for MNIST and 85.5% for CIFAR-10 dataset. It achieves 3975× smaller energy-delay product than conventional digital processors.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134370829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902771
P. Horský, J. Plojhar, Jiri Daniel
This letter describes a new average current control dc–dc LED driver suitable for automotive pixel (matrix) lighting. Current is sensed only on an integrated high side switch and peak current is controlled to achieve required average output current independent of tolerances of components and parameters other than the current sensing itself. Fast reaction to output voltage changes required by the pixel light operation is achieved by using a constant ripple control with an off time inversely proportional to the output voltage.
{"title":"Adaptive Peak Average Current Control LED Driver for Automotive Lighting","authors":"P. Horský, J. Plojhar, Jiri Daniel","doi":"10.1109/ESSCIRC.2019.8902771","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902771","url":null,"abstract":"This letter describes a new average current control dc–dc LED driver suitable for automotive pixel (matrix) lighting. Current is sensed only on an integrated high side switch and peak current is controlled to achieve required average output current independent of tolerances of components and parameters other than the current sensing itself. Fast reaction to output voltage changes required by the pixel light operation is achieved by using a constant ripple control with an off time inversely proportional to the output voltage.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127729705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902597
Li-Yang Chen, C. Yang
This letter presents a pulsed-coherent time-of-flight (ToF) receiver for a laser ranging system implemented in 28-nm CMOS process. The prototype is designed at 19-GHz carrier frequency with 6.8-ns pulsed modulation. A segmented coarse-fine ToF measurement is adopted to achieve high resolution and fast acquisition. The coarse ToF is recorded by detecting the pulse’s edge whereas the fine measurement is measured by coherent detection. The proposed post-edge detection with automatic gain control loop provides better suppression of walk error from 600 to 26 ps as compared to the rising-edge detection. Also, phase-invariant variable-gain amplifiers provide a low phase error of <± 1° across gain settings with 60-dB dynamic range. This letter can, based on the timing accuracy, achieve 40-µm precision with 1-MHz sampling rate.
{"title":"A 19-GHz Pulsed-Coherent ToF Receiver With 40-μm Precision for Laser Ranging Systems","authors":"Li-Yang Chen, C. Yang","doi":"10.1109/ESSCIRC.2019.8902597","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902597","url":null,"abstract":"This letter presents a pulsed-coherent time-of-flight (ToF) receiver for a laser ranging system implemented in 28-nm CMOS process. The prototype is designed at 19-GHz carrier frequency with 6.8-ns pulsed modulation. A segmented coarse-fine ToF measurement is adopted to achieve high resolution and fast acquisition. The coarse ToF is recorded by detecting the pulse’s edge whereas the fine measurement is measured by coherent detection. The proposed post-edge detection with automatic gain control loop provides better suppression of walk error from 600 to 26 ps as compared to the rising-edge detection. Also, phase-invariant variable-gain amplifiers provide a low phase error of <± 1° across gain settings with 60-dB dynamic range. This letter can, based on the timing accuracy, achieve 40-µm precision with 1-MHz sampling rate.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902911
J. Uehlin, W. A. Smith, V. R. Pamula, S. Perlmutter, V. Sathe, J. Rudell
A single-chip bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This paper presents a prototype BBCI ASIC including a 64-channel time-multiplexed recording front-end, 4-channel high-voltage compliant resonant-stimulator and electronics to support concurrent multi-channel differential- and common-mode stimulus artifact cancellation. A cascaded charge pump-based stimulation driver provides +/-11V compliance using 1.2V devices. High-frequency (~3GHz), self-resonant clocking is used to reduce capacitor area while suppressing associated switching losses. A 32-tap LMS-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip is powered by 2.5/1.2V supplies, dissipating 205µW in recording, 142µW in the cancellation back-end, and 31% DC-DC efficiency in the stimulation drivers, each with a maximum output power of 24mW. This 4mm2 neural interface chip was implemented in 65nm 1P9M LP CMOS.
{"title":"A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS","authors":"J. Uehlin, W. A. Smith, V. R. Pamula, S. Perlmutter, V. Sathe, J. Rudell","doi":"10.1109/ESSCIRC.2019.8902911","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902911","url":null,"abstract":"A single-chip bidirectional brain-computer interface (BBCI) enables neuromodulation through simultaneous neural recording and stimulation. This paper presents a prototype BBCI ASIC including a 64-channel time-multiplexed recording front-end, 4-channel high-voltage compliant resonant-stimulator and electronics to support concurrent multi-channel differential- and common-mode stimulus artifact cancellation. A cascaded charge pump-based stimulation driver provides +/-11V compliance using 1.2V devices. High-frequency (~3GHz), self-resonant clocking is used to reduce capacitor area while suppressing associated switching losses. A 32-tap LMS-based digital adaptive filter achieves 60-dB artifact suppression, enabling simultaneous neural stimulation and recording. The entire chip is powered by 2.5/1.2V supplies, dissipating 205µW in recording, 142µW in the cancellation back-end, and 31% DC-DC efficiency in the stimulation drivers, each with a maximum output power of 24mW. This 4mm2 neural interface chip was implemented in 65nm 1P9M LP CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115103799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902769
T. Matsui, Keisaku Sento, T. Ebata, A. Ishibashi
In this letter, the influence on an analog-to-digital converter (ADC) of the dielectric relaxation effect of a metal–oxide–metal (MOM) capacitor is described, agreement of a capacitance model with simulations is shown, and a circuit for canceling the dielectric relaxation effect is proposed. When using an MOM capacitor that exhibits dielectric relaxation in an SAR-ADC for an MCU, accuracy is degraded by switching between multiple analog inputs due to the slow charge and discharge components in the capacitors. In this letter a circuit is proposed in which, by applying the same voltage stress on a local DAC at the negative side input of a comparator as on that at the positive one which samples the single-ended input and performs bit decisions, the influence of the dielectric relaxation effect is converted into common mode error and can be canceled by a differential-input comparator. This ADC is fabricated in a 28-nm embedded flash memory process, and in operation at 5 V and 1 MSps achieves an absolute accuracy error of −1.69/1.38 LSB, an INL of −0.50/0.65 LSB, and a DNL of −0.40/0.28 LSB without being affected by dielectric relaxation.
{"title":"A Capacitor Dielectric Relaxation Effect Cancellation Circuit in a 12-Bit, 1-MSps, 5.0-V SAR ADC on a 28-nm Embedded Flash Memory Microcontroller","authors":"T. Matsui, Keisaku Sento, T. Ebata, A. Ishibashi","doi":"10.1109/ESSCIRC.2019.8902769","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902769","url":null,"abstract":"In this letter, the influence on an analog-to-digital converter (ADC) of the dielectric relaxation effect of a metal–oxide–metal (MOM) capacitor is described, agreement of a capacitance model with simulations is shown, and a circuit for canceling the dielectric relaxation effect is proposed. When using an MOM capacitor that exhibits dielectric relaxation in an SAR-ADC for an MCU, accuracy is degraded by switching between multiple analog inputs due to the slow charge and discharge components in the capacitors. In this letter a circuit is proposed in which, by applying the same voltage stress on a local DAC at the negative side input of a comparator as on that at the positive one which samples the single-ended input and performs bit decisions, the influence of the dielectric relaxation effect is converted into common mode error and can be canceled by a differential-input comparator. This ADC is fabricated in a 28-nm embedded flash memory process, and in operation at 5 V and 1 MSps achieves an absolute accuracy error of −1.69/1.38 LSB, an INL of −0.50/0.65 LSB, and a DNL of −0.40/0.28 LSB without being affected by dielectric relaxation.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125253017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902861
J. van Staveren, C. García Almudéver, Giordano Scappucci, M. Veldhorst, M. Babaie, E. Charbon, F. Sebastiano
This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2 K to 300 K. The proposed references achieve a temperature drift below 436 ppm/K over a statistically significant number of samples after a single-point trim and a supply regulation better than 1.7 %/V from a a supply as low as 0.99 V. These results demonstrate, for the first time, the generation of PVT-independent voltages over an ultra-wide temperature range using sub-1-V nanometer CMOS circuits, thus enabling the use of the proposed references in harsh environments, such as in space and quantum-computing applications.
{"title":"Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS","authors":"J. van Staveren, C. García Almudéver, Giordano Scappucci, M. Veldhorst, M. Babaie, E. Charbon, F. Sebastiano","doi":"10.1109/ESSCIRC.2019.8902861","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902861","url":null,"abstract":"This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2 K to 300 K. The proposed references achieve a temperature drift below 436 ppm/K over a statistically significant number of samples after a single-point trim and a supply regulation better than 1.7 %/V from a a supply as low as 0.99 V. These results demonstrate, for the first time, the generation of PVT-independent voltages over an ultra-wide temperature range using sub-1-V nanometer CMOS circuits, thus enabling the use of the proposed references in harsh environments, such as in space and quantum-computing applications.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125486352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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