Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902575
Yusang Chun, Ashwin Ramachandran, Tejasvi Anand
A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.
{"title":"A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS","authors":"Yusang Chun, Ashwin Ramachandran, Tejasvi Anand","doi":"10.1109/ESSCIRC.2019.8902575","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902575","url":null,"abstract":"A PAM-8 wireline transceiver with receiver-side PWM (time-domain) based feed forward equalization is presented. The receiver converts voltage modulated signals to pulse width modulated signals and processes them using delay elements. Time-to-voltage and voltage-to-time converters are designed to have non-linearity with opposite signs with the aim of achieving higher front-end linearity. The proposed PAM-8 transceiver can operate from 12.0 Gb/s to 39.6 Gb/s and compensates 14 dB loss at 6.6 GHz with an efficiency of 8.66 pJ/bit in 65nm CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129129975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902790
A. Ramkaj, M. Steyaert, F. Tavernier
We present a three-stage triple-latch feedforward fully dynamic comparator, with an achievable data rate of 13.5 Gb/s and a BER < 10−12 for input amplitudes as small as 5 mVpp-diff. The combination of a high gain three-stage configuration and an extra parallel feedforward path results in a maximum CLK–OUT delay of only 26.8 ps and a delay slope of 6.4 ps/decade. Furthermore, the cascaded triple-latch architecture with minimized stacking enables a < 70-ps delay across a wide common-mode (VCM) and supply (VDD) range. The prototype comparator in 28-nm bulk CMOS dissipates 2.2 mW at 13.5 Gb/s and 5 mVpp-diff from a 1-V supply, for a core area of 78 µm2.
{"title":"A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS","authors":"A. Ramkaj, M. Steyaert, F. Tavernier","doi":"10.1109/ESSCIRC.2019.8902790","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902790","url":null,"abstract":"We present a three-stage triple-latch feedforward fully dynamic comparator, with an achievable data rate of 13.5 Gb/s and a BER < 10−12 for input amplitudes as small as 5 mVpp-diff. The combination of a high gain three-stage configuration and an extra parallel feedforward path results in a maximum CLK–OUT delay of only 26.8 ps and a delay slope of 6.4 ps/decade. Furthermore, the cascaded triple-latch architecture with minimized stacking enables a < 70-ps delay across a wide common-mode (VCM) and supply (VDD) range. The prototype comparator in 28-nm bulk CMOS dissipates 2.2 mW at 13.5 Gb/s and 5 mVpp-diff from a 1-V supply, for a core area of 78 µm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121499335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902523
Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane
This paper presents a low jitter performance and low power consumption injection-locked clock multiplier (ILCM) for IoT application in 65-nm CMOS. A transformer-based ultra-low power (ULP) LC-VCO is proposed to minimize the overall power consumption. The introduced capacitor feedback path boosts the VCO loop gain and thus a robust startup can be obtained. The proposed transformer-based VCO achieves −115.1 dBc/Hz at 1 MHz frequency offset with a 97 μW power consumption, which corresponds to a -194 dBc/Hz VCO figure-of-merit (FoM). Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while consuming 210 μW power. A -269 dB FoMJP of jitter and power is achieved by this proposed ILCM, and a -262 dB FoMJRP is obtained while considering the 520 MHz input reference with multiplication factor equals to 5.
本文提出了一种低抖动性能和低功耗的注入锁定时钟乘法器(ILCM)，用于65纳米CMOS的物联网应用。提出了一种基于变压器的超低功耗(ULP) LC-VCO。引入的电容反馈路径提高了压控振荡器环路的增益，从而实现了稳健性启动。本文提出的基于变压器的VCO在1mhz频偏下实现了- 115.1 dBc/Hz，功耗为97 μW，对应于-194 dBc/Hz的VCO品质系数(FoM)。由于所提出的低功耗压控振荡器，总ILCM在消耗210 μW功率的同时实现了78 fs的RMS抖动。在考虑倍增因子为5的520 MHz输入基准时，该ILCM可实现抖动和功率的-269 dB fomjjp，并可获得-262 dB FoMJRP。
{"title":"A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO","authors":"Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang, Bangan Liu, Zheng Li, Jian Pang, T. Someya, A. Shirane","doi":"10.1109/ESSCIRC.2019.8902523","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902523","url":null,"abstract":"This paper presents a low jitter performance and low power consumption injection-locked clock multiplier (ILCM) for IoT application in 65-nm CMOS. A transformer-based ultra-low power (ULP) LC-VCO is proposed to minimize the overall power consumption. The introduced capacitor feedback path boosts the VCO loop gain and thus a robust startup can be obtained. The proposed transformer-based VCO achieves −115.1 dBc/Hz at 1 MHz frequency offset with a 97 μW power consumption, which corresponds to a -194 dBc/Hz VCO figure-of-merit (FoM). Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while consuming 210 μW power. A -269 dB FoMJP of jitter and power is achieved by this proposed ILCM, and a -262 dB FoMJRP is obtained while considering the 520 MHz input reference with multiplication factor equals to 5.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114514073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902927
R. Bagger, H. Sjöland
A Ka–band, 32–43 GHz, differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre–driver, driver and final stage, respectively. To enable use of 2.7 V supply, a cascode topology was employed in all three stages. The input is 80 Ω differential and the output load is 50 Ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB, including output losses of 2–2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front–end design, and its output thus faces an antenna interface with integrated LNA and TX/RX switches, and the input is connected to an on-chip variable gain amplifier.
{"title":"An 11 GHz–Bandwidth Variable Gain Ka–Band Power Amplifier for 5G Applications","authors":"R. Bagger, H. Sjöland","doi":"10.1109/ESSCIRC.2019.8902927","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902927","url":null,"abstract":"A Ka–band, 32–43 GHz, differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre–driver, driver and final stage, respectively. To enable use of 2.7 V supply, a cascode topology was employed in all three stages. The input is 80 Ω differential and the output load is 50 Ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB, including output losses of 2–2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front–end design, and its output thus faces an antenna interface with integrated LNA and TX/RX switches, and the input is connected to an on-chip variable gain amplifier.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902693
Francesco Mattioli Della Rocca, Hanning Mai, S. W. Hutchings, T. A. Abbas, A. Tsiamis, Peter Lomax, I. Gyöngy, N. Dutton, R. Henderson
A 128 x 128 SPAD motion detection-triggered time of flight (ToF) sensor is implemented in 40nm CMOS. The sensor combines vision and ToF ranging functions to only acquire depth frames when inter-frame intensity changes are detected. The 40µm x 20µm pixel integrates two 16-bit time-gated counters to acquire ToF histograms and repurposes them to compare two vision frames without requirement for additional out-of-pixel frame memory resources. An embedded ToF and vision processor performs on-chip vision frame comparison and binary frame output compression as well as controlling the time-resolved histogram sampling. The sensor achieves a maximum 20kfps in vision modality and 500fps in motion detection-triggered ToF over a measured 2.55m range with 1.6cm accuracy. The vision function reduces the sensor power consumption by 70% over continuous ToF operation and allows the sensor to gate the ToF laser emitter to reduce the system power when no motion activity is observed.
一个128 x 128 SPAD运动检测触发的飞行时间(ToF)传感器在40nm CMOS中实现。该传感器结合了视觉和ToF测距功能，仅在检测到帧间强度变化时获取深度帧。40 μ m x 20 μ m像素集成了两个16位时间门控计数器，以获取ToF直方图，并将其重新用于比较两个视觉帧，而无需额外的像素外帧内存资源。嵌入式ToF和视觉处理器执行片上视觉帧比较和二进制帧输出压缩以及控制时间分辨直方图采样。该传感器在视觉模式下达到最大20kfps，在运动检测触发的ToF中达到最大500fps，测量范围为2.55m，精度为1.6cm。视觉功能使传感器在连续ToF操作中功耗降低70%，并允许传感器对ToF激光发射器进行门控，以在没有观察到运动活动时降低系统功耗。
{"title":"A 128 × 128 SPAD Dynamic Vision-Triggered Time of Flight Imager","authors":"Francesco Mattioli Della Rocca, Hanning Mai, S. W. Hutchings, T. A. Abbas, A. Tsiamis, Peter Lomax, I. Gyöngy, N. Dutton, R. Henderson","doi":"10.1109/ESSCIRC.2019.8902693","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902693","url":null,"abstract":"A 128 x 128 SPAD motion detection-triggered time of flight (ToF) sensor is implemented in 40nm CMOS. The sensor combines vision and ToF ranging functions to only acquire depth frames when inter-frame intensity changes are detected. The 40µm x 20µm pixel integrates two 16-bit time-gated counters to acquire ToF histograms and repurposes them to compare two vision frames without requirement for additional out-of-pixel frame memory resources. An embedded ToF and vision processor performs on-chip vision frame comparison and binary frame output compression as well as controlling the time-resolved histogram sampling. The sensor achieves a maximum 20kfps in vision modality and 500fps in motion detection-triggered ToF over a measured 2.55m range with 1.6cm accuracy. The vision function reduces the sensor power consumption by 70% over continuous ToF operation and allows the sensor to gate the ToF laser emitter to reduce the system power when no motion activity is observed.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902823
Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta
The terahertz frequency range beyond 3 THz has exciting potential to have a transformative impact in a wide range of applications, including chemical and biomedical sensing, spectroscopy, imaging, and short-distance wireless communication. While there have been significant advancements in silicon-based THz imagers in the frequency ranges below 1 THz, technological development beyond 3 THz has been impeded by the lack of solid-state sources in this frequency range. In addition, the design space beyond 3 THz opens up fundamentally new challenges across electronics and the electromagnetic interface. In this spectral range, the wavelength is small enough (λox ≈ 50 μm at 3 THz) that a vertical via from the top antenna layer to the detector is a distributed element (transmission line or radiator). In this letter, we follow a careful circuits-electromagnetics co-design approach toward a hybrid imaging system with a 100-pixel CMOS imager that interfaces with a THz quantum cascade laser frequency comb that spans 3.25–3.5 THz with mode spacing of 17 GHz. The array chip, while designed for an optimal operation across 2.7–2.9 THz, demonstrates an average noise equivalent power (NEP) (across pixels) of $1260,{text{pW}}/sqrt {{text{Hz}}} $ between 3.25–3.5 THz and a projected NEP of $284,{text{pW}}/sqrt {{text{Hz}}} $ across the design range of 2.7–2.9 THz. To the best of our knowledge, we demonstrate for the first time full THz imaging in a hybrid quantum cascade laser (QCL)–CMOS fashion. This approach allows future works to leverage both QCL and CMOS technologies to demonstrate new technological advances for systems in the 1–10 THz range.
{"title":"A Hybrid THz Imaging System With a 100-Pixel CMOS Imager and a 3.25–3.50 THz Quantum Cascade Laser Frequency Comb","authors":"Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta","doi":"10.1109/ESSCIRC.2019.8902823","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902823","url":null,"abstract":"The terahertz frequency range beyond 3 THz has exciting potential to have a transformative impact in a wide range of applications, including chemical and biomedical sensing, spectroscopy, imaging, and short-distance wireless communication. While there have been significant advancements in silicon-based THz imagers in the frequency ranges below 1 THz, technological development beyond 3 THz has been impeded by the lack of solid-state sources in this frequency range. In addition, the design space beyond 3 THz opens up fundamentally new challenges across electronics and the electromagnetic interface. In this spectral range, the wavelength is small enough (λox ≈ 50 μm at 3 THz) that a vertical via from the top antenna layer to the detector is a distributed element (transmission line or radiator). In this letter, we follow a careful circuits-electromagnetics co-design approach toward a hybrid imaging system with a 100-pixel CMOS imager that interfaces with a THz quantum cascade laser frequency comb that spans 3.25–3.5 THz with mode spacing of 17 GHz. The array chip, while designed for an optimal operation across 2.7–2.9 THz, demonstrates an average noise equivalent power (NEP) (across pixels) of $1260,{text{pW}}/sqrt {{text{Hz}}} $ between 3.25–3.5 THz and a projected NEP of $284,{text{pW}}/sqrt {{text{Hz}}} $ across the design range of 2.7–2.9 THz. To the best of our knowledge, we demonstrate for the first time full THz imaging in a hybrid quantum cascade laser (QCL)–CMOS fashion. This approach allows future works to leverage both QCL and CMOS technologies to demonstrate new technological advances for systems in the 1–10 THz range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902908
Lorenzo Lotti, G. LaCaille, A. Niknejad
This letter presents a wideband injection-locked frequency tripler for mm-wave local oscillator generation. Conventional class-C injection is combined with class-D tail-switching, achieving significant extension of the locking range. Theoretical insights on the effectiveness of the proposed technique are provided. A 28-nm CMOS prototype achieves 57–74 GHz operation with 11-mW power consumption, without the need of tuning or calibration.
{"title":"A 57–74-GHz Tail-Switching Injection-Locked Frequency Tripler in 28-nm CMOS","authors":"Lorenzo Lotti, G. LaCaille, A. Niknejad","doi":"10.1109/ESSCIRC.2019.8902908","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902908","url":null,"abstract":"This letter presents a wideband injection-locked frequency tripler for mm-wave local oscillator generation. Conventional class-C injection is combined with class-D tail-switching, achieving significant extension of the locking range. Theoretical insights on the effectiveness of the proposed technique are provided. A 28-nm CMOS prototype achieves 57–74 GHz operation with 11-mW power consumption, without the need of tuning or calibration.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130856539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902764
A. Visweswaran, Bastien Vignon, Xin-yan Tang, S. Brebels, B. Debaillie, P. Wambacq
A two-way power-combining amplifier operating from 112-142GHz is presented. Integrated in Infineon’s 0.13μm SiGe-BiCMOS technology, it delivers 17dBm of peak saturated power to a 50Ω load at 13% PAE. Five fully-differential, transformer-coupled amplifier stages per path provide 34dB of forward transmission gain. Each 5-stage PA consists of capacitively gain-enhanced pre-drivers operated from 1.5V, followed by an inductively gain-enhanced cascoded driver powered by 3.3V. BJT models relevant at frequencies beyond 100GHz are evaluated to outline the trade-off between stability and gain exploited in this work. The design and layout of a folded, fully-differential, λ/4 power combiner is also presented, along with a full two-port characterization of the power-amplifier prototype.
{"title":"A 112-142GHz Power Amplifier with Regenerative Reactive Feedback achieving 17dBm peak Psat at 13% PAE","authors":"A. Visweswaran, Bastien Vignon, Xin-yan Tang, S. Brebels, B. Debaillie, P. Wambacq","doi":"10.1109/ESSCIRC.2019.8902764","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902764","url":null,"abstract":"A two-way power-combining amplifier operating from 112-142GHz is presented. Integrated in Infineon’s 0.13μm SiGe-BiCMOS technology, it delivers 17dBm of peak saturated power to a 50Ω load at 13% PAE. Five fully-differential, transformer-coupled amplifier stages per path provide 34dB of forward transmission gain. Each 5-stage PA consists of capacitively gain-enhanced pre-drivers operated from 1.5V, followed by an inductively gain-enhanced cascoded driver powered by 3.3V. BJT models relevant at frequencies beyond 100GHz are evaluated to outline the trade-off between stability and gain exploited in this work. The design and layout of a folded, fully-differential, λ/4 power combiner is also presented, along with a full two-port characterization of the power-amplifier prototype.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126185481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902864
Yury Antonov, M. Valkama, M. Kosunen, J. Ryynänen, M. Zahra, K. Stadius, Zahra Khonsari, Ilia Kempi, Toni Miilunpalo, Juha Inkinen, Vishnu Unnikrishnan, L. Anttila
This paper proposes a wideband 2-5GHz LO phase-shifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering direct-conversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm2.
{"title":"A Delay-Based LO Phase-Shifting Generator for a 2-5GHz Beamsteering Receiver in 28nm CMOS","authors":"Yury Antonov, M. Valkama, M. Kosunen, J. Ryynänen, M. Zahra, K. Stadius, Zahra Khonsari, Ilia Kempi, Toni Miilunpalo, Juha Inkinen, Vishnu Unnikrishnan, L. Anttila","doi":"10.1109/ESSCIRC.2019.8902864","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902864","url":null,"abstract":"This paper proposes a wideband 2-5GHz LO phase-shifting generator based on two digitally controlled delay lines. The concept is verified on a two-channel beamsteering direct-conversion receiver prototype implemented in 28nm CMOS. The novel generator provides both tunable phase-shifting and generation of I/Q components, achieving picosecond time resolution. The generator consumes 4.5-11.2mW and occupies 0.021mm2.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902913
F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber
This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.
{"title":"28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications","authors":"F. Arnaud, S. Haendler, S. Clerc, R. Ranica, A. Gandolfo, O. Weber","doi":"10.1109/ESSCIRC.2019.8902913","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902913","url":null,"abstract":"This paper proposes a general overview of Fully Depleted Silicon On Insulator (FDSOI) technology advantages leveraging body bias capability as a key enabler for digital, analog and memories performance enhancement. 2x total power contraction for digital designs has been demonstrating without any frequency degradation thanks to Forward Body Biasing (FBB), combined with 70% transistor variability reduction. Power of analog blocks has been strongly reduced with body bias technique while keeping trans-conductance efficiency increasing and output voltage gain. Finally, excellent memories performances has been achieved by applying FBB/RBB solution, dropping the leakage of unselected word-line in Phase Change Memory (PCM) array and improving Vmin operation for static RAM across a wide temperature range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121852766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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