Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902890
J. Walling
In this paper, power amplifiers in CMOS technologies are reviewed including traditional PAs and the digital power amplifier (DPA). DPAs embed the functionality of an up-conversion mixer and digital-to-analog converter (DAC) in the PA. Hence a more appropriate label for DPAs is RF-Power-DACs. The "Switched-Capacitor Power Amplifier" (SCPA) is highlighted due to its potential to transform future communications networks because of its small-size, high linearity, and high efficiency. Because the SCPA (and other DPAs) can directly interface with digital signals while outputting RF signals, it is a flexible mixed-signal interface circuit that does not require a large baseband filter. Several recent innovations in the SCPA that enable it to be reconfigured digitally across multiple frequency bands and to be used in beamforming/MIMO transceivers are highlighted.
本文综述了CMOS技术中的功率放大器，包括传统功率放大器和数字功率放大器。dpa在PA中嵌入了上转换混频器和数模转换器(DAC)的功能。因此，dpa更合适的标签是rf - power - dac。“开关电容功率放大器”(SCPA)因其体积小，线性度高，效率高，具有改变未来通信网络的潜力而备受关注。由于SCPA(和其他dpa)可以在输出RF信号的同时直接与数字信号接口，因此它是一种灵活的混合信号接口电路，不需要大型基带滤波器。SCPA最近的几项创新使其能够跨多个频带进行数字重新配置，并用于波束成形/MIMO收发器。
{"title":"The Switched-Capacitor Power Amplifier: A Key Enabler for Future Communications Systems","authors":"J. Walling","doi":"10.1109/ESSCIRC.2019.8902890","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902890","url":null,"abstract":"In this paper, power amplifiers in CMOS technologies are reviewed including traditional PAs and the digital power amplifier (DPA). DPAs embed the functionality of an up-conversion mixer and digital-to-analog converter (DAC) in the PA. Hence a more appropriate label for DPAs is RF-Power-DACs. The \"Switched-Capacitor Power Amplifier\" (SCPA) is highlighted due to its potential to transform future communications networks because of its small-size, high linearity, and high efficiency. Because the SCPA (and other DPAs) can directly interface with digital signals while outputting RF signals, it is a flexible mixed-signal interface circuit that does not require a large baseband filter. Several recent innovations in the SCPA that enable it to be reconfigured digitally across multiple frequency bands and to be used in beamforming/MIMO transceivers are highlighted.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902610
R. S. A. Kumar, N. Krishnapura
A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.
{"title":"A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter","authors":"R. S. A. Kumar, N. Krishnapura","doi":"10.1109/ESSCIRC.2019.8902610","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902610","url":null,"abstract":"A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902824
Hyunjoon Kim, Qian Chen, Taegeun Yoo, T. T. Kim, Bongjin Kim
This work proposes a digital in-memory computing macro with 1-16b reconfigurable weight and input bit-precisions for energy-efficient DNN processing. The proposed digital macro comprises 128×128 bitcells, and each bitcell consists of three building blocks for in-memory computing, an XNOR-based bitwise multiplier, a full-adder, and an SRAM cell. The two-dimensional bitcell array is then divided into parallel neurons, each with 128× column-shape multiply-and-accumulate (column-MAC) units arranged in a row. Each column-MAC with N-bit variable weight precision is built with ‘N+7’ bitcells in a column (i.e., 8-to-23 bitcells at 1-to-16bit). The N-bit weights are stored at SRAM cells for in-memory computing with the minimal memory access for fetching weights. The remaining 7 bitcells are needed to extend MSBs for accumulating partial-sums through 128 column-MACs. A bit-serial input is broadcasted to all bitcells in the same column, and parallel bitwise multiply operations are performed. Bitwise multiplied results from each column-MAC are then accumulated using N+7 full-adders which are vertically connected to work as a ripple carry adder. Meanwhile, the input precision is determined by the number of bit-serial input cycles from LSB to MSB. Hence, the post-accumulation is required for multi-bit input precision. A 65nm test-chip is fabricated, and the measured energy-efficiency is 117.3 to 2.06TOPS/W at 1-16bit.
{"title":"A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation","authors":"Hyunjoon Kim, Qian Chen, Taegeun Yoo, T. T. Kim, Bongjin Kim","doi":"10.1109/ESSCIRC.2019.8902824","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902824","url":null,"abstract":"This work proposes a digital in-memory computing macro with 1-16b reconfigurable weight and input bit-precisions for energy-efficient DNN processing. The proposed digital macro comprises 128×128 bitcells, and each bitcell consists of three building blocks for in-memory computing, an XNOR-based bitwise multiplier, a full-adder, and an SRAM cell. The two-dimensional bitcell array is then divided into parallel neurons, each with 128× column-shape multiply-and-accumulate (column-MAC) units arranged in a row. Each column-MAC with N-bit variable weight precision is built with ‘N+7’ bitcells in a column (i.e., 8-to-23 bitcells at 1-to-16bit). The N-bit weights are stored at SRAM cells for in-memory computing with the minimal memory access for fetching weights. The remaining 7 bitcells are needed to extend MSBs for accumulating partial-sums through 128 column-MACs. A bit-serial input is broadcasted to all bitcells in the same column, and parallel bitwise multiply operations are performed. Bitwise multiplied results from each column-MAC are then accumulated using N+7 full-adders which are vertically connected to work as a ripple carry adder. Meanwhile, the input precision is determined by the number of bit-serial input cycles from LSB to MSB. Hence, the post-accumulation is required for multi-bit input precision. A 65nm test-chip is fabricated, and the measured energy-efficiency is 117.3 to 2.06TOPS/W at 1-16bit.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127015192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A compact and energy-efficient hysteretic boost converter with an anti-phase AC-coupling emulate current control is presented. The scheme proposes a two-transistor current emulator and a comparator for both fast transient responses and tight closed-loop regulations. Fabricated in a 180 nm CMOS process, the converter regulates a 5 V output with 400 mA load capability from an input between 2.7 V and 4.5V. Measurement results show that the proposed scheme achieved superior transient responses and improved regulation performances. With load transitions between 0 mA and 300 mA, the converter shows over-/undershoot voltages of 38 mV and -42 mV, respectively. The measured load and line regulation performances are 5 mV/A and 2.3 mV/V, respectively.
{"title":"A 95.3% Peak Efficiency 38mV overshoot and 5mV/A load regulation Hysteretic Boost Converter with Anti-Phase Emulate Current Control","authors":"W. Qu, Donglie Gu, Haixiao Cao, Xu Yang, Jianxiong Xi, Lenian He, Shuo Dong","doi":"10.1109/ESSCIRC.2019.8902720","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902720","url":null,"abstract":"A compact and energy-efficient hysteretic boost converter with an anti-phase AC-coupling emulate current control is presented. The scheme proposes a two-transistor current emulator and a comparator for both fast transient responses and tight closed-loop regulations. Fabricated in a 180 nm CMOS process, the converter regulates a 5 V output with 400 mA load capability from an input between 2.7 V and 4.5V. Measurement results show that the proposed scheme achieved superior transient responses and improved regulation performances. With load transitions between 0 mA and 300 mA, the converter shows over-/undershoot voltages of 38 mV and -42 mV, respectively. The measured load and line regulation performances are 5 mV/A and 2.3 mV/V, respectively.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132241532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902616
Hao Ding, Xuqiang Zheng, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.
{"title":"A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS","authors":"Hao Ding, Xuqiang Zheng, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu","doi":"10.1109/ESSCIRC.2019.8902616","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902616","url":null,"abstract":"This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130797349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902754
B. Fletcher, T. Mak, Shidhartha Das
This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35um CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110um, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3× improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulse-code mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.
{"title":"A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration","authors":"B. Fletcher, T. Mak, Shidhartha Das","doi":"10.1109/ESSCIRC.2019.8902754","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902754","url":null,"abstract":"This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35um CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110um, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3× improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulse-code mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902859
Keun-Mok Kim, Eui-Rim Jeong, Kyung-Sik Choi, Subin Kim, Byeonghun Yun, Hyunki Jung, Wonkab Oh, J. Ko, Sang-Gug Lee
This paper presents an ultra-low power (ULP) high sensitivity binary frequency-shift keying (BFSK) direct conversion receiver (RX) for the internet of things (IoT). By employing a combination of a 2-stage ring voltage-controlled oscillator (VCO) and a 50 %-to-25 % duty conversion passive mixer, the power consumption is dramatically reduced. The prototype of the proposed RX which is implemented in a 55 nm CMOS technology shows −99 dBm sensitivity for 915 MHz 100 kbps BFSK signal while dissipating 499 µW from 0.9 V supply.
{"title":"A 915 MHz, 499 μW, –99 dBm, and 100 kbps BFSK Direct Conversion Receiver","authors":"Keun-Mok Kim, Eui-Rim Jeong, Kyung-Sik Choi, Subin Kim, Byeonghun Yun, Hyunki Jung, Wonkab Oh, J. Ko, Sang-Gug Lee","doi":"10.1109/ESSCIRC.2019.8902859","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902859","url":null,"abstract":"This paper presents an ultra-low power (ULP) high sensitivity binary frequency-shift keying (BFSK) direct conversion receiver (RX) for the internet of things (IoT). By employing a combination of a 2-stage ring voltage-controlled oscillator (VCO) and a 50 %-to-25 % duty conversion passive mixer, the power consumption is dramatically reduced. The prototype of the proposed RX which is implemented in a 55 nm CMOS technology shows −99 dBm sensitivity for 915 MHz 100 kbps BFSK signal while dissipating 499 µW from 0.9 V supply.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124683985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902924
P. Meinerzhagen, S. Kundu, Andres F. Malavasi, Trang Nguyen, M. Khellah, J. Tschanz, V. De
Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.
{"title":"Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS","authors":"P. Meinerzhagen, S. Kundu, Andres F. Malavasi, Trang Nguyen, M. Khellah, J. Tschanz, V. De","doi":"10.1109/ESSCIRC.2019.8902924","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902924","url":null,"abstract":"Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122699834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902534
S. Bang, M. Cho, P. Meinerzhagen, Andres F. Malavasi, M. Khellah, J. Tschanz, V. De
Distributed charge injection (CI) scheme featuring distributed VMAX-complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in 10-nm FinFET CMOS test-chip. A local DDD detects nearby voltage droop in two clock cycles of IP block, and quickly triggers associated CI clamps to inject charge from a high voltage rail (e.g., 1.8 V) to VCC for immediate voltage droop mitigation. Local droop controller collectively guarantees stable operation after CI is triggered, by gradually allowing the voltage regulator to take over after the droop subsides. Measured data shows droop reduction by up to 45% for a uniform transient load current transition, and by 38% in a hot-spot load current transition at 1.0 V and 2.0 GHz. The droop reduction is translated to power savings of ∼11% over a guard-banded baseline.
{"title":"An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop","authors":"S. Bang, M. Cho, P. Meinerzhagen, Andres F. Malavasi, M. Khellah, J. Tschanz, V. De","doi":"10.1109/ESSCIRC.2019.8902534","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902534","url":null,"abstract":"Distributed charge injection (CI) scheme featuring distributed VMAX-complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in 10-nm FinFET CMOS test-chip. A local DDD detects nearby voltage droop in two clock cycles of IP block, and quickly triggers associated CI clamps to inject charge from a high voltage rail (e.g., 1.8 V) to VCC for immediate voltage droop mitigation. Local droop controller collectively guarantees stable operation after CI is triggered, by gradually allowing the voltage regulator to take over after the droop subsides. Measured data shows droop reduction by up to 45% for a uniform transient load current transition, and by 38% in a hot-spot load current transition at 1.0 V and 2.0 GHz. The droop reduction is translated to power savings of ∼11% over a guard-banded baseline.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116411680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902684
Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, E. Alon
This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm2, and consumes 0.72-0.62 pJ/bit.
{"title":"A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit","authors":"Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, E. Alon","doi":"10.1109/ESSCIRC.2019.8902684","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902684","url":null,"abstract":"This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm2, and consumes 0.72-0.62 pJ/bit.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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