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ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)最新文献

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The Switched-Capacitor Power Amplifier: A Key Enabler for Future Communications Systems 开关电容功率放大器:未来通信系统的关键推动者
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902890
J. Walling
In this paper, power amplifiers in CMOS technologies are reviewed including traditional PAs and the digital power amplifier (DPA). DPAs embed the functionality of an up-conversion mixer and digital-to-analog converter (DAC) in the PA. Hence a more appropriate label for DPAs is RF-Power-DACs. The "Switched-Capacitor Power Amplifier" (SCPA) is highlighted due to its potential to transform future communications networks because of its small-size, high linearity, and high efficiency. Because the SCPA (and other DPAs) can directly interface with digital signals while outputting RF signals, it is a flexible mixed-signal interface circuit that does not require a large baseband filter. Several recent innovations in the SCPA that enable it to be reconfigured digitally across multiple frequency bands and to be used in beamforming/MIMO transceivers are highlighted.
本文综述了CMOS技术中的功率放大器,包括传统功率放大器和数字功率放大器。dpa在PA中嵌入了上转换混频器和数模转换器(DAC)的功能。因此,dpa更合适的标签是rf - power - dac。“开关电容功率放大器”(SCPA)因其体积小,线性度高,效率高,具有改变未来通信网络的潜力而备受关注。由于SCPA(和其他dpa)可以在输出RF信号的同时直接与数字信号接口,因此它是一种灵活的混合信号接口电路,不需要大型基带滤波器。SCPA最近的几项创新使其能够跨多个频带进行数字重新配置,并用于波束成形/MIMO收发器。
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引用次数: 5
A 2-Channel ADC Using a Delta-Sigma Modulator Without Reset & a Modulated-Sinc-Sum Filter 采用无复位Delta-Sigma调制器和调制自和滤波器的2通道ADC
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902610
R. S. A. Kumar, N. Krishnapura
A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.
提出了一种只需修改数字滤波器即可将任意连续运行的离散δ - σ调制器转换为多通道ADC的新方法。两个输入通道复用并馈送到调制器。如果抽取滤波器的输出直接解复用,那么将存在的串扰将使用以下采样率工作的调制自和数字滤波器来消除。该技术避免了增量式adc所需的复位,以及先前提出的无复位多通道转换技术所需的输入采样保持。在180nm CMOS工艺中演示了时钟频率为6.144 MHz、每通道带宽为22 kHz的双通道ADC原型。包括数字滤波器在内,它每通道消耗1.53 mW,峰值信噪比/DR为94.4 dB/98.5 dB,同时将通道间串扰限制在- 94 dBc以下。
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引用次数: 1
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation 具有列mac结构和位串行计算的1-16b精度可重构数字内存计算宏
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902824
Hyunjoon Kim, Qian Chen, Taegeun Yoo, T. T. Kim, Bongjin Kim
This work proposes a digital in-memory computing macro with 1-16b reconfigurable weight and input bit-precisions for energy-efficient DNN processing. The proposed digital macro comprises 128×128 bitcells, and each bitcell consists of three building blocks for in-memory computing, an XNOR-based bitwise multiplier, a full-adder, and an SRAM cell. The two-dimensional bitcell array is then divided into parallel neurons, each with 128× column-shape multiply-and-accumulate (column-MAC) units arranged in a row. Each column-MAC with N-bit variable weight precision is built with ‘N+7’ bitcells in a column (i.e., 8-to-23 bitcells at 1-to-16bit). The N-bit weights are stored at SRAM cells for in-memory computing with the minimal memory access for fetching weights. The remaining 7 bitcells are needed to extend MSBs for accumulating partial-sums through 128 column-MACs. A bit-serial input is broadcasted to all bitcells in the same column, and parallel bitwise multiply operations are performed. Bitwise multiplied results from each column-MAC are then accumulated using N+7 full-adders which are vertically connected to work as a ripple carry adder. Meanwhile, the input precision is determined by the number of bit-serial input cycles from LSB to MSB. Hence, the post-accumulation is required for multi-bit input precision. A 65nm test-chip is fabricated, and the measured energy-efficiency is 117.3 to 2.06TOPS/W at 1-16bit.
这项工作提出了一个具有1-16b可重构权重和输入位精度的数字内存计算宏,用于节能深度神经网络处理。所提出的数字宏包括128×128位单元,每个位单元由三个用于内存计算的构建块、一个基于xnor的位乘法器、一个全加法器和一个SRAM单元组成。然后将二维位单元数组划分为并行神经元,每个神经元具有排成一行的128×柱状乘法和累加(column-MAC)单元。每个具有N位可变权重精度的列mac都在列中使用“N+7”位元(即1- 16位的8- 23位元)构建。n位权重存储在SRAM单元中,用于内存计算,获取权重的内存访问最少。剩余的7位单元格用于扩展msb,以便通过128列mac累积部分和。将位串行输入广播到同一列中的所有位单元格,并执行并行的按位相乘操作。每个列mac的按位相乘结果然后使用N+7个全加法器累积,这些加法器垂直连接以作为纹波进位加法器。同时,输入精度由LSB到MSB的位串行输入周期数决定。因此,需要多比特输入精度的后累加。制作了65nm测试芯片,测得1-16bit时的能量效率为117.3 ~ 2.06TOPS/W。
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引用次数: 32
A 95.3% Peak Efficiency 38mV overshoot and 5mV/A load regulation Hysteretic Boost Converter with Anti-Phase Emulate Current Control 具有反相位仿真电流控制的38mV超调和5mV/A负载调节滞回升压变换器,峰值效率95.3%
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902720
W. Qu, Donglie Gu, Haixiao Cao, Xu Yang, Jianxiong Xi, Lenian He, Shuo Dong
A compact and energy-efficient hysteretic boost converter with an anti-phase AC-coupling emulate current control is presented. The scheme proposes a two-transistor current emulator and a comparator for both fast transient responses and tight closed-loop regulations. Fabricated in a 180 nm CMOS process, the converter regulates a 5 V output with 400 mA load capability from an input between 2.7 V and 4.5V. Measurement results show that the proposed scheme achieved superior transient responses and improved regulation performances. With load transitions between 0 mA and 300 mA, the converter shows over-/undershoot voltages of 38 mV and -42 mV, respectively. The measured load and line regulation performances are 5 mV/A and 2.3 mV/V, respectively.
提出了一种具有反相位交流耦合仿真电流控制的紧凑型节能滞回升压变换器。该方案提出了一个双晶体管电流仿真器和一个比较器,用于快速瞬态响应和严密闭环调节。该转换器采用180nm CMOS工艺制造,从2.7 V到4.5V的输入调节5v输出和400ma负载能力。实测结果表明,该方案具有较好的暂态响应性能和较好的调节性能。当负载在0 mA和300 mA之间转换时,转换器分别显示38 mV和-42 mV的过冲/欠冲电压。实测负载和线路调节性能分别为5 mV/A和2.3 mV/V。
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引用次数: 0
A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS 一个112gb /s的PAM-4发射机,带有65纳米CMOS的2抽头分数间隔FFE
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902616
Hao Ding, Xuqiang Zheng, Danyu Wu, Lei Zhou, Jin Wu, Fangxu Lv, Jianye Wang, Xinyu Liu
This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.
本文介绍了一种采用65纳米CMOS工艺实现的具有2分导分数间隔前馈均衡器(FFE)的112 gb /s四电平脉冲幅度调制(PAM-4)发射器。分接延迟由位于时钟路径中的基于粗-细电容阵列的延迟单元来调节。采用动态锁存器、伪and2s和带宽增强的4:1 mux来保证足够的时间裕度和112 gb /s设计的足够带宽。测量结果表明,分数间距FFE能显著优化睁眼效果。所制备的PAM-4发射机最大数据速率为112 Gb/s,能量效率为2.17 pJ/bit。
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引用次数: 0
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop 一种全数字、符合vmax的稳定分布式电荷注入方案,用于快速缓解电压下降
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902534
S. Bang, M. Cho, P. Meinerzhagen, Andres F. Malavasi, M. Khellah, J. Tschanz, V. De
Distributed charge injection (CI) scheme featuring distributed VMAX-complaint CI clamps, distributed digital droop detectors (DDDs), and distributed droop controllers for fast mitigation of voltage droop is fabricated in 10-nm FinFET CMOS test-chip. A local DDD detects nearby voltage droop in two clock cycles of IP block, and quickly triggers associated CI clamps to inject charge from a high voltage rail (e.g., 1.8 V) to VCC for immediate voltage droop mitigation. Local droop controller collectively guarantees stable operation after CI is triggered, by gradually allowing the voltage regulator to take over after the droop subsides. Measured data shows droop reduction by up to 45% for a uniform transient load current transition, and by 38% in a hot-spot load current transition at 1.0 V and 2.0 GHz. The droop reduction is translated to power savings of ∼11% over a guard-banded baseline.
在10nm FinFET CMOS测试芯片上制备了分布式电荷注入(CI)方案,该方案具有分布式vmax -投诉CI钳,分布式数字下垂检测器(DDDs)和分布式下垂控制器,用于快速缓解电压下垂。本地DDD在IP块的两个时钟周期内检测到附近的电压下降,并快速触发相关的CI钳,从高压轨(例如1.8 V)向VCC注入电荷,以立即缓解电压下降。局部下垂控制器通过在下垂消退后逐渐让稳压器接管,共同保证CI触发后的稳定运行。测量数据显示,均匀瞬态负载电流转换可降低高达45%的下垂,在1.0 V和2.0 GHz的热点负载电流转换可降低38%。与保护带基线相比,下垂减少可转化为功率节省约11%。
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引用次数: 2
A 0.06–3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers 一种用于物联网接收机的0.06 - 3.4 mhz 92 μ w极锐过渡带模拟FIR通道选择滤波器
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902851
Bart J. Thijssen, E. Klumperink, P. Quinlan, B. Nauta
Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a digital-to-analog converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22-nm FDSOI and has a core area of 0.09 mm2. It consumes 92 µW from a 700-mV supply and achieves f−60 dB/f−3 dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.
为了提高超低功耗物联网接收机单级gm-C通道选择滤波器的性能,提出了模拟FIR滤波。该变换器实现为数模转换器;允许随时间变化的跨导,从而产生非常锐利的FIR滤波器。该滤波器采用22nm FDSOI制造,核心面积为0.09 mm2。它从700mv电源消耗92µW,达到f−60db /f−3db = 3.8。该滤波器增益为31.5 dB,带外OIP3为28 dBm,输出参考1-dB压缩点为3.7 dBm。滤波器带宽从0.06到3.4 MHz可调。
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引用次数: 5
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS 10nm CMOS中触发器和脉冲锁存器的最小延迟余量/误差检测与校正
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902924
P. Meinerzhagen, S. Kundu, Andres F. Malavasi, Trang Nguyen, M. Khellah, J. Tschanz, V. De
Min-delay (MID) error rates increase dramatically under aggressive voltage and technology scaling, limiting VMIN. Pulsed latches offer significant clocking power savings over flip-flops but further aggravate MID failures. This letter proposes MID margin/error detection and correction (M2/EDAC) for flip-flops and pulsed latches to reduce VMIN guard bands for voltage noise, temperature variation, and aging, and to detect and correct rare MID failures. Statistical data collection from a prototype in 10-nm tri-gate CMOS shows up to 122-mV VMIN reduction. Reliable pulsed latches enabled by M2/EDAC offer 12%–18% total dynamic power savings for logic blocks in 10-nm CMOS.
在高电压和技术缩放下,最小延迟(MID)错误率急剧增加,限制了VMIN。脉冲锁存器比触发器提供了显著的时钟功耗节省,但进一步加剧了MID故障。本函提出用于触发器和脉冲锁存器的MID余量/误差检测和校正(M2/EDAC),以减少电压噪声,温度变化和老化的VMIN保护带,并检测和纠正罕见的MID故障。从10纳米三栅极CMOS原型收集的统计数据显示,VMIN降低高达122 mv。由M2/EDAC实现的可靠脉冲锁存器可为10nm CMOS中的逻辑模块提供12%-18%的总动态功耗节省。
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引用次数: 0
A 915 MHz, 499 μW, –99 dBm, and 100 kbps BFSK Direct Conversion Receiver 一个915mhz, 499 μW, - 99dbm, 100kbps的BFSK直接转换接收机
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902859
Keun-Mok Kim, Eui-Rim Jeong, Kyung-Sik Choi, Subin Kim, Byeonghun Yun, Hyunki Jung, Wonkab Oh, J. Ko, Sang-Gug Lee
This paper presents an ultra-low power (ULP) high sensitivity binary frequency-shift keying (BFSK) direct conversion receiver (RX) for the internet of things (IoT). By employing a combination of a 2-stage ring voltage-controlled oscillator (VCO) and a 50 %-to-25 % duty conversion passive mixer, the power consumption is dramatically reduced. The prototype of the proposed RX which is implemented in a 55 nm CMOS technology shows −99 dBm sensitivity for 915 MHz 100 kbps BFSK signal while dissipating 499 µW from 0.9 V supply.
介绍了一种用于物联网(IoT)的超低功耗(ULP)高灵敏度二进制移频键控(BFSK)直接转换接收机(RX)。通过采用两级环压控振荡器(VCO)和50%至25%的负载转换无源混频器的组合,功耗显着降低。采用55 nm CMOS技术实现的RX原型在0.9 V电源功耗499 μ W的情况下,对915 MHz 100 kbps BFSK信号的灵敏度为- 99 dBm。
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引用次数: 3
A 185 μW −105.1 dB THD 88.6 dB SNDR Negative-R Stabilized Audio Preamplifier 一种185 μW−105.1 dB THD 88.6 dB SNDR负r稳定音频前置放大器
Pub Date : 2019-09-01 DOI: 10.1109/ESSCIRC.2019.8902846
Seungwoo Song, Changuk Lee, Moonhyung Jang, Youngcheol Chae
This paper presents a low-power preamplifier for high fidelity audio codecs. It attains high linearity at low power by using a negative-R stabilized amplifier architecture that employs a negative-R assisted amplifier in a low-frequency path to cancel the non-idealities of a main amplifier. This shows the in-band noise attenuation of amplifiers and the drastic improvement of the linearity. Fabricated in a 65-nm CMOS process, the preamplifier achieves −105.1 dB THD, 88.6 dB SNDR, and 89.3 dB DR with 20 dB gain in 20 kHz bandwidth, while consuming only 185 μW from a 1.2 V supply. This results in the highest energy-efficiency FoMSNDR of 168.9 dB among audio preamplifiers.
提出了一种用于高保真音频编解码器的低功耗前置放大器。它采用负r稳定放大器架构,在低频路径上采用负r辅助放大器,以消除主放大器的非理想性,从而在低功率下实现高线性度。这显示了放大器的带内噪声衰减和线性度的急剧改善。该前置放大器采用65纳米CMOS工艺,在20 kHz带宽下实现- 105.1 dB THD、88.6 dB SNDR和89.3 dB DR,增益为20 dB,功耗仅为185 μW。这导致了在音频前置放大器中168.9 dB的最高能量效率的FoMSNDR。
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引用次数: 5
期刊
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)
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