Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902851
Bart J. Thijssen, E. Klumperink, P. Quinlan, B. Nauta
Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a digital-to-analog converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22-nm FDSOI and has a core area of 0.09 mm2. It consumes 92 µW from a 700-mV supply and achieves f−60 dB/f−3 dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.
{"title":"A 0.06–3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers","authors":"Bart J. Thijssen, E. Klumperink, P. Quinlan, B. Nauta","doi":"10.1109/ESSCIRC.2019.8902851","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902851","url":null,"abstract":"Analog FIR filtering is proposed to improve the performance of a single stage gm-C channel selection filter for ultra low power Internet-of-Things receivers. The transconductor is implemented as a digital-to-analog converter; allowing a varying transconductance in time, which results in a very sharp FIR filter. The filter is manufactured in 22-nm FDSOI and has a core area of 0.09 mm2. It consumes 92 µW from a 700-mV supply and achieves f−60 dB/f−3 dB = 3.8. The filter has 31.5 dB gain, out-of-band OIP3 of 28 dBm and output referred 1-dB compression point of 3.7 dBm. The filter bandwidth is tunable from 0.06 to 3.4 MHz.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"56 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121015526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902733
Sachin Taneja, M. Alioto
This work introduces a Physically Unclonable Function (PUF) based key generation scheme with run-time in-situ instability detection and process/voltage/temperature (PVT) sensors. Such sensors are fused to evaluate the sufficient number of correction bits NECC required by Error Correcting Code (ECC) to make the PUF output stable, and meet a given key error rate target. Run-time sensing overcomes the substantial ECC energy penalty associated with the traditional design-time margin of NECC for worst-case word, die, voltage and temperature. ECC with tunable NECC is introduced to enable energy saving in typical cases where NECC is lower than its worst-case value. Sensor fusion via simple linear regression estimates the required NECC at run-time.A testchip in 40 nm demonstrates the concept, based on a static monostable current mirror PUF with NECC = 0…4. Average energy reduction by 1.8X is shown compared to a traditional margined design, at an area overhead of less than 20%. As additional benefit of adjustable NECC, such energy savings can be further expanded under applications having less stringent stability requirements.
{"title":"PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion","authors":"Sachin Taneja, M. Alioto","doi":"10.1109/ESSCIRC.2019.8902733","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902733","url":null,"abstract":"This work introduces a Physically Unclonable Function (PUF) based key generation scheme with run-time in-situ instability detection and process/voltage/temperature (PVT) sensors. Such sensors are fused to evaluate the sufficient number of correction bits NECC required by Error Correcting Code (ECC) to make the PUF output stable, and meet a given key error rate target. Run-time sensing overcomes the substantial ECC energy penalty associated with the traditional design-time margin of NECC for worst-case word, die, voltage and temperature. ECC with tunable NECC is introduced to enable energy saving in typical cases where NECC is lower than its worst-case value. Sensor fusion via simple linear regression estimates the required NECC at run-time.A testchip in 40 nm demonstrates the concept, based on a static monostable current mirror PUF with NECC = 0…4. Average energy reduction by 1.8X is shown compared to a traditional margined design, at an area overhead of less than 20%. As additional benefit of adjustable NECC, such energy savings can be further expanded under applications having less stringent stability requirements.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902918
Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe
A highly versatile all-dynamic sensor interface is proposed. It supports temperature/capacitance/resistance sensing with (a) adaptive power vs speed and resolution, (b) a configurable signal range, and (c) the ability for time-interleaved multimodal recording. State-of-the-art Figure-of-Merits (FoMs) are achieved of 0.82pJ•C2, 31fJ/c.-step, and 124fJ/c.-step, for temperature, capacitance and resistance sensing, respectively, with a minimum power consumption of 0.34nW and a chip area of 0.084mm2 in 65nm CMOS. Multimodal sensing is demonstrated in real time, showing that this chip can measure temperature, acceleration (with a capacitive sensor) and pH (with a resistive sensor) together with only 1.4nW of power consumption.
{"title":"A 0.34-571nW All-Dynamic Versatile Sensor Interface for Temperature, Capacitance, and Resistance Sensing","authors":"Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe","doi":"10.1109/ESSCIRC.2019.8902918","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902918","url":null,"abstract":"A highly versatile all-dynamic sensor interface is proposed. It supports temperature/capacitance/resistance sensing with (a) adaptive power vs speed and resolution, (b) a configurable signal range, and (c) the ability for time-interleaved multimodal recording. State-of-the-art Figure-of-Merits (FoMs) are achieved of 0.82pJ•C2, 31fJ/c.-step, and 124fJ/c.-step, for temperature, capacitance and resistance sensing, respectively, with a minimum power consumption of 0.34nW and a chip area of 0.084mm2 in 65nm CMOS. Multimodal sensing is demonstrated in real time, showing that this chip can measure temperature, acceleration (with a capacitive sensor) and pH (with a resistive sensor) together with only 1.4nW of power consumption.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125883408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902785
M. Auer, Timuçin Karaca
A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.
{"title":"A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop","authors":"M. Auer, Timuçin Karaca","doi":"10.1109/ESSCIRC.2019.8902785","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902785","url":null,"abstract":"A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902885
Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina
This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.
{"title":"A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip","authors":"Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina","doi":"10.1109/ESSCIRC.2019.8902885","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902885","url":null,"abstract":"This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low-power preamplifier for high fidelity audio codecs. It attains high linearity at low power by using a negative-R stabilized amplifier architecture that employs a negative-R assisted amplifier in a low-frequency path to cancel the non-idealities of a main amplifier. This shows the in-band noise attenuation of amplifiers and the drastic improvement of the linearity. Fabricated in a 65-nm CMOS process, the preamplifier achieves −105.1 dB THD, 88.6 dB SNDR, and 89.3 dB DR with 20 dB gain in 20 kHz bandwidth, while consuming only 185 μW from a 1.2 V supply. This results in the highest energy-efficiency FoMSNDR of 168.9 dB among audio preamplifiers.
提出了一种用于高保真音频编解码器的低功耗前置放大器。它采用负r稳定放大器架构，在低频路径上采用负r辅助放大器，以消除主放大器的非理想性，从而在低功率下实现高线性度。这显示了放大器的带内噪声衰减和线性度的急剧改善。该前置放大器采用65纳米CMOS工艺，在20 kHz带宽下实现- 105.1 dB THD、88.6 dB SNDR和89.3 dB DR，增益为20 dB，功耗仅为185 μW。这导致了在音频前置放大器中168.9 dB的最高能量效率的FoMSNDR。
{"title":"A 185 μW −105.1 dB THD 88.6 dB SNDR Negative-R Stabilized Audio Preamplifier","authors":"Seungwoo Song, Changuk Lee, Moonhyung Jang, Youngcheol Chae","doi":"10.1109/ESSCIRC.2019.8902846","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902846","url":null,"abstract":"This paper presents a low-power preamplifier for high fidelity audio codecs. It attains high linearity at low power by using a negative-R stabilized amplifier architecture that employs a negative-R assisted amplifier in a low-frequency path to cancel the non-idealities of a main amplifier. This shows the in-band noise attenuation of amplifiers and the drastic improvement of the linearity. Fabricated in a 65-nm CMOS process, the preamplifier achieves −105.1 dB THD, 88.6 dB SNDR, and 89.3 dB DR with 20 dB gain in 20 kHz bandwidth, while consuming only 185 μW from a 1.2 V supply. This results in the highest energy-efficiency FoMSNDR of 168.9 dB among audio preamplifiers.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127391660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902680
Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee
A differential NAND-structured physically unclonable function (PUF) with 20F2 area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (Vth) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to Vth variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.
{"title":"A 20F2 Area-Efficient Differential nand-Structured Physically Unclonable Function for Low-Cost IoT Security","authors":"Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee","doi":"10.1109/ESSCIRC.2019.8902680","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902680","url":null,"abstract":"A differential NAND-structured physically unclonable function (PUF) with 20F2 area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (Vth) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to Vth variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902656
M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra
This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.
{"title":"2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications","authors":"M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra","doi":"10.1109/ESSCIRC.2019.8902656","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902656","url":null,"abstract":"This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129410445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902921
Gönenç Berkol, P. Baltus, P. Harpe, E. Cantatore
This paper presents the design and experimental characterization of an ultrasound transceiver. The transceiver includes an on-chip transmitter and a receiver to be used in a symmetric data-link, where each sensor node has limited energy resources and is operated in air or a fluidic environment. The receiver and the transmitter operate from a 0.8V supply and consume 1.18µW and 50µW, respectively, while exchanging data at 1kbps data-rate. The receiver sensitivity is −81.6dBm at a 10°3 Bit Error Rate (BER) level, which enables an experimentally verified transmission over 3.2m in air and a predicted transmission distance in water in the order of 2km, with a measured energy per bit performance of 51.18 nJ/b.
{"title":"A −81.6dBm Sensitivity Ultrasound Transceiver in 65nm CMOS for Symmetrical Data-Links","authors":"Gönenç Berkol, P. Baltus, P. Harpe, E. Cantatore","doi":"10.1109/ESSCIRC.2019.8902921","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902921","url":null,"abstract":"This paper presents the design and experimental characterization of an ultrasound transceiver. The transceiver includes an on-chip transmitter and a receiver to be used in a symmetric data-link, where each sensor node has limited energy resources and is operated in air or a fluidic environment. The receiver and the transmitter operate from a 0.8V supply and consume 1.18µW and 50µW, respectively, while exchanging data at 1kbps data-rate. The receiver sensitivity is −81.6dBm at a 10°3 Bit Error Rate (BER) level, which enables an experimentally verified transmission over 3.2m in air and a predicted transmission distance in water in the order of 2km, with a measured energy per bit performance of 51.18 nJ/b.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128744285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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