Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902918
Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe
A highly versatile all-dynamic sensor interface is proposed. It supports temperature/capacitance/resistance sensing with (a) adaptive power vs speed and resolution, (b) a configurable signal range, and (c) the ability for time-interleaved multimodal recording. State-of-the-art Figure-of-Merits (FoMs) are achieved of 0.82pJ•C2, 31fJ/c.-step, and 124fJ/c.-step, for temperature, capacitance and resistance sensing, respectively, with a minimum power consumption of 0.34nW and a chip area of 0.084mm2 in 65nm CMOS. Multimodal sensing is demonstrated in real time, showing that this chip can measure temperature, acceleration (with a capacitive sensor) and pH (with a resistive sensor) together with only 1.4nW of power consumption.
{"title":"A 0.34-571nW All-Dynamic Versatile Sensor Interface for Temperature, Capacitance, and Resistance Sensing","authors":"Haoming Xin, M. Andraud, P. Baltus, E. Cantatore, P. Harpe","doi":"10.1109/ESSCIRC.2019.8902918","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902918","url":null,"abstract":"A highly versatile all-dynamic sensor interface is proposed. It supports temperature/capacitance/resistance sensing with (a) adaptive power vs speed and resolution, (b) a configurable signal range, and (c) the ability for time-interleaved multimodal recording. State-of-the-art Figure-of-Merits (FoMs) are achieved of 0.82pJ•C2, 31fJ/c.-step, and 124fJ/c.-step, for temperature, capacitance and resistance sensing, respectively, with a minimum power consumption of 0.34nW and a chip area of 0.084mm2 in 65nm CMOS. Multimodal sensing is demonstrated in real time, showing that this chip can measure temperature, acceleration (with a capacitive sensor) and pH (with a resistive sensor) together with only 1.4nW of power consumption.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125883408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902754
B. Fletcher, T. Mak, Shidhartha Das
This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35um CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110um, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3× improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulse-code mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.
{"title":"A 10.8pJ/bit Pulse-Position Inductive Transceiver for Low-Energy Wireless 3D Integration","authors":"B. Fletcher, T. Mak, Shidhartha Das","doi":"10.1109/ESSCIRC.2019.8902754","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902754","url":null,"abstract":"This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35um CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110um, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3× improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulse-code mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902733
Sachin Taneja, M. Alioto
This work introduces a Physically Unclonable Function (PUF) based key generation scheme with run-time in-situ instability detection and process/voltage/temperature (PVT) sensors. Such sensors are fused to evaluate the sufficient number of correction bits NECC required by Error Correcting Code (ECC) to make the PUF output stable, and meet a given key error rate target. Run-time sensing overcomes the substantial ECC energy penalty associated with the traditional design-time margin of NECC for worst-case word, die, voltage and temperature. ECC with tunable NECC is introduced to enable energy saving in typical cases where NECC is lower than its worst-case value. Sensor fusion via simple linear regression estimates the required NECC at run-time.A testchip in 40 nm demonstrates the concept, based on a static monostable current mirror PUF with NECC = 0…4. Average energy reduction by 1.8X is shown compared to a traditional margined design, at an area overhead of less than 20%. As additional benefit of adjustable NECC, such energy savings can be further expanded under applications having less stringent stability requirements.
{"title":"PUF-based Key Generation with Design Margin Reduction via In-Situ and PVT Sensor Fusion","authors":"Sachin Taneja, M. Alioto","doi":"10.1109/ESSCIRC.2019.8902733","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902733","url":null,"abstract":"This work introduces a Physically Unclonable Function (PUF) based key generation scheme with run-time in-situ instability detection and process/voltage/temperature (PVT) sensors. Such sensors are fused to evaluate the sufficient number of correction bits NECC required by Error Correcting Code (ECC) to make the PUF output stable, and meet a given key error rate target. Run-time sensing overcomes the substantial ECC energy penalty associated with the traditional design-time margin of NECC for worst-case word, die, voltage and temperature. ECC with tunable NECC is introduced to enable energy saving in typical cases where NECC is lower than its worst-case value. Sensor fusion via simple linear regression estimates the required NECC at run-time.A testchip in 40 nm demonstrates the concept, based on a static monostable current mirror PUF with NECC = 0…4. Average energy reduction by 1.8X is shown compared to a traditional margined design, at an area overhead of less than 20%. As additional benefit of adjustable NECC, such energy savings can be further expanded under applications having less stringent stability requirements.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121889640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902885
Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina
This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.
{"title":"A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip","authors":"Imran Bashir, K. Pomorski, R. Staszewski, Mike Asker, Ç. Çetintepe, Dirk R. Leipold, A. Esmailiyan, Hongyin Wang, T. Siriburanon, P. Giounanlis, E. Blokhina","doi":"10.1109/ESSCIRC.2019.8902885","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902885","url":null,"abstract":"This paper discloses a mixed-signal control unit of a fully integrated semiconductor quantum processor SoC realized in a 22nm FD-SOI technology. Independent high-resolution DACs that set the amplitude and pulse-width of the control signals were integrated for each qubit, enabling both a programmable semiconductor qubit operation and a per-qubit individual calibration that compensates for the process variability. The lower deco-herence time of the semiconductor charge-qubits as compared to their spin-qubit counterparts was mitigated by using a high frequency of control unit operation. This is facilitated by the co-integration on the same die of the semiconductor quantum structures together with their corresponding classic control circuitry. The main challenge of achieving deep cryogenic operation for the mixed-signal classic control circuit was surpassed by using programmable local heating DACs that slightly boost the local temperature of the control blocks above the average temperature of the die, which needs to be maintained around 4 K to enable a reliable quantum operation. A staged multi-phase operation was adopted for the digital core in order to minimize the quantum decoherence originated in digital noise injection. The high-frequency clock tree and divider allows the generation of sub-20 ps fast edge control pulses with programmable widths down to 166 ps. This offers a wide quantum computation window when compared with the 1µs decoherence time of the charge-qubit structures.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902785
M. Auer, Timuçin Karaca
A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.
{"title":"A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop","authors":"M. Auer, Timuçin Karaca","doi":"10.1109/ESSCIRC.2019.8902785","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902785","url":null,"abstract":"A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126540327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902684
Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, E. Alon
This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm2, and consumes 0.72-0.62 pJ/bit.
{"title":"A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit","authors":"Nicholas Sutardja, Jaeduk Han, Nathan Narevsky, E. Alon","doi":"10.1109/ESSCIRC.2019.8902684","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902684","url":null,"abstract":"This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm2, and consumes 0.72-0.62 pJ/bit.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117223691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902656
M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra
This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.
{"title":"2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications","authors":"M. Carissimi, R. Mukherjee, V. Tyagi, F. Disegni, Davide Manfrè, C. Torti, D. Gallinari, S. Rossi, A. Gambero, D. Brambilla, P. Zuliani, R. Zurla, A. Cabrini, G. Torelli, M. Pasotti, C. Auricchio, E. Calvetti, L. Capecchi, L. Croce, Stefano Zanchi, V. Rana, Preeti Mishra","doi":"10.1109/ESSCIRC.2019.8902656","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902656","url":null,"abstract":"This letter presents a 2-Mb embedded phase change memory (ePCM) macrocell designed in 90-nm BJT-CMOS-DMOS (BCD) technology able to address the next generation of automotive and smart-power products exploiting an ePCM cell based on a Ge-rich chalcogenide alloy. The optimized memory allows 16-ns random access time and 5-Mbit/s write throughput from −40 °C to 175 °C, with 100 kcycle endurance. The sense amplifier, the programming circuitry, and the data processing logic able to meet automotive requirements are described. The silicon results are provided.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129410445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902680
Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee
A differential NAND-structured physically unclonable function (PUF) with 20F2 area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (Vth) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to Vth variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.
{"title":"A 20F2 Area-Efficient Differential nand-Structured Physically Unclonable Function for Low-Cost IoT Security","authors":"Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee","doi":"10.1109/ESSCIRC.2019.8902680","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902680","url":null,"abstract":"A differential NAND-structured physically unclonable function (PUF) with 20F2 area per bit is proposed for cost-effective Internet of Things applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized nMOS transistors by effectively amplifying threshold voltage (Vth) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to Vth variation, which is desired for stability, and faster operation than leakage current-based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133957482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ESSCIRC.2019.8902823
Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta
The terahertz frequency range beyond 3 THz has exciting potential to have a transformative impact in a wide range of applications, including chemical and biomedical sensing, spectroscopy, imaging, and short-distance wireless communication. While there have been significant advancements in silicon-based THz imagers in the frequency ranges below 1 THz, technological development beyond 3 THz has been impeded by the lack of solid-state sources in this frequency range. In addition, the design space beyond 3 THz opens up fundamentally new challenges across electronics and the electromagnetic interface. In this spectral range, the wavelength is small enough (λox ≈ 50 μm at 3 THz) that a vertical via from the top antenna layer to the detector is a distributed element (transmission line or radiator). In this letter, we follow a careful circuits-electromagnetics co-design approach toward a hybrid imaging system with a 100-pixel CMOS imager that interfaces with a THz quantum cascade laser frequency comb that spans 3.25–3.5 THz with mode spacing of 17 GHz. The array chip, while designed for an optimal operation across 2.7–2.9 THz, demonstrates an average noise equivalent power (NEP) (across pixels) of $1260,{text{pW}}/sqrt {{text{Hz}}} $ between 3.25–3.5 THz and a projected NEP of $284,{text{pW}}/sqrt {{text{Hz}}} $ across the design range of 2.7–2.9 THz. To the best of our knowledge, we demonstrate for the first time full THz imaging in a hybrid quantum cascade laser (QCL)–CMOS fashion. This approach allows future works to leverage both QCL and CMOS technologies to demonstrate new technological advances for systems in the 1–10 THz range.
{"title":"A Hybrid THz Imaging System With a 100-Pixel CMOS Imager and a 3.25–3.50 THz Quantum Cascade Laser Frequency Comb","authors":"Todd Joseph Smith, A. Broome, Daniel Stanley, J. Westberg, G. Wysocki, K. Sengupta","doi":"10.1109/ESSCIRC.2019.8902823","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2019.8902823","url":null,"abstract":"The terahertz frequency range beyond 3 THz has exciting potential to have a transformative impact in a wide range of applications, including chemical and biomedical sensing, spectroscopy, imaging, and short-distance wireless communication. While there have been significant advancements in silicon-based THz imagers in the frequency ranges below 1 THz, technological development beyond 3 THz has been impeded by the lack of solid-state sources in this frequency range. In addition, the design space beyond 3 THz opens up fundamentally new challenges across electronics and the electromagnetic interface. In this spectral range, the wavelength is small enough (λox ≈ 50 μm at 3 THz) that a vertical via from the top antenna layer to the detector is a distributed element (transmission line or radiator). In this letter, we follow a careful circuits-electromagnetics co-design approach toward a hybrid imaging system with a 100-pixel CMOS imager that interfaces with a THz quantum cascade laser frequency comb that spans 3.25–3.5 THz with mode spacing of 17 GHz. The array chip, while designed for an optimal operation across 2.7–2.9 THz, demonstrates an average noise equivalent power (NEP) (across pixels) of $1260,{text{pW}}/sqrt {{text{Hz}}} $ between 3.25–3.5 THz and a projected NEP of $284,{text{pW}}/sqrt {{text{Hz}}} $ across the design range of 2.7–2.9 THz. To the best of our knowledge, we demonstrate for the first time full THz imaging in a hybrid quantum cascade laser (QCL)–CMOS fashion. This approach allows future works to leverage both QCL and CMOS technologies to demonstrate new technological advances for systems in the 1–10 THz range.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：