Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919411
Fernando D. Silva, D. Micha
Theoretical simulations of solar cell current-voltage characteristics provide important information for a better design of the device structure, such as layers thicknesses and doping levels, in order to obtain high photovoltaic conversion efficiency. The inclusion of precise material parameters is critical to obtain reliable results and detailed understanding of the simulated device operation. In this study, GaAs solar cell structures were simulated by drift-diffusion model with SCAPS-1D in order to optimize the performance under 1 sun illumination. Moreover, we used the published results of some devices as references to infer their structures, as the details are normally not completely disclosed by the authors. To do so, an optimization study was required to probe different materials, thicknesses and doping levels for the layers. With the inferred structure, it was possible to evaluate the possibility of improvements through variation of the structure parameters to achieve even higher efficiencies.
{"title":"High-Efficiency GaAs Solar Cell Optimization by Theoretical Simulation","authors":"Fernando D. Silva, D. Micha","doi":"10.1109/SBMicro.2019.8919411","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919411","url":null,"abstract":"Theoretical simulations of solar cell current-voltage characteristics provide important information for a better design of the device structure, such as layers thicknesses and doping levels, in order to obtain high photovoltaic conversion efficiency. The inclusion of precise material parameters is critical to obtain reliable results and detailed understanding of the simulated device operation. In this study, GaAs solar cell structures were simulated by drift-diffusion model with SCAPS-1D in order to optimize the performance under 1 sun illumination. Moreover, we used the published results of some devices as references to infer their structures, as the details are normally not completely disclosed by the authors. To do so, an optimization study was required to probe different materials, thicknesses and doping levels for the layers. With the inferred structure, it was possible to evaluate the possibility of improvements through variation of the structure parameters to achieve even higher efficiencies.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127057413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919380
Gabriel Maranhão, J. G. Guimarães
The propose of this work is to evolve the studies on neuromorphic circuits by simulating transistors models that look the most with the ones used in commercial process. Since most of data about company models contain a restricted access, some universities provide predictions models to reproduce the real ones. In this paper we present a silicon analog integrate and fire neuron (I&F), proposed by G. Indiveri as a part of a neuromorphic device. Using 32nm CMOS technology simulated in LTspice with BSIM4v4 and applying predictive parameters provides by Predictive Technology Model (PTM), we were able to reduce the source power, to 0.9V, and chip size of the latest design which was implemented using a 180nm CMOS process at 1.8 power supply.
{"title":"Integrate and Fire Neuron Implementation using CMOS Predictive Technology Model for 32nm","authors":"Gabriel Maranhão, J. G. Guimarães","doi":"10.1109/SBMicro.2019.8919380","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919380","url":null,"abstract":"The propose of this work is to evolve the studies on neuromorphic circuits by simulating transistors models that look the most with the ones used in commercial process. Since most of data about company models contain a restricted access, some universities provide predictions models to reproduce the real ones. In this paper we present a silicon analog integrate and fire neuron (I&F), proposed by G. Indiveri as a part of a neuromorphic device. Using 32nm CMOS technology simulated in LTspice with BSIM4v4 and applying predictive parameters provides by Predictive Technology Model (PTM), we were able to reduce the source power, to 0.9V, and chip size of the latest design which was implemented using a 180nm CMOS process at 1.8 power supply.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133932203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919388
M. Dantas, Denise C. Souza, Alejandro A. Zúñiga-Páez, Wellington A. A. Silva, E. Galeazzo, H. Peres, M. M. Kopelvski
Zinc oxide (ZnO) has attracted considerable interest for a wide range of applications, including its use as an active layer in gas sensor devices and as promising emitters for field emission devices. This paper explores ZnO nanowires growth through thermal oxidation of zinc thin films deposited over glass substrates. We applied this low-complexity IC-compatible procedure for fabricating field emission cathodes. Raman Spectroscopy and Scanning Electron Microscopy show that the processes applied succeeded in obtaining nanoscale structures of ZnO with dimensions up to 4 micrometers in length and 30-100 nanometers in diameter. This study also investigated field emission characteristics of these ZnO nanowires. Electrical characterization showed an intense electron field emission with good uniformity of the emitted current on the active area of the device, with a low turn-on electric field (2.4 volts/micrometer). These results demonstrate that the low-complex fabrication procedures adopted as well as the ZnO nanomaterial itself are suitable for FE devices development.
{"title":"ZnO Nanowires Growth from Thin Zinc Films for Field Emission Purposes","authors":"M. Dantas, Denise C. Souza, Alejandro A. Zúñiga-Páez, Wellington A. A. Silva, E. Galeazzo, H. Peres, M. M. Kopelvski","doi":"10.1109/SBMicro.2019.8919388","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919388","url":null,"abstract":"Zinc oxide (ZnO) has attracted considerable interest for a wide range of applications, including its use as an active layer in gas sensor devices and as promising emitters for field emission devices. This paper explores ZnO nanowires growth through thermal oxidation of zinc thin films deposited over glass substrates. We applied this low-complexity IC-compatible procedure for fabricating field emission cathodes. Raman Spectroscopy and Scanning Electron Microscopy show that the processes applied succeeded in obtaining nanoscale structures of ZnO with dimensions up to 4 micrometers in length and 30-100 nanometers in diameter. This study also investigated field emission characteristics of these ZnO nanowires. Electrical characterization showed an intense electron field emission with good uniformity of the emitted current on the active area of the device, with a low turn-on electric field (2.4 volts/micrometer). These results demonstrate that the low-complex fabrication procedures adopted as well as the ZnO nanomaterial itself are suitable for FE devices development.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133701107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919301
L. Stucchi-Zucchi, Audrey R. Silva, J. A. Diniz
Junctionless-Field-Effect-Transistor (JL-FET) devices were fabricated with Silicon-On-Insulator (SOI) technology. The device channel area was thinned down to nanometer-scale by silicon etching in a solution of NH4 OH with the area to be exposed define using optical lithography and silicon oxide etching in HF buffer solution. The hardmask was stripped and dopant diffusion on a Phosphorus saturated furnace was carried out to achieve the dopant concentration necessary. The gate oxide was silicon oxide grown thermally in a dry environment. The electrical contacts were fabricated using optical lithography, silicon oxide etching in HF solution, aluminum sputtering and lift-off. The electrical contacts were annealed in forming gas (H2 + N2) for 10 minutes. Gate metal was titanium nitride deposited using sputtering and defined using optical lithography and lift-off. A layer of aluminum was deposited with the titanium nitride to protect it against oxidation. Some advantages were observed on this updated process. The outlines of the etched area are observable with optical microscopy in a dark field filter, making process confirmation easy. The same outlines are exposed for the majority of fabrication time, making atomic force microscopy (AFM) possible. Also, pseudo-MOS measurements are possible even before the gate metallization, which gives insight on the fabrication process and quality. The measurements on devices fully fabricated showed increasing control of the gate bias on the drain current, which is in agreement to JL-FET predictions, although these behave a gated resistor due to their negative threshold voltage. This happens because the $mathrm{V}_{OH}$ is high even for low a $mathrm{V}_{GS}$, making the $mathrm{V}_{DS}$ needed to achieve saturation mode unmanageable. The electrical contacts were ohmic in nature and showed that the dopant diffusion process is compatible with JL-FET fabrication. Overall, these devices show that the JL-FET, and other nanometer-scaled structures, are possible to achieve using the channel thinning in NH4 OH solution silicon etching.
{"title":"Junctionless-FET device fabrication using silicon etching in NH4OH solution: device behaviour according to etching time","authors":"L. Stucchi-Zucchi, Audrey R. Silva, J. A. Diniz","doi":"10.1109/SBMicro.2019.8919301","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919301","url":null,"abstract":"Junctionless-Field-Effect-Transistor (JL-FET) devices were fabricated with Silicon-On-Insulator (SOI) technology. The device channel area was thinned down to nanometer-scale by silicon etching in a solution of NH4 OH with the area to be exposed define using optical lithography and silicon oxide etching in HF buffer solution. The hardmask was stripped and dopant diffusion on a Phosphorus saturated furnace was carried out to achieve the dopant concentration necessary. The gate oxide was silicon oxide grown thermally in a dry environment. The electrical contacts were fabricated using optical lithography, silicon oxide etching in HF solution, aluminum sputtering and lift-off. The electrical contacts were annealed in forming gas (H2 + N2) for 10 minutes. Gate metal was titanium nitride deposited using sputtering and defined using optical lithography and lift-off. A layer of aluminum was deposited with the titanium nitride to protect it against oxidation. Some advantages were observed on this updated process. The outlines of the etched area are observable with optical microscopy in a dark field filter, making process confirmation easy. The same outlines are exposed for the majority of fabrication time, making atomic force microscopy (AFM) possible. Also, pseudo-MOS measurements are possible even before the gate metallization, which gives insight on the fabrication process and quality. The measurements on devices fully fabricated showed increasing control of the gate bias on the drain current, which is in agreement to JL-FET predictions, although these behave a gated resistor due to their negative threshold voltage. This happens because the $mathrm{V}_{OH}$ is high even for low a $mathrm{V}_{GS}$, making the $mathrm{V}_{DS}$ needed to achieve saturation mode unmanageable. The electrical contacts were ohmic in nature and showed that the dopant diffusion process is compatible with JL-FET fabrication. Overall, these devices show that the JL-FET, and other nanometer-scaled structures, are possible to achieve using the channel thinning in NH4 OH solution silicon etching.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114717061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919450
Marcelo D. de Lima, T. Borrely, A. Quivy
We estimated the reduction of surface recombination velocity (SRV) resulting from the deposition of an $Al_{0.28}Ga_{0.72}As$ window layer (WL) on top of a GaAs Solar cell (SC) only by analyzing, simulating and comparing $mathrm{I}times mathrm{V}$ curves. Two samples were analyzed, where the only difference between them was the presence of the WL. We separately calculated the optical changes caused by the introduction of the $Al_{0.28}Ga_{0.72}As$ and then we estimated how much of the performance enhancement was due to the optical changes and how much was due to the SRV variation. Our estimation indicated one order of magnitude reduction in SRV (from 1 $times$ 107 cm/s to 1 $times 10^{6}$ cm/s).
{"title":"Evaluation of Surface Recombination Velocity by Means of Computational Simulations and I×V Curves","authors":"Marcelo D. de Lima, T. Borrely, A. Quivy","doi":"10.1109/SBMicro.2019.8919450","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919450","url":null,"abstract":"We estimated the reduction of surface recombination velocity (SRV) resulting from the deposition of an $Al_{0.28}Ga_{0.72}As$ window layer (WL) on top of a GaAs Solar cell (SC) only by analyzing, simulating and comparing $mathrm{I}times mathrm{V}$ curves. Two samples were analyzed, where the only difference between them was the presence of the WL. We separately calculated the optical changes caused by the introduction of the $Al_{0.28}Ga_{0.72}As$ and then we estimated how much of the performance enhancement was due to the optical changes and how much was due to the SRV variation. Our estimation indicated one order of magnitude reduction in SRV (from 1 $times$ 107 cm/s to 1 $times 10^{6}$ cm/s).","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117062212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919369
Jeferson C. Rosario, Celso Peter, J. Inácio, M. Much, H. Boudinov, Willyan Hasenkamp Carreira
Recent studies have demonstrated the intracranial pressure (ICP) monitoring is an important tool for cerebral perfusion pressure (CPP) calculation and cerebral blood flow (CBF) assessment, reducing significantly the mortality statistics. Traumatic brain injury (TBI), several others pathologies and neurosurgery conditions have been using the ICP monitoring technique. With the waves of the microelectronics and microelectromechanical systems (MEMS) industry evolution, it was possible to put the transducer and all the electronics inside the catheter tip, allowing a less invasive monitoring and decreasing the risk of infection. The state of art catheters with micro transducer on the tip can be divided into three groups: strain-gauge, optical fiber and pneumatic. Each group has its own characteristics, however the strain-gauge based has been demonstrated to be a robust solution, reliable, cost effective and with sufficient accuracy. In the present work, it was developed a strain-gauge micro transducer implantable catheter for intracranial pressure monitoring. The packaging processes adopted were the standard used by the semiconductor industry, however considering application special requirements, several process parameters and assemblage was adapted to the geometry and materials used (i.e. biocompatible) as well as, taking in consideration low volume production of medical devices. The prototypes assembled showed variations on the zero drift test. The temperature drift was 0,63 and 0,89 cmH2O/°C and the accuracy, ±1 cmH2O.
{"title":"Packaging Development of an Implantable Intracranial Pressure Catheter","authors":"Jeferson C. Rosario, Celso Peter, J. Inácio, M. Much, H. Boudinov, Willyan Hasenkamp Carreira","doi":"10.1109/SBMicro.2019.8919369","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919369","url":null,"abstract":"Recent studies have demonstrated the intracranial pressure (ICP) monitoring is an important tool for cerebral perfusion pressure (CPP) calculation and cerebral blood flow (CBF) assessment, reducing significantly the mortality statistics. Traumatic brain injury (TBI), several others pathologies and neurosurgery conditions have been using the ICP monitoring technique. With the waves of the microelectronics and microelectromechanical systems (MEMS) industry evolution, it was possible to put the transducer and all the electronics inside the catheter tip, allowing a less invasive monitoring and decreasing the risk of infection. The state of art catheters with micro transducer on the tip can be divided into three groups: strain-gauge, optical fiber and pneumatic. Each group has its own characteristics, however the strain-gauge based has been demonstrated to be a robust solution, reliable, cost effective and with sufficient accuracy. In the present work, it was developed a strain-gauge micro transducer implantable catheter for intracranial pressure monitoring. The packaging processes adopted were the standard used by the semiconductor industry, however considering application special requirements, several process parameters and assemblage was adapted to the geometry and materials used (i.e. biocompatible) as well as, taking in consideration low volume production of medical devices. The prototypes assembled showed variations on the zero drift test. The temperature drift was 0,63 and 0,89 cmH2O/°C and the accuracy, ±1 cmH2O.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129318163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919375
M. Watanabe, W. Chiappim, V. Christiano, S. G. S. Filho
This paper discusses the metal-oxide-semiconductor (MOS) solar cells for energy harvesting from indoor light emitting diode (LED) illumination using Al/SiO2/Si-p structures. Wafers of the Si-p (100) with a resistivity of $10Omega $.cm were used. The gate dielectric was grown by rapid thermal processing (RTP) with thicknesses of 1.65, 1.73, 2.10 and 2.23 nm. The main parameters studied were extracted using electrical characterization through IxV curves of the MOS solar cells with total areas of 3.24 $text{c}mathrm {m}^{2}$. At first, it was observed an increase of the dark current density from 0.49 to $4.4mu text{A}/text{c}mathrm {m}^{2}$ for the thickness varying from 1.65 to 2.23 nm. It is worthy of note the increase of the generated power from 8.1 to $46.7mu text{W}/text{c}mathrm {m}^{2}$ with the rise of the thickness in the range of 1.65 to 2.23 nm for a constant incident power of 5 mW/$text{c}mathrm {m}^{2}$. In this case, the lower the thickness, the higher the tunneling current through the gate dielectrics, which causes the decrease of the depletion region length and this decrease, in turn, makes the generation current density lower in the depletion region. Also, the reduction of the short-circuit current (JsC) due to the increase of the widths (W) and spacings (S) of the fishbone-grating geometry was well-correlated with the decrease of the perimeter (Pe) and the rise of the aspect ratio W/S.
{"title":"MOS solar cells for indoor LED energy harvesting: influence of the grating geometry and the thickness of the gate dielectrics","authors":"M. Watanabe, W. Chiappim, V. Christiano, S. G. S. Filho","doi":"10.1109/SBMicro.2019.8919375","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919375","url":null,"abstract":"This paper discusses the metal-oxide-semiconductor (MOS) solar cells for energy harvesting from indoor light emitting diode (LED) illumination using Al/SiO2/Si-p structures. Wafers of the Si-p (100) with a resistivity of $10Omega $.cm were used. The gate dielectric was grown by rapid thermal processing (RTP) with thicknesses of 1.65, 1.73, 2.10 and 2.23 nm. The main parameters studied were extracted using electrical characterization through IxV curves of the MOS solar cells with total areas of 3.24 $text{c}mathrm {m}^{2}$. At first, it was observed an increase of the dark current density from 0.49 to $4.4mu text{A}/text{c}mathrm {m}^{2}$ for the thickness varying from 1.65 to 2.23 nm. It is worthy of note the increase of the generated power from 8.1 to $46.7mu text{W}/text{c}mathrm {m}^{2}$ with the rise of the thickness in the range of 1.65 to 2.23 nm for a constant incident power of 5 mW/$text{c}mathrm {m}^{2}$. In this case, the lower the thickness, the higher the tunneling current through the gate dielectrics, which causes the decrease of the depletion region length and this decrease, in turn, makes the generation current density lower in the depletion region. Also, the reduction of the short-circuit current (JsC) due to the increase of the widths (W) and spacings (S) of the fishbone-grating geometry was well-correlated with the decrease of the perimeter (Pe) and the rise of the aspect ratio W/S.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126868942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919270
A. D. M. Nogueira, P. Agopian, J. Martino
Electrical characterization of a silicon nanowire Tunnel Field Effect Transistor (TFET) is used to construct a lookup table in order to model and simulate analog circuit through Verilog-A approach. The performance of a differential amplifier with current mirror load is evaluated using the TFET lookup table model and the TSMC 130 nm CMOS process design kit. Both circuits are evaluated in two different bias, with the TFET circuit presenting 20 dB higher voltage gain and power consumption of at least three orders of magnitude smaller than CMOS technology. All the simulations were realized with Cadence Spectre software.
{"title":"Silicon Nanowire Tunnel-FET Differential Amplifier Using Verilog-A Lookup Table Approach","authors":"A. D. M. Nogueira, P. Agopian, J. Martino","doi":"10.1109/SBMicro.2019.8919270","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919270","url":null,"abstract":"Electrical characterization of a silicon nanowire Tunnel Field Effect Transistor (TFET) is used to construct a lookup table in order to model and simulate analog circuit through Verilog-A approach. The performance of a differential amplifier with current mirror load is evaluated using the TFET lookup table model and the TSMC 130 nm CMOS process design kit. Both circuits are evaluated in two different bias, with the TFET circuit presenting 20 dB higher voltage gain and power consumption of at least three orders of magnitude smaller than CMOS technology. All the simulations were realized with Cadence Spectre software.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121655410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-08-01DOI: 10.1109/SBMicro.2019.8919401
Marco R. Cavallari, J. E. E. Izquierdo, D. C. García, V. A. M. Nogueira, J. D. S. Oliveira, L. M. Pastrana, I. Kymissis, F. Fonseca
Polyvinyl phenol with a cross-linker agent was demonstrated as a dielectric film and incorporated to a bottom gate organic transistor structure. Films were shown transparent to visible light, resistant to organic solvents and compatible with plasma etching to open vias. Only cross-linked films, however, withstood lithography in order to pattern bottom contact electrodes on top of the dielectric. Cross-linked films showed a dielectric constant of ca. 5, which is higher than polymethylmethacrylate and silicon oxide. The devices herein have potential to be applied in flexible sensor arrays from organic transistors.
{"title":"Cross-linked polyvinyl phenol as dielectric for flexible bottom gate bottom contact transistors","authors":"Marco R. Cavallari, J. E. E. Izquierdo, D. C. García, V. A. M. Nogueira, J. D. S. Oliveira, L. M. Pastrana, I. Kymissis, F. Fonseca","doi":"10.1109/SBMicro.2019.8919401","DOIUrl":"https://doi.org/10.1109/SBMicro.2019.8919401","url":null,"abstract":"Polyvinyl phenol with a cross-linker agent was demonstrated as a dielectric film and incorporated to a bottom gate organic transistor structure. Films were shown transparent to visible light, resistant to organic solvents and compatible with plasma etching to open vias. Only cross-linked films, however, withstood lithography in order to pattern bottom contact electrodes on top of the dielectric. Cross-linked films showed a dielectric constant of ca. 5, which is higher than polymethylmethacrylate and silicon oxide. The devices herein have potential to be applied in flexible sensor arrays from organic transistors.","PeriodicalId":403446,"journal":{"name":"2019 34th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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