Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898203
C. Boit, Norbert Schafer, D. Abou‐Ras, Clemens Helfmeier, A. Glowacki, U. Kerst
Failure analysis (FA) of electronic devices today is mostly conducted through the device backside. Advanced silicon (Si) backside preparation for this purpose has developed over the past years, with a final Si thickness from around 300μm to 100μm down to around 20μm to 10μm. This paper discusses what to expect if Si can be processed a little thinner, from 20μm down to a few μm. Improvement of optical imaging, spectral extension of photon emission and expanded optical interaction for stimulation techniques are investigated. Further, Si thickness is coming close to the penetration depth of particle beams. The interaction potential for device analysis is discussed, preliminary results are presented.
{"title":"Backside failure analysis techniques: What's the gain of silicon getting thinner?","authors":"C. Boit, Norbert Schafer, D. Abou‐Ras, Clemens Helfmeier, A. Glowacki, U. Kerst","doi":"10.1109/IPFA.2014.6898203","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898203","url":null,"abstract":"Failure analysis (FA) of electronic devices today is mostly conducted through the device backside. Advanced silicon (Si) backside preparation for this purpose has developed over the past years, with a final Si thickness from around 300μm to 100μm down to around 20μm to 10μm. This paper discusses what to expect if Si can be processed a little thinner, from 20μm down to a few μm. Improvement of optical imaging, spectral extension of photon emission and expanded optical interaction for stimulation techniques are investigated. Further, Si thickness is coming close to the penetration depth of particle beams. The interaction potential for device analysis is discussed, preliminary results are presented.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898199
Bin Zhang, G. Tao
Thermal shock is usually used for LED wire-bonding accelerated life testing, and the failure is commonly treated as a low-cycle fatigue problem. The lifetime analyses which base on the Coffin-Manson model never consider the modulus saltation of silicone enclosure with the temperature changing. With an extensive DOE, an improved Coffin-Manson model is proposed, which also copes with the glass transition of silicone encapsolent. With this improved model, a more accurate prediction of wire-bonding reliability can be made.
{"title":"An improved Coffin-Manson model for mid-power LED wire-bonding reliability","authors":"Bin Zhang, G. Tao","doi":"10.1109/IPFA.2014.6898199","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898199","url":null,"abstract":"Thermal shock is usually used for LED wire-bonding accelerated life testing, and the failure is commonly treated as a low-cycle fatigue problem. The lifetime analyses which base on the Coffin-Manson model never consider the modulus saltation of silicone enclosure with the temperature changing. With an extensive DOE, an improved Coffin-Manson model is proposed, which also copes with the glass transition of silicone encapsolent. With this improved model, a more accurate prediction of wire-bonding reliability can be made.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127385988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898159
S. Moreau, D. Bouchu, G. Audoit
The present methodology proposes to reduce curtaining artifacts using a plasma-FIB when milling relatively deep trenches. Finally, the methodology is very fast (<;1 h), simple to set up and can be automated. Its purpose consists in eliminating or reducing the origin of curtaining artifacts by judicious milling. This methodology can advantageously replace the rocking method presented in the literature.
{"title":"Fast and easy sample preparation with reduced curtaining artifacts using a P-FIB","authors":"S. Moreau, D. Bouchu, G. Audoit","doi":"10.1109/IPFA.2014.6898159","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898159","url":null,"abstract":"The present methodology proposes to reduce curtaining artifacts using a plasma-FIB when milling relatively deep trenches. Finally, the methodology is very fast (<;1 h), simple to set up and can be automated. Its purpose consists in eliminating or reducing the origin of curtaining artifacts by judicious milling. This methodology can advantageously replace the rocking method presented in the literature.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127155826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898155
Chow Yew Meng, Bai Haonan, G. Tan, P. Salinas, Johney Ou Yang
This failure analysis is based on a 28nm FPGA IDelay logic block which features an all programmable, 32-tap delay line. Each tap delay is carefully calibrated to provide an absolute delay value of 78ps independent of process voltage, and temperature variations. To locate the failing IDelay site, scan chain methodology was utilized. Combinations of delay tests were created to localize the defect within the IDelay block and the failure was isolated to a single tap delay circuit. Photon emission analysis validated the electrical analysis with an emission successfully detected at the suspect area. Physical failure analysis utilizing a combination of AFP current contrast imaging and nano-probing analysis at the contact layer further isolated the area of interest to a specific transistor. Die delayering and SEM high beam inspection did not show any anomalies, but subsequent TEM analysis revealed diffusion bridging at the failure location.
{"title":"Electrical and physical analysis of a 28nm FPGA programmable delay circuit single tap delay failure","authors":"Chow Yew Meng, Bai Haonan, G. Tan, P. Salinas, Johney Ou Yang","doi":"10.1109/IPFA.2014.6898155","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898155","url":null,"abstract":"This failure analysis is based on a 28nm FPGA IDelay logic block which features an all programmable, 32-tap delay line. Each tap delay is carefully calibrated to provide an absolute delay value of 78ps independent of process voltage, and temperature variations. To locate the failing IDelay site, scan chain methodology was utilized. Combinations of delay tests were created to localize the defect within the IDelay block and the failure was isolated to a single tap delay circuit. Photon emission analysis validated the electrical analysis with an emission successfully detected at the suspect area. Physical failure analysis utilizing a combination of AFP current contrast imaging and nano-probing analysis at the contact layer further isolated the area of interest to a specific transistor. Die delayering and SEM high beam inspection did not show any anomalies, but subsequent TEM analysis revealed diffusion bridging at the failure location.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898188
G. Mura, M. Vanzi
The paper focuses on Reliability of Reliability Predictions by comparison with available Reliability Data Sheet and Accelerated Stress Test results on commercially available devices. The striking difference in the predicted MTTFs (Mean Time To Failure) is discussed.
{"title":"Reliability prediction and real world for LED lamps","authors":"G. Mura, M. Vanzi","doi":"10.1109/IPFA.2014.6898188","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898188","url":null,"abstract":"The paper focuses on Reliability of Reliability Predictions by comparison with available Reliability Data Sheet and Accelerated Stress Test results on commercially available devices. The striking difference in the predicted MTTFs (Mean Time To Failure) is discussed.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122180338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898161
Huang Yamin, H. Tan, D. Wang, J. Lam, Z. Mai
Time-dependent dielectric breakdown (TDDB) of ultra-low-k materials is one of the most critical reliability issues in leading edge Cu/low-k technology due to the weak intrinsic breakdown strength of ultra-low-k materials as compared to that of SiO2 dielectrics. With continuous device dimension scaling, this problem is further exacerbated for Cu/ultra-low-k interconnects. There are different TDDB models proposed to address this issue, however, there is no direct evidence to get into the failure mechanism. The key technical reason is that the damage to the dielectric material properties is not able to be monitored during the TDDB test. In this paper, we will describe the experiments and the setup used to capture the dielectric bonding damage during the reliability test. Raman and FTIR complimentary vibrational spectroscopy were used to detect the dielectric bonding on the pattern wafer, which has historically been a challenge for current leading edge Cu/low k or ultra-low-k technologies due to the influence of the metal interconnects and the thin dielectric layer. From our experiments, we successfully detected the TDDB degradation behavior of ultra-low-k dielectric in Cu/ultra-low-k interconnects and found the intrinsic degradation of the ultra-low-k dielectric. Further study on the damaged structures with TEM analysis revealed that the Ta ions migrated from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. In addition, no out-diffusion of Cu ions was observed in our TEM investigation on Cu/Ta/TaN/SiCOH structures.
{"title":"Experiments and results of Raman and FTIR complementary vibrational spectroscopy for IC reliability failure analysis","authors":"Huang Yamin, H. Tan, D. Wang, J. Lam, Z. Mai","doi":"10.1109/IPFA.2014.6898161","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898161","url":null,"abstract":"Time-dependent dielectric breakdown (TDDB) of ultra-low-k materials is one of the most critical reliability issues in leading edge Cu/low-k technology due to the weak intrinsic breakdown strength of ultra-low-k materials as compared to that of SiO2 dielectrics. With continuous device dimension scaling, this problem is further exacerbated for Cu/ultra-low-k interconnects. There are different TDDB models proposed to address this issue, however, there is no direct evidence to get into the failure mechanism. The key technical reason is that the damage to the dielectric material properties is not able to be monitored during the TDDB test. In this paper, we will describe the experiments and the setup used to capture the dielectric bonding damage during the reliability test. Raman and FTIR complimentary vibrational spectroscopy were used to detect the dielectric bonding on the pattern wafer, which has historically been a challenge for current leading edge Cu/low k or ultra-low-k technologies due to the influence of the metal interconnects and the thin dielectric layer. From our experiments, we successfully detected the TDDB degradation behavior of ultra-low-k dielectric in Cu/ultra-low-k interconnects and found the intrinsic degradation of the ultra-low-k dielectric. Further study on the damaged structures with TEM analysis revealed that the Ta ions migrated from the Ta/TaN barrier bi-layer into the ultra-low-k dielectrics. In addition, no out-diffusion of Cu ions was observed in our TEM investigation on Cu/Ta/TaN/SiCOH structures.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131925338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898193
A. Du, J. Zhu, Y. Zhou, B. Liu, E. Er, Z. Mo, S. P. Zhao, J. Lam
There is increasing demand of advanced TEM techniques for modern IC failure analysis. Some practical issues of using TEM holography in studying MOSFETs P-N junction, channel strain and magnetic domains are discussed in this paper. It is shown that salicide/contact have significant effect on the phase diagram of shallow S/D P-N junction and hinders its application in shallow junction devices. In holography strain measurement, it is found that intensity of diffraction beam depends strongly on the sample thickness and crystallography orientation. A proper sample thickness should be chosen to maximize the nearly two-beam diffraction beam intensity and therefore the measurement sensitivity. Magnetic domain imaging is much affected by the FIB damage during sample preparation and low energy milling should be employed. At last, it is demonstrated that numerical de-convolution of EELS spectrum provides improved energy resolution for more reliable dielectric bonding chemical analysis.
{"title":"Advanced TEM applications in semiconductor devices","authors":"A. Du, J. Zhu, Y. Zhou, B. Liu, E. Er, Z. Mo, S. P. Zhao, J. Lam","doi":"10.1109/IPFA.2014.6898193","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898193","url":null,"abstract":"There is increasing demand of advanced TEM techniques for modern IC failure analysis. Some practical issues of using TEM holography in studying MOSFETs P-N junction, channel strain and magnetic domains are discussed in this paper. It is shown that salicide/contact have significant effect on the phase diagram of shallow S/D P-N junction and hinders its application in shallow junction devices. In holography strain measurement, it is found that intensity of diffraction beam depends strongly on the sample thickness and crystallography orientation. A proper sample thickness should be chosen to maximize the nearly two-beam diffraction beam intensity and therefore the measurement sensitivity. Magnetic domain imaging is much affected by the FIB damage during sample preparation and low energy milling should be employed. At last, it is demonstrated that numerical de-convolution of EELS spectrum provides improved energy resolution for more reliable dielectric bonding chemical analysis.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121077882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898172
F. K. Yong
The paper shares the application of electron diffraction spot indexing to identify intermetallic phases in copper wire bond. Standard Scanning Transmission Electron Microscopy (STEM) technique with a converged electron probe was modified to produce parallel nano beam for forming electron diffraction spot patterns, CuAl(η2)and CuAl2(θ) phases in copper wire bond were identified by indexing the diffraction spots.
{"title":"Identification of Cu-Al intermetallic phases of copper wire bonding using TEM nano beam diffraction indexing technique","authors":"F. K. Yong","doi":"10.1109/IPFA.2014.6898172","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898172","url":null,"abstract":"The paper shares the application of electron diffraction spot indexing to identify intermetallic phases in copper wire bond. Standard Scanning Transmission Electron Microscopy (STEM) technique with a converged electron probe was modified to produce parallel nano beam for forming electron diffraction spot patterns, CuAl(η2)and CuAl2(θ) phases in copper wire bond were identified by indexing the diffraction spots.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129712513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898176
S. Goh, G. F. You, B. Yeoh, H. Hao, N. Chung, C. Yap, J. Lam
Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.
{"title":"Wafer-level fault isolation approach to debug integrated circuits JTAG failures","authors":"S. Goh, G. F. You, B. Yeoh, H. Hao, N. Chung, C. Yap, J. Lam","doi":"10.1109/IPFA.2014.6898176","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898176","url":null,"abstract":"Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity, without which, chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique called frequency mapping can be extended to JTAG data registers shift failures with the help of basic JTAG test methodology knowledge.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131160191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-18DOI: 10.1109/IPFA.2014.6898145
H. Ceric, S. Selberherr
Characteristic of solder bumps is that during technology processing and usage their material composition changes. We present a model for describing a growth of intermetallic compound inside a solder bump under the influence of electro-migration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.
{"title":"Electromigration reliability of solder bumps","authors":"H. Ceric, S. Selberherr","doi":"10.1109/IPFA.2014.6898145","DOIUrl":"https://doi.org/10.1109/IPFA.2014.6898145","url":null,"abstract":"Characteristic of solder bumps is that during technology processing and usage their material composition changes. We present a model for describing a growth of intermetallic compound inside a solder bump under the influence of electro-migration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings.","PeriodicalId":409316,"journal":{"name":"Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123621677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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