Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155633
M. Phan, J. Shier, A. Evans
IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled c
{"title":"A fast 1024-bit bipolar RAM using JFET load devices","authors":"M. Phan, J. Shier, A. Evans","doi":"10.1109/ISSCC.1977.1155633","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155633","url":null,"abstract":"IT HAS LONG BEEN recognized that the need for compact load devices is one of the main problems in building dense bipolar integrated circuits. In recent years several quite promising new approaches to this problem have been developed, including: (1) very high value P-type resistors made by ion implantation (2) the use of lateral PNP transistors to supply and limit the operating current ( 12L) and (3) various kinds of vacuumdeposited resistive materials. The JFET loads to be presented provide yet another way of achieving very compact load elements in bipolar integrated circuits. The JFET loads use the lightlydoped N-type channels which appear under the isolation oxide in an oxide-isolated structure employing an N-type epitaxial layer. These channels arise from the preferential segregation of the dopant during the growth of the isolation oxide’ and have been found to be stable and reproducible. The delineation of the load device is accomplished by a masked P type doping step made prior to epitaxial growth, with the P regions serving as channel stoppers between isolated devices. A load device is produced by simply omitting the channel stopper between two N regions to be connected to the load and thus is physically located in the isolation regions an aspect which substantially improves the circuit density by using space wasted in most bipolar structures; Figures 1 and 4. The load device is best described as a substrate-gate JFET (Figure 2) with many advantages: (1) it is very compact, equivalent resistances of 1 Mi?, being realized in 1 t o 2 mil2 area (including the channel stoppers), (2) i t behaves like a constant-current source, rather like the depletion loads u ed in MOS devices but without the need for gate metalization over it, (3) it connects readily to any part of a transistor collector region without the need for contacts or metalization, (4) its position under thick oxide minimizes parasitic capacitance and sensitivity to potentials of the overlying metalization, ( 5 ) the light doping level in substrate and load gives a low capacitance to substrate, and (6) the sheet resistance and nonlinear properties of these loads can be varied over a very broad range by adjusting process parameters. The process, which provides very shallow double-diffused NPN transistors with washed emitters, PtSi Schottky diodes, and high-beta vertical PNP transistors, lends itself particularly well to the use of a diode-coupled cell for the main storage flipflops in an all-TTL RAM design. As a result a 1024-bit TTL RAM was chosen for the initial design using the JFET load 1 Grove, A S . , Leistiko, 0. and Sah, C.T., “Redistribution of Acceptor and Donor Impurities During Thermal Oxidation of Silicon”, J. Applied Physics, Vol. 35, p. 2695; 1964. Lynes, D.J. and Hodges. D.A., “A Diode-Coupled Bipolar Transistor Memory Cell”, ISSCC Digest of Technical Papers, p. 44-45; Feb., 1970. 2 devices. These loads allowed the use of a compact, low-powerdissipation diode-coupled c","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128300408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155651
R. Muller, H. Nietsch, B. Rossler, E. Wolter
THERE HAS BEEN an increasing interest in recent years in an electrically erasable MOS PROM employing the excellent information retention of the floating gate principle’. Several proposals for N-channel EAROMs are known’ >3. This paper will describe an 8192-bit N-channel EAROM featuring: a ) single transistor cell, b) standard operating voltages and single high voltage pulse for programming and erasure, c), 24-pin package, d) input/output TTL compatible for read and programming, e ) static, no clock required, and fl low standby power.
{"title":"Electrically alterable 8192 bit N-channel MOS PROM","authors":"R. Muller, H. Nietsch, B. Rossler, E. Wolter","doi":"10.1109/ISSCC.1977.1155651","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155651","url":null,"abstract":"THERE HAS BEEN an increasing interest in recent years in an electrically erasable MOS PROM employing the excellent information retention of the floating gate principle’. Several proposals for N-channel EAROMs are known’ >3. This paper will describe an 8192-bit N-channel EAROM featuring: a ) single transistor cell, b) standard operating voltages and single high voltage pulse for programming and erasure, c), 24-pin package, d) input/output TTL compatible for read and programming, e ) static, no clock required, and fl low standby power.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"28 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132828044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155669
C. Shinn
AN ALL MONOLITHIC, dc to > I GI*, amplifier/Schmidt trigger with 8 mV rms input sensitivity has been designed using a junction-isolated 5 GHz fT process in spite of the inherent high capacitances. Included on a 1.39 x 1.59 mm chip are electronic gain control, 180’ phase switching, ECL line driver output, all biasing circuits and a one-shot LED driver. A functional block diagram is shown in Figure 1. The amplifier is composed of a cascade of three identical modified Gilbert gain cells’. The current gain of this type of circuit is set by the ratio of device input impedances which in turn are a function of their quiescent currents. Because the currents are added at the output of each stage, a cascade requires a geometric increase in the power dissipation for each additional stage. N t h even the first stage current constrained to be fairly high to obtain wide bandwidth, a cascade would be unreasonable. Modifying the gain cell by the addition of emitter resistors allows the input impedance and thus the current gain, to become independent of dc bias. Furthermore, this modification generally results in a substantial reduction in the mean squared output noise current (in2) since the expression is changed from:
尽管具有固有的高电容，但采用结隔离的5 GHz fT工艺设计了一种具有8 mV rms输入灵敏度的全单片直流到> I GI*放大器/施密特触发器。包含在1.39 x 1.59 mm芯片上的是电子增益控制，180 '相位开关，ECL线路驱动器输出，所有偏置电路和一个单镜头LED驱动器。功能框图如图1所示。该放大器由三个相同的改良吉尔伯特增益单元级联组成。这种类型电路的电流增益是由器件输入阻抗的比值决定的，而器件输入阻抗又是其静态电流的函数。由于电流是在每一级的输出处增加的，因此级联需要每增加一级的功耗呈几何级数增加。然而，即使将第一级电流约束得相当高以获得较宽的带宽，级联也是不合理的。通过添加射极电阻来修改增益单元，可以使输入阻抗和电流增益与直流偏置无关。此外，这种修改通常会导致均方输出噪声电流(in2)的大幅降低，因为表达式变为:
{"title":"Wideband DC-coupled amp/schmidt","authors":"C. Shinn","doi":"10.1109/ISSCC.1977.1155669","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155669","url":null,"abstract":"AN ALL MONOLITHIC, dc to > I GI*, amplifier/Schmidt trigger with 8 mV rms input sensitivity has been designed using a junction-isolated 5 GHz fT process in spite of the inherent high capacitances. Included on a 1.39 x 1.59 mm chip are electronic gain control, 180’ phase switching, ECL line driver output, all biasing circuits and a one-shot LED driver. A functional block diagram is shown in Figure 1. The amplifier is composed of a cascade of three identical modified Gilbert gain cells’. The current gain of this type of circuit is set by the ratio of device input impedances which in turn are a function of their quiescent currents. Because the currents are added at the output of each stage, a cascade requires a geometric increase in the power dissipation for each additional stage. N t h even the first stage current constrained to be fairly high to obtain wide bandwidth, a cascade would be unreasonable. Modifying the gain cell by the addition of emitter resistors allows the input impedance and thus the current gain, to become independent of dc bias. Furthermore, this modification generally results in a substantial reduction in the mean squared output noise current (in2) since the expression is changed from:","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129876986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155702
H. Mukai, K. Kawarada, K. Kondo, K. Toyoda
A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory
{"title":"Ultra high speed 1K-bit RAM with 7.5 ns access time","authors":"H. Mukai, K. Kawarada, K. Kondo, K. Toyoda","doi":"10.1109/ISSCC.1977.1155702","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155702","url":null,"abstract":"A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155634
G. Louie, J. Wipfli, A. Ebright
{"title":"A dual processor serial data controller chip","authors":"G. Louie, J. Wipfli, A. Ebright","doi":"10.1109/ISSCC.1977.1155634","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155634","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134197068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155715
N. Tsuzuki, Y. Saito, T. Sakai
A HIGH-POWER three-stage transistor amplifier utilizing a bipolar transistor, which can deliver 12W output power at 4 GHz, will be described. The amplifier, exhibiting power gain of l l l3dB, power added efficiency of 17%, and can operate with a 20-V dc power supply, contains seven units of a 3-W bipolar transistor, fabricated with self-aligned electrode formation technology’. Figure 1 shows the block diagram of the amplifier circuit. Each transistor amplifier segment contains input and output matching networks of the microstripline type, and is connected to the power combiner/divider of a double section 3dB quarter wavelength hybrid. Teflon glass-fiber substrates have been used for the matching networks and for the hybrid couplers. In Figures 2 (a) and (b) RF performance characteristics i.e., output power, efficiency and AM-PM conversion coefficient versus input power, and output power versus frequency characteristics at different ambient temperatures are shown. The noise loading characteristics are also satisfactory.
{"title":"A 4-GHz 12-W transistor amplifier utilizing a self-aligned bipolar structure","authors":"N. Tsuzuki, Y. Saito, T. Sakai","doi":"10.1109/ISSCC.1977.1155715","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155715","url":null,"abstract":"A HIGH-POWER three-stage transistor amplifier utilizing a bipolar transistor, which can deliver 12W output power at 4 GHz, will be described. The amplifier, exhibiting power gain of l l l3dB, power added efficiency of 17%, and can operate with a 20-V dc power supply, contains seven units of a 3-W bipolar transistor, fabricated with self-aligned electrode formation technology’. Figure 1 shows the block diagram of the amplifier circuit. Each transistor amplifier segment contains input and output matching networks of the microstripline type, and is connected to the power combiner/divider of a double section 3dB quarter wavelength hybrid. Teflon glass-fiber substrates have been used for the matching networks and for the hybrid couplers. In Figures 2 (a) and (b) RF performance characteristics i.e., output power, efficiency and AM-PM conversion coefficient versus input power, and output power versus frequency characteristics at different ambient temperatures are shown. The noise loading characteristics are also satisfactory.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133702015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155734
J. Heightley
{"title":"Aids to the layout of custom LSI","authors":"J. Heightley","doi":"10.1109/ISSCC.1977.1155734","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155734","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155641
R. Van Tuyl, C. Liechti, Robert Lee, E. Gowen
{"title":"4-GHz frequency division with GaAs MESFET ICs","authors":"R. Van Tuyl, C. Liechti, Robert Lee, E. Gowen","doi":"10.1109/ISSCC.1977.1155641","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155641","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：