Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155718
C. Séquin, M. Tompsett, D. Sealer, P. Suciu, P. Ryan
A SELF-CONTAINED charge-coupled 55-tap split-electrode filter will be described in this paper. The major problem that had to be solved was that of transforming the signal from the sense electrodes into a usable output signal with a large dynamic range and a minimal harmonic distortion. The factors that must be considered in formulating a solution to this problem are: (1) eliminating the effects of depletion capacitance, (2) detecting a difference signal in the presence of a large common mode signal and (3) preventing reset noise in the detection circuitry. A practical method to avoid the effects of depletion capacitance under the split sense electrodes is to keep these electrodes at a fixed potential during the sensing process by using a feedback loop around an operational amplifier as indicated in Figure 1. This sensing circuitry is optimally used in conjunction with a voltage input to the charge transfer channel, where the charge packets are metered under an MOS electrode, (MW), the geometry of which is the same as that of the sense electrodes, and which is also kept at the same potential VSE; Figure 1. The overall transfer characteristic from the voltage applied to the input diode, (and thus the interface potential in the metering well MW) to the amount of image charge produced on the sense electrodes (and hence the output voltage V O ~ T ) can then be expected to be linear. Various possible ways to clamp the sense electrodes to a given potential and to extract the desired output signal have been discussed earlier’’2. A novel approach to extract this difference signal in the presence of the considerably larger common mode signal is shown in Figure 2. One amplifier (AD) performs the differencing operation, while the other amplifier ( Ac) is used to suppress the common mode signal on the two sense busses. AC operates by comparing the arithmetic mean of the sense electrode potentials to the sense voltage reference VSE and feeds back the same error signal to both sense busses through capacitors CCt and Cc. The feedback signal around AD through CDwll maintain the balance between the two sense busses, and the combined
本文将介绍一种独立的电荷耦合55分接分电极滤波器。必须解决的主要问题是如何将来自传感电极的信号转换成具有大动态范围和最小谐波失真的可用输出信号。在制定这个问题的解决方案时必须考虑的因素是:(1)消除耗尽电容的影响;(2)在存在大共模信号时检测差分信号;(3)防止检测电路中的复位噪声。避免分裂感测电极下耗尽电容影响的一种实用方法是在感测过程中，通过在运算放大器周围使用反馈回路，使这些电极保持在固定电位，如图1所示。该传感电路最佳地与电荷转移通道的电压输入结合使用，其中电荷包在MOS电极下测量，(MW)，其几何形状与传感电极相同，并且也保持在相同的电位VSE;图1所示。从施加到输入二极管的电压(因此计量井中的界面电位为MW)到在感测电极上产生的图像电荷量(因此输出电压为V O ~ T)的总体转移特性可以预期为线性。各种可能的方法钳位感测电极到一个给定的电位，并提取所需的输出信号已在前面讨论过。图2显示了一种在较大的共模信号存在的情况下提取这种差分信号的新方法。一个放大器(AD)执行差分操作，而另一个放大器(Ac)用于抑制两个检测总线上的共模信号。AC的工作原理是将检测电极电位的算术平均值与检测电压参考VSE进行比较，并通过电容CCt和Cc将相同的误差信号反馈给两个检测母线，AD周围的反馈信号通过cdd保持两个检测母线之间的平衡，并结合起来
{"title":"Sensing technique for self-contained charge-coupled split-electrode filters","authors":"C. Séquin, M. Tompsett, D. Sealer, P. Suciu, P. Ryan","doi":"10.1109/ISSCC.1977.1155718","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155718","url":null,"abstract":"A SELF-CONTAINED charge-coupled 55-tap split-electrode filter will be described in this paper. The major problem that had to be solved was that of transforming the signal from the sense electrodes into a usable output signal with a large dynamic range and a minimal harmonic distortion. The factors that must be considered in formulating a solution to this problem are: (1) eliminating the effects of depletion capacitance, (2) detecting a difference signal in the presence of a large common mode signal and (3) preventing reset noise in the detection circuitry. A practical method to avoid the effects of depletion capacitance under the split sense electrodes is to keep these electrodes at a fixed potential during the sensing process by using a feedback loop around an operational amplifier as indicated in Figure 1. This sensing circuitry is optimally used in conjunction with a voltage input to the charge transfer channel, where the charge packets are metered under an MOS electrode, (MW), the geometry of which is the same as that of the sense electrodes, and which is also kept at the same potential VSE; Figure 1. The overall transfer characteristic from the voltage applied to the input diode, (and thus the interface potential in the metering well MW) to the amount of image charge produced on the sense electrodes (and hence the output voltage V O ~ T ) can then be expected to be linear. Various possible ways to clamp the sense electrodes to a given potential and to extract the desired output signal have been discussed earlier’’2. A novel approach to extract this difference signal in the presence of the considerably larger common mode signal is shown in Figure 2. One amplifier (AD) performs the differencing operation, while the other amplifier ( Ac) is used to suppress the common mode signal on the two sense busses. AC operates by comparing the arithmetic mean of the sense electrode potentials to the sense voltage reference VSE and feeds back the same error signal to both sense busses through capacitors CCt and Cc. The feedback signal around AD through CDwll maintain the balance between the two sense busses, and the combined","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155729
L. Terman, W. Kosonocky
{"title":"Semiconductor RAMs: Limits to growth","authors":"L. Terman, W. Kosonocky","doi":"10.1109/ISSCC.1977.1155729","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155729","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155647
H. Yamada, M. Katakura
LEVEL COMPRESSION-EXPANSION systems (compandors), are widely used for reducing noise in signal transmission’ 3 2 . However, the IC realization of the log linear transformation system has been considered difficult due to the requirement for high performance PNP transistors in these circuits. A system which incorporates an equivalent PNP transistor with high performance characteristics will be described.
{"title":"A monolithic IC for decibel-linear noise reduction","authors":"H. Yamada, M. Katakura","doi":"10.1109/ISSCC.1977.1155647","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155647","url":null,"abstract":"LEVEL COMPRESSION-EXPANSION systems (compandors), are widely used for reducing noise in signal transmission’ 3 2 . However, the IC realization of the log linear transformation system has been considered difficult due to the requirement for high performance PNP transistors in these circuits. A system which incorporates an equivalent PNP transistor with high performance characteristics will be described.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121661394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155668
J. Schoeff
COMPANDED PULSE CODE MODULATED (PCM) transmission of voice signals has become standardized through widespread use of the Bell system p-law and the CCITT** A-law transfer characteristics. Until now, all codecs (eoder/decoders) for these communication systems have been fabricated in either discrete or hybrid form and have been relatively expensive. This paper will present a newly developed monolithic digital-to-analog converter specifically designed for compression and expansion of signals according to the existing PCM standard. This converter, however, is not limited to PCM communication, but may be used in other areas such as data acquisition, servo controls, data recording, telemetry, voice synthesis, log attenuation, secure communications, sonar, and many other applications which require a 12-bit plus sign dynamic range and the convenience of an 8-bit digital code. When used in a telecommunications application, the companding DAC is a complete PCM decoder, with metal options for p-law and A-law. A one-half step decision level for encoding is provided within the circuit and controlled with the encode/decode logic input. This current offsets the entire transfer characteristic one half step, regardless of the value of the output current. The outputs are multiplexed for time sharing of one DAC for both encode and decode operation. The DAC settling time is 500 ns, and i t will decode more than 32 PCM channels in 125 ps, which is the sampling period at 8 kHz. In a shared encoder it will convert eight channels, assuming a 1 0 ps sample and hold acquisition time. The outputs are high impedance, high compliance current sources and will interface with most balanced loads. The reference inputs will accept a fixed reference or a positive or negative multiplying input. The transfer characteristic of the companding DAC is shown in Figure 1. The output consists of eight positive chords and eight negative chords, each containing sixteen steps. The slopes of these chords are binarily related with the chord at the origin having steps equivalent in size to those in a 12-bit converter. The step size is a nearly constant 3.2% of reading throughout most of the dynamic range, which corresponds to approximately 0.3 dB per step. Each successive chord endpoint is 6 dB below the next higher endpoint for every chord in the A-law specification, and follows this for most chords in the p-law. The dynamic range, or ratio, of the full scale to the smallest step size is 72 dB for the p-law version and 66 dB for the A-law unit. The electrical specifications for the circuit are summarized in Table I.
通过广泛使用贝尔系统p-定律和CCITT** a -定律传输特性，压缩脉冲码调制(PCM)语音信号的传输已经标准化。到目前为止，用于这些通信系统的所有编解码器(编码器/解码器)都是以分立或混合形式制造的，并且相对昂贵。本文将介绍一种新开发的单片数模转换器，根据现有的PCM标准专门设计用于信号的压缩和扩展。然而，该转换器不仅限于PCM通信，还可用于其他领域，如数据采集，伺服控制，数据记录，遥测，语音合成，日志衰减，安全通信，声纳以及许多其他需要12位加号动态范围和8位数字代码的便利的应用。当用于电信应用时，扩展DAC是一个完整的PCM解码器，具有p律和a律金属选项。电路内提供用于编码的半步决策电平，并由编码/解码逻辑输入控制。无论输出电流的值是多少，该电流都会将整个传输特性偏移半步。输出多路复用，用于一个DAC的时间共享，用于编码和解码操作。DAC的建立时间为500ns，它将以125ps的速度解码超过32个PCM通道，这是8 kHz的采样周期。在共享编码器中，它将转换8个通道，假设10ps采样并保持采集时间。输出是高阻抗，高顺应电流源，并将与大多数平衡负载接口。参考输入将接受固定参考或正或负相乘输入。扩展DAC的传输特性如图1所示。输出由8个正和弦和8个负和弦组成，每个和弦包含16步。这些和弦的斜率与原点的和弦有二元关系，其步长与12位转换器中的步长相当。在大部分动态范围内，步长几乎是读数的3.2%，相当于每步约0.3 dB。在a律中，每个连续的和弦端点比下一个更高的端点低6db，在p律中，大多数和弦都遵循这一原则。满量程到最小步长的动态范围或比率，对于p律单元为72 dB，对于a律单元为66 dB。电路的电气规格概述在表1中。
{"title":"A monolithic companding D/A converter","authors":"J. Schoeff","doi":"10.1109/ISSCC.1977.1155668","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155668","url":null,"abstract":"COMPANDED PULSE CODE MODULATED (PCM) transmission of voice signals has become standardized through widespread use of the Bell system p-law and the CCITT** A-law transfer characteristics. Until now, all codecs (eoder/decoders) for these communication systems have been fabricated in either discrete or hybrid form and have been relatively expensive. This paper will present a newly developed monolithic digital-to-analog converter specifically designed for compression and expansion of signals according to the existing PCM standard. This converter, however, is not limited to PCM communication, but may be used in other areas such as data acquisition, servo controls, data recording, telemetry, voice synthesis, log attenuation, secure communications, sonar, and many other applications which require a 12-bit plus sign dynamic range and the convenience of an 8-bit digital code. When used in a telecommunications application, the companding DAC is a complete PCM decoder, with metal options for p-law and A-law. A one-half step decision level for encoding is provided within the circuit and controlled with the encode/decode logic input. This current offsets the entire transfer characteristic one half step, regardless of the value of the output current. The outputs are multiplexed for time sharing of one DAC for both encode and decode operation. The DAC settling time is 500 ns, and i t will decode more than 32 PCM channels in 125 ps, which is the sampling period at 8 kHz. In a shared encoder it will convert eight channels, assuming a 1 0 ps sample and hold acquisition time. The outputs are high impedance, high compliance current sources and will interface with most balanced loads. The reference inputs will accept a fixed reference or a positive or negative multiplying input. The transfer characteristic of the companding DAC is shown in Figure 1. The output consists of eight positive chords and eight negative chords, each containing sixteen steps. The slopes of these chords are binarily related with the chord at the origin having steps equivalent in size to those in a 12-bit converter. The step size is a nearly constant 3.2% of reading throughout most of the dynamic range, which corresponds to approximately 0.3 dB per step. Each successive chord endpoint is 6 dB below the next higher endpoint for every chord in the A-law specification, and follows this for most chords in the p-law. The dynamic range, or ratio, of the full scale to the smallest step size is 72 dB for the p-law version and 66 dB for the A-law unit. The electrical specifications for the circuit are summarized in Table I.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155715
N. Tsuzuki, Y. Saito, T. Sakai
A HIGH-POWER three-stage transistor amplifier utilizing a bipolar transistor, which can deliver 12W output power at 4 GHz, will be described. The amplifier, exhibiting power gain of l l l3dB, power added efficiency of 17%, and can operate with a 20-V dc power supply, contains seven units of a 3-W bipolar transistor, fabricated with self-aligned electrode formation technology’. Figure 1 shows the block diagram of the amplifier circuit. Each transistor amplifier segment contains input and output matching networks of the microstripline type, and is connected to the power combiner/divider of a double section 3dB quarter wavelength hybrid. Teflon glass-fiber substrates have been used for the matching networks and for the hybrid couplers. In Figures 2 (a) and (b) RF performance characteristics i.e., output power, efficiency and AM-PM conversion coefficient versus input power, and output power versus frequency characteristics at different ambient temperatures are shown. The noise loading characteristics are also satisfactory.
{"title":"A 4-GHz 12-W transistor amplifier utilizing a self-aligned bipolar structure","authors":"N. Tsuzuki, Y. Saito, T. Sakai","doi":"10.1109/ISSCC.1977.1155715","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155715","url":null,"abstract":"A HIGH-POWER three-stage transistor amplifier utilizing a bipolar transistor, which can deliver 12W output power at 4 GHz, will be described. The amplifier, exhibiting power gain of l l l3dB, power added efficiency of 17%, and can operate with a 20-V dc power supply, contains seven units of a 3-W bipolar transistor, fabricated with self-aligned electrode formation technology’. Figure 1 shows the block diagram of the amplifier circuit. Each transistor amplifier segment contains input and output matching networks of the microstripline type, and is connected to the power combiner/divider of a double section 3dB quarter wavelength hybrid. Teflon glass-fiber substrates have been used for the matching networks and for the hybrid couplers. In Figures 2 (a) and (b) RF performance characteristics i.e., output power, efficiency and AM-PM conversion coefficient versus input power, and output power versus frequency characteristics at different ambient temperatures are shown. The noise loading characteristics are also satisfactory.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133702015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155634
G. Louie, J. Wipfli, A. Ebright
{"title":"A dual processor serial data controller chip","authors":"G. Louie, J. Wipfli, A. Ebright","doi":"10.1109/ISSCC.1977.1155634","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155634","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134197068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155651
R. Muller, H. Nietsch, B. Rossler, E. Wolter
THERE HAS BEEN an increasing interest in recent years in an electrically erasable MOS PROM employing the excellent information retention of the floating gate principle’. Several proposals for N-channel EAROMs are known’ >3. This paper will describe an 8192-bit N-channel EAROM featuring: a ) single transistor cell, b) standard operating voltages and single high voltage pulse for programming and erasure, c), 24-pin package, d) input/output TTL compatible for read and programming, e ) static, no clock required, and fl low standby power.
{"title":"Electrically alterable 8192 bit N-channel MOS PROM","authors":"R. Muller, H. Nietsch, B. Rossler, E. Wolter","doi":"10.1109/ISSCC.1977.1155651","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155651","url":null,"abstract":"THERE HAS BEEN an increasing interest in recent years in an electrically erasable MOS PROM employing the excellent information retention of the floating gate principle’. Several proposals for N-channel EAROMs are known’ >3. This paper will describe an 8192-bit N-channel EAROM featuring: a ) single transistor cell, b) standard operating voltages and single high voltage pulse for programming and erasure, c), 24-pin package, d) input/output TTL compatible for read and programming, e ) static, no clock required, and fl low standby power.","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"28 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132828044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISSCC.1977.1155641
R. Van Tuyl, C. Liechti, Robert Lee, E. Gowen
{"title":"4-GHz frequency division with GaAs MESFET ICs","authors":"R. Van Tuyl, C. Liechti, Robert Lee, E. Gowen","doi":"10.1109/ISSCC.1977.1155641","DOIUrl":"https://doi.org/10.1109/ISSCC.1977.1155641","url":null,"abstract":"","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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