Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992946
R. Farjad-Rad, W. Dally, Hoik-Tiaq Ng, J. Poulton, T. Stone, R. Rathi, E. Lee, D. Huang, R. Nathan
The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.
{"title":"A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips","authors":"R. Farjad-Rad, W. Dally, Hoik-Tiaq Ng, J. Poulton, T. Stone, R. Rathi, E. Lee, D. Huang, R. Nathan","doi":"10.1109/ISSCC.2002.992946","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992946","url":null,"abstract":"The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992998
Yeonwoo Ku, Y. Eo, K. Lee
This presentation shows the feasibility of integrating a reference oscillator on CMOS circuits, using digitally temperature-compensated SAW oscillator and Polylithic IC technology on a quartz-on-silicon wafer. The oscillator shows -115 dBc/Hz phase noise at 10 kHz offset, 7.5 mW power consumption, and 4.5 ppm frequency stability.
{"title":"Polylithic integration of a reference SAW quartz-on-silicon oscillator for single-chip radio","authors":"Yeonwoo Ku, Y. Eo, K. Lee","doi":"10.1109/ISSCC.2002.992998","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992998","url":null,"abstract":"This presentation shows the feasibility of integrating a reference oscillator on CMOS circuits, using digitally temperature-compensated SAW oscillator and Polylithic IC technology on a quartz-on-silicon wafer. The oscillator shows -115 dBc/Hz phase noise at 10 kHz offset, 7.5 mW power consumption, and 4.5 ppm frequency stability.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"47 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123268848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992956
T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, K. Washio
A single-chip 5.8 GHz ETC transceiver IC with PLL and demodulator uses SiGe HBT/CMOS. The fully integrated ETC chip includes a 31 dB-gain RX stage, an ASK demodulator, and a high-precision RSSI. The PLL is constructed with a varactor-tuned LC-VCO and a low-power BiCMOS synthesizer. The TX stage incorporates a transformer-transferred single-ended PA.
{"title":"Single-chip 5.8 GHz ETC transceiver IC with PLL and demodulation circuits using SiGe HBT/CMOS","authors":"T. Masuda, K. Ohhata, N. Shiramizu, S. Hanazawa, M. Kudoh, Y. Tanba, Y. Takeuchi, H. Shimamoto, T. Nagashima, K. Washio","doi":"10.1109/ISSCC.2002.992956","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992956","url":null,"abstract":"A single-chip 5.8 GHz ETC transceiver IC with PLL and demodulator uses SiGe HBT/CMOS. The fully integrated ETC chip includes a 31 dB-gain RX stage, an ASK demodulator, and a high-precision RSSI. The PLL is constructed with a varactor-tuned LC-VCO and a low-power BiCMOS synthesizer. The TX stage incorporates a transformer-transferred single-ended PA.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992996
M. Takamiya, M. Mizuno, K. Nakamura
An on-chip 8-channel sampling oscilloscope macro for signal integrity checking uses a 0.13 /spl mu/m CMOS process. It contains a phase-interpolated sampling clock generator for 100GHz sampling, charge-sharing sampling heads, and ESD-tolerant decoupling capacitors for noise-immune measurement.
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993005
J. Rabaey, J. Ammer, T. Karalar, Suet-Fei Li, B. Otis, M. Sheets, Tim Tuan
An untapped opportunity in the realm of wireless data lies in low data-rate (<10 kb/s) low-cost wireless transceivers, assembled into distributed networks of sensor and actuator nodes. This enables applications such as smart buildings and highways, environment monitoring, user interfaces, entertainment, factory automation, and robotics While the aggregate system processes large amounts of data, individual nodes participate in a small fraction only (typical data rates <1 kb/s). These ubiquitous networks require that the individual nodes are tiny, easily integratable into the environment, and have negligible cost. The challenges and opportunities in the design of integrated wireless sensor and actuator nodes, to be used in such self-configuring ad-hoc networks, are described. To be viable, the node must be smaller than a couple of mm/sup 3/, cost <$1, and consume <100 μW, allowing for energy scavenging from the environment.
{"title":"PicoRadios for wireless sensor networks: the next challenge in ultra-low power design","authors":"J. Rabaey, J. Ammer, T. Karalar, Suet-Fei Li, B. Otis, M. Sheets, Tim Tuan","doi":"10.1109/ISSCC.2002.993005","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993005","url":null,"abstract":"An untapped opportunity in the realm of wireless data lies in low data-rate (<10 kb/s) low-cost wireless transceivers, assembled into distributed networks of sensor and actuator nodes. This enables applications such as smart buildings and highways, environment monitoring, user interfaces, entertainment, factory automation, and robotics While the aggregate system processes large amounts of data, individual nodes participate in a small fraction only (typical data rates <1 kb/s). These ubiquitous networks require that the individual nodes are tiny, easily integratable into the environment, and have negligible cost. The challenges and opportunities in the design of integrated wireless sensor and actuator nodes, to be used in such self-configuring ad-hoc networks, are described. To be viable, the node must be smaller than a couple of mm/sup 3/, cost <$1, and consume <100 μW, allowing for energy scavenging from the environment.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134289483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992267
S. U, R. Martins, J. Franca
A 57 MHz SC bandpass interpolating filter with 320 Msample/s output is realized in 0.35 /spl mu/m CMOS for DDFS (direct-digital frequency synthesis) systems. 15-tap FIR response is achieved with sampling rate increase and frequency upconversion by translating 22 MHz 80 Msample/s input to 56 MHz 320 Msample/s output. Dynamic range is 69 dB (1%THD) and 61 dB (1%IM3). The filter dissipates 120 mW analog and 16 mW digital at 2.5 V supply.
在0.35 /spl mu/m CMOS上实现了用于DDFS(直接数字频率合成)系统的57mhz SC带通插值滤波器，输出320msample /s。通过将22 MHz 80 Msample/s的输入转换为56 MHz 320 Msample/s的输出，可以提高采样率并实现频率上变频，从而实现15抽头FIR响应。动态范围为69 dB (1%THD)和61 dB (1%IM3)。该滤波器在2.5 V电源下耗散120兆瓦模拟功率和16兆瓦数字功率。
{"title":"A 2.5 V 57 MHz 15-tap SC bandpass interpolating filter with 320 MHz output sampling rate in 0.35 /spl mu/m CMOS","authors":"S. U, R. Martins, J. Franca","doi":"10.1109/ISSCC.2002.992267","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992267","url":null,"abstract":"A 57 MHz SC bandpass interpolating filter with 320 Msample/s output is realized in 0.35 /spl mu/m CMOS for DDFS (direct-digital frequency synthesis) systems. 15-tap FIR response is achieved with sampling rate increase and frequency upconversion by translating 22 MHz 80 Msample/s input to 56 MHz 320 Msample/s output. Dynamic range is 69 dB (1%THD) and 61 dB (1%IM3). The filter dissipates 120 mW analog and 16 mW digital at 2.5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992292
T. Sugiyama, S. Yoshimura, R. Suzuki, H. Sumi
A 320/spl times/240 color imaging CMOS sensor with a current-copier cell array and comparators for column-parallel processing accomplishes video rate depth acquisition. The sensor dissipates 82 mW for 3.3kframe/s 3-D sensing with 2.5 mm depth resolution, and 36 mW for 30frames/s imaging with a single CDS circuit for FPN reduction at 3.3 V.
{"title":"A 1/4-inch QVGA color imaging and 3-D sensing CMOS sensor with analog frame memory","authors":"T. Sugiyama, S. Yoshimura, R. Suzuki, H. Sumi","doi":"10.1109/ISSCC.2002.992292","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992292","url":null,"abstract":"A 320/spl times/240 color imaging CMOS sensor with a current-copier cell array and comparators for column-parallel processing accomplishes video rate depth acquisition. The sensor dissipates 82 mW for 3.3kframe/s 3-D sensing with 2.5 mm depth resolution, and 36 mW for 30frames/s imaging with a single CDS circuit for FPN reduction at 3.3 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132280401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992162
P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, A. Mulé
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.
{"title":"The clock distribution of the Power4 microprocessor","authors":"P. Restle, C. Carter, J. Eckhardt, B. Krauter, B. McCredie, K. Jenkins, A. Weger, A. Mulé","doi":"10.1109/ISSCC.2002.992162","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992162","url":null,"abstract":"The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132591283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993086
T. Yamada, N. Irie, J. Nishimoto, Y. Kondoh, T. Nakazawa, K. Yamada, K. Tatezawa, T. Irita, S. Tamaki, H. Yagi, M. Furuyama, K. Ogura, H. Watanabe, R. Satomura, K. Hirose, F. Arakawa, T. Hattori, I. Kudo, I. Kawasaki, K. Uchiyama
An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.
{"title":"A 133 MHz 170 mW 10 /spl mu/A standby application processor for 3G cellular phones","authors":"T. Yamada, N. Irie, J. Nishimoto, Y. Kondoh, T. Nakazawa, K. Yamada, K. Tatezawa, T. Irita, S. Tamaki, H. Yagi, M. Furuyama, K. Ogura, H. Watanabe, R. Satomura, K. Hirose, F. Arakawa, T. Hattori, I. Kudo, I. Kawasaki, K. Uchiyama","doi":"10.1109/ISSCC.2002.993086","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993086","url":null,"abstract":"An application processor for 3G cellular phones, using 0.18 /spl mu/m CMOS technology, includes a single CPU and DSP core with an on-chip 128 kB SRAM. It enables software-based 15 frames/s MPEG-4 encoding of QCIF Simple @L1 at 70 MHz and 140 mW. Standby current of the processor is <10 /spl mu/A in a partially powered standby mode using separate power lines.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992935
A. Olofsson, F. Lange
The authors present a 6 GOPS DSP which implements the TigerSharc architecture with an instruction set enhanced for wireless communication. It is implemented in a 0.13 μm CMOS process with 8 layers of copper interconnect and operates at 250 MHz with 1 W power dissipation under nominal conditions.
{"title":"A 4.32 GOPS 1 W general-purpose DSP with an enhanced instruction set for wireless communication","authors":"A. Olofsson, F. Lange","doi":"10.1109/ISSCC.2002.992935","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992935","url":null,"abstract":"The authors present a 6 GOPS DSP which implements the TigerSharc architecture with an instruction set enhanced for wireless communication. It is implemented in a 0.13 μm CMOS process with 8 layers of copper interconnect and operates at 250 MHz with 1 W power dissipation under nominal conditions.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134175192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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