Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993095
P. Blanken, S. Menten
A chopped 4/sup th-/order continuous-time 1 bit /spl Sigma//spl Delta/ A/D converter with 10 /spl mu/V offset and 8 kHz bandwidth has been designed for battery current measurement. Chopping at 16 kHz, the circuit has a 0.1 V input range, a 68 dB SNR, and a 1 MHz output bit rate. Area is 0.45x0.4 mm in 0.35 /spl mu/m CMOS. Current consumption is 30 /spl mu/A at 2.5-4 V.
{"title":"A 10 /spl mu/V-offset 8 kHz bandwidth 4/sup th/-order chopped /spl Sigma//spl Delta/ A/D converter for battery management","authors":"P. Blanken, S. Menten","doi":"10.1109/ISSCC.2002.993095","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993095","url":null,"abstract":"A chopped 4/sup th-/order continuous-time 1 bit /spl Sigma//spl Delta/ A/D converter with 10 /spl mu/V offset and 8 kHz bandwidth has been designed for battery current measurement. Chopping at 16 kHz, the circuit has a 0.1 V input range, a 68 dB SNR, and a 1 MHz output bit rate. Area is 0.45x0.4 mm in 0.35 /spl mu/m CMOS. Current consumption is 30 /spl mu/A at 2.5-4 V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129825798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992932
J. Hurwitz, M. Panaghiston, K. Findlater, R. Henderson, T. Bailey, A. Holmes, B. Paisley
A 5 V 1120×1808 pixel 35 mm film format CMOS image sensor for camera-back use, fabricated in 0.5 μm 2-poly 3-metal (2P3M) technology, includes integrated light-detection circuitry using non-destructive pixel read and consumes <50 μW. Reticle stitching is employed for the large format. Dynamic range is 66 dB and peak SNR is 55 dB.
采用0.5 μm 2-聚金属(2P3M)技术制造的5 V 1120×1808像素35 mm胶片格式CMOS后置图像传感器，包括采用非破坏性像素读取的集成光检测电路，功耗<50 μW。大幅面采用十字线拼接。动态范围为66 dB，峰值信噪比为55 dB。
{"title":"A 35 mm film format CMOS image sensor for camera-back applications","authors":"J. Hurwitz, M. Panaghiston, K. Findlater, R. Henderson, T. Bailey, A. Holmes, B. Paisley","doi":"10.1109/ISSCC.2002.992932","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992932","url":null,"abstract":"A 5 V 1120×1808 pixel 35 mm film format CMOS image sensor for camera-back use, fabricated in 0.5 μm 2-poly 3-metal (2P3M) technology, includes integrated light-detection circuitry using non-destructive pixel read and consumes <50 μW. Reticle stitching is employed for the large format. Dynamic range is 66 dB and peak SNR is 55 dB.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992963
D. Bradley, P. Mahoney, B. Stackhouse
A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.
{"title":"The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor","authors":"D. Bradley, P. Mahoney, B. Stackhouse","doi":"10.1109/ISSCC.2002.992963","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992963","url":null,"abstract":"A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129045018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992213
Jun Cao, A. Momtaz, K. Vakilian, M.M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, A. Hairapetian
A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.
{"title":"OC-192 receiver in standard 0.18/spl mu/m CMOS","authors":"Jun Cao, A. Momtaz, K. Vakilian, M.M. Green, D. Chung, K. Jen, M. Caresosa, B. Tan, I. Fujimori, A. Hairapetian","doi":"10.1109/ISSCC.2002.992213","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992213","url":null,"abstract":"A fully integrated OC-192 multi-rate (9.95Gb/s-10.71Gb/s) receiver uses standard 0.18/spl mu/m CMOS. The circuit consists of an input amplifier, CDR, 1:16 demux and 18 LVDS drivers. The chip exceeds SONET jitter tolerance spec by >100%. Recovered 10Gb/s clock jitter is <4mUl(rms). The input sensitivity is <50mV with 870mW at 1.8V.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129203376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992096
M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih
A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.
{"title":"A packet-memory-integrated 44 Gb/s switching processor with a 10 Gb port and 12 Gb ports","authors":"M. Lau, S. Shieh, Pei-Feng Wang, B. Smith, Min-Shueh Yuan, D. Lee, J. Gaba, J. Chao, B. Shung, C. Shih","doi":"10.1109/ISSCC.2002.992096","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992096","url":null,"abstract":"A 44 Gb/s switching processor chip has 1 MB embedded packet memory. With a 10 Gb and 12 1 Gb ports, this chip is useful for LAN/WAN bridging applications. Wire-speed switching performance is demonstrated using a shared buffer switching architecture. This 0.18 μm CMOS processor integrates a 10 Gb port with an XGMII interface.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127359314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993109
N. Tzartzanis, W. Walker, H. Nguyen, A. Inoue
A register file leverages from a replica-based control unit to improve reliability, operate in a wide voltage range, and support two supply voltages. The main power supply can be stepped down to reduce power, or shut off for sleep mode. Access time is 1.4 ns and power dissipation is 220 mW at 500 MHz in 1.2 V, 0.11 /spl mu/m CMOS.
{"title":"A 34 word/spl times/64 b 10 R/6 W write-through self timed dual-supply-voltage register file","authors":"N. Tzartzanis, W. Walker, H. Nguyen, A. Inoue","doi":"10.1109/ISSCC.2002.993109","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993109","url":null,"abstract":"A register file leverages from a replica-based control unit to improve reliability, operate in a wide voltage range, and support two supply voltages. The main power supply can be stepped down to reduce power, or shut off for sleep mode. Access time is 1.4 ns and power dissipation is 220 mW at 500 MHz in 1.2 V, 0.11 /spl mu/m CMOS.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115819411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992929
T. Miida, K. Kawajiri, H. Terakago, T. Endo, T. Okazaki, S. Yamamoto, A. Nishimura
A 1.5 Mpixel imager with 4.2 /spl mu/m square pixel is composed of a single MOSFET and a pinned photodiode. A localized high-density p-region near the source of the MOSFET converts the accumulated hole number to source voltage. Low random noise, low dark signal, high sensitivity with good color reproduction and resolution are achieved.
{"title":"A 1.5 Mpixel imager with localized hole-modulation method","authors":"T. Miida, K. Kawajiri, H. Terakago, T. Endo, T. Okazaki, S. Yamamoto, A. Nishimura","doi":"10.1109/ISSCC.2002.992929","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992929","url":null,"abstract":"A 1.5 Mpixel imager with 4.2 /spl mu/m square pixel is composed of a single MOSFET and a pinned photodiode. A localized high-density p-region near the source of the MOSFET converts the accumulated hole number to source voltage. Low random noise, low dark signal, high sensitivity with good color reproduction and resolution are achieved.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126971085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.992243
M. Ingels, S. Bojja, P. Wouters
A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.
{"title":"A 0.5/spl mu/m CMOS low-distortion low-power line driver with embedded digital adaptive bias algorithm for integrated ADSL analog front-ends","authors":"M. Ingels, S. Bojja, P. Wouters","doi":"10.1109/ISSCC.2002.992243","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.992243","url":null,"abstract":"A 5V 0.5/spl mu/m CMOS line driver has distortion <-65dB in the ADSL upstream band for a 4V peak-to-peak differential output swing on a 12.5/spl Omega/ load. The quiescent current is controlled digitally with a dedicated algorithm that corrects for offsets and process variations. The driver is integrated in a complete ADSL CPE analog front-end.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126849388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993099
M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland
A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.
一个0.25 /spl mu/m CMOS正交复杂带通低中频GPS接收机包括一个LNA、锁相环、混频器和一个连续时间/spl Delta//spl Sigma/ ADC。该芯片具有-130 dBm的输入灵敏度，62 dB DR和-32 dB IMRR，同时从2v电源消耗40 mW。芯片是9毫米/sup 2/。
{"title":"A fully-integrated GPS receiver front-end with 40 mW power consumption","authors":"M. Steyaert, P. Coppejans, W. De Cock, P. Leroux, P. Vancorenland","doi":"10.1109/ISSCC.2002.993099","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993099","url":null,"abstract":"A 0.25 /spl mu/m CMOS quadrature complex bandpass low-IF GPS receiver includes an LNA, PLL, mixer and a continuous-time /spl Delta//spl Sigma/ ADC. The chip has -130 dBm input sensitivity, 62 dB DR, and -32 dB IMRR, while consuming 40 mW from 2 V supply. The chip is 9 mm/sup 2/.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124551337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISSCC.2002.993101
L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell
A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.
{"title":"A CMOS broadband tuner IC","authors":"L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R. Cieslak, J. Caldwell","doi":"10.1109/ISSCC.2002.993101","DOIUrl":"https://doi.org/10.1109/ISSCC.2002.993101","url":null,"abstract":"A single-chip dual-conversion tuner in 0.35 /spl mu/m CMOS incorporates both a 50-860 MHz LNA and a digital CMOS synthesizer with a -173 dBc/Hz phase-noise floor. The synthesizer generates 100 mA switching currents at a 12.5 MHz rate and all associated in-band spurs are suppressed <0.5 /spl mu/Vrms input referred. The 5 mm/sup 2/ die consumes 1.5 W from a 5 V supply.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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