Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242273
D. Ueda, K. Takeuchi, M. Kobayashi, T. Hiramoto
In this paper, a new modeling approach for understanding and designing a recently proposed steep subthreshold slope SOI transistor (i.e. PN-Body Tied SOI FET [1-3]) is proposed. We revealed that the abrupt switching operation can be modeled using a simple equivalent circuit comprising two cross-coupled voltage inverters (i.e. electron current and hole current inverters). The model will be useful for designing PNBTFETs with optimum transition voltage, small hysteresis, and low standby current.
本文提出了一种新的建模方法来理解和设计最近提出的陡坡亚阈值SOI晶体管(即PN-Body Tied SOI FET[1-3])。我们发现，突然开关操作可以用一个简单的等效电路来模拟，该电路包括两个交叉耦合电压逆变器(即电子电流和空穴电流逆变器)。该模型将有助于设计具有最佳过渡电压、小迟滞和低待机电流的pnbtfet。
{"title":"Carrier-separated equivalent circuit modeling for steep subthreshold slope PN-body tied SOI FET","authors":"D. Ueda, K. Takeuchi, M. Kobayashi, T. Hiramoto","doi":"10.23919/SNW.2017.8242273","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242273","url":null,"abstract":"In this paper, a new modeling approach for understanding and designing a recently proposed steep subthreshold slope SOI transistor (i.e. PN-Body Tied SOI FET [1-3]) is proposed. We revealed that the abrupt switching operation can be modeled using a simple equivalent circuit comprising two cross-coupled voltage inverters (i.e. electron current and hole current inverters). The model will be useful for designing PNBTFETs with optimum transition voltage, small hysteresis, and low standby current.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124155235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242307
S. Bang, Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Dong Keun Lee, Byung-Gook Park
In this paper, we have simulated how the overshoot current in the Resistive-switching Random Access Memory (RRAM) cell is generated and whether the integrated transistor can effectively suppress the overshoot current that can cause degradation of cell endurance. We propose a CMOS-friendly 1T1R fabrication process and proceed with circuit simulation using the process parameters. The simulation shows that the internal transistor effectively prevent RRAM overshoot current and be capable of controlling the compliance current.
{"title":"Investigation on the RRAM overshoot current suppression with circuit simulation","authors":"S. Bang, Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Dong Keun Lee, Byung-Gook Park","doi":"10.23919/SNW.2017.8242307","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242307","url":null,"abstract":"In this paper, we have simulated how the overshoot current in the Resistive-switching Random Access Memory (RRAM) cell is generated and whether the integrated transistor can effectively suppress the overshoot current that can cause degradation of cell endurance. We propose a CMOS-friendly 1T1R fabrication process and proceed with circuit simulation using the process parameters. The simulation shows that the internal transistor effectively prevent RRAM overshoot current and be capable of controlling the compliance current.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129706150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242269
M. Muruganathan, D. Moraru, M. Tabe, H. Mizuta
We report for ultra-thin Si tunnelling diodes that negative differential conductance (NDC) is dominated by the excess current at room temperature. This is attributed to the gap-states induced by the co-dopants in the pn junction. First-principles simulation shows that the presence of co-dopants in the pn junction region leads to an increase in the interband tunnelling current by two orders of magnitude. Furthermore co-dopants interaction plays a key role in the interband tunnelling. In the absence of dopants states in the pn junction region, raising the doping concentration at source region does not give an appreciable improvement in tunnelling current.
{"title":"Co-dopants induced tunnel-current enhancement and their interaction in silicon nano tunnel diode","authors":"M. Muruganathan, D. Moraru, M. Tabe, H. Mizuta","doi":"10.23919/SNW.2017.8242269","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242269","url":null,"abstract":"We report for ultra-thin Si tunnelling diodes that negative differential conductance (NDC) is dominated by the excess current at room temperature. This is attributed to the gap-states induced by the co-dopants in the pn junction. First-principles simulation shows that the presence of co-dopants in the pn junction region leads to an increase in the interband tunnelling current by two orders of magnitude. Furthermore co-dopants interaction plays a key role in the interband tunnelling. In the absence of dopants states in the pn junction region, raising the doping concentration at source region does not give an appreciable improvement in tunnelling current.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129605744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242337
L. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Y. Niquet, X. Jehl, S. Barraud, C. Bäuerle, T. Meunier, M. Sanquer, S. de Franceschi, M. Vinet
We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.
{"title":"Harnessing Si CMOS technology for quantum information","authors":"L. Hutin, B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, H. Bohuslavskyi, L. Bourdet, Y. Niquet, X. Jehl, S. Barraud, C. Bäuerle, T. Meunier, M. Sanquer, S. de Franceschi, M. Vinet","doi":"10.23919/SNW.2017.8242337","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242337","url":null,"abstract":"We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121354581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242286
Hyungwoo Ko, Jongsu Kim, Dokyun Son, Myounggon Kang, Hyungcheol Shin
In this paper, the dual-k spacer of nanowire-FET is investigated using a variety of materials compared with single spacer. The proposed structure shows significant improvement of delay characteristics and better electrostatic controllability than those of single spacer.
{"title":"Improvement of dual-Λ spacer for nanowire-FETs considering circuit delay and electricstatic controllability","authors":"Hyungwoo Ko, Jongsu Kim, Dokyun Son, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242286","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242286","url":null,"abstract":"In this paper, the dual-k spacer of nanowire-FET is investigated using a variety of materials compared with single spacer. The proposed structure shows significant improvement of delay characteristics and better electrostatic controllability than those of single spacer.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242277
A. Fujiwara, K. Nishiguchi, G. Yamahata, K. Chida
Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential barriers electrically. In addition prominent stability and reproducibility of silicon MOSFETs are undoubted benefits for practical applications of such devices.
{"title":"Ultimate single electronics with silicon nanowire MOSFETs","authors":"A. Fujiwara, K. Nishiguchi, G. Yamahata, K. Chida","doi":"10.23919/SNW.2017.8242277","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242277","url":null,"abstract":"Scaling of silicon MOSFETs has been predicted to go around 10 nm and below. For such a small transistor a gate-all-around nanowire is regarded as an ideal geometry to maintain gate control. On the other hand, such downsizing and excellent gate control has provided opportunities to control individual electrons one by one by placing gates on top of the nanowire to define charge islands and potential barriers electrically. In addition prominent stability and reproducibility of silicon MOSFETs are undoubted benefits for practical applications of such devices.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133544399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242281
H. Firdaus, M. Hori, Y. Takahashi, A. Fujiwara, Y. Ono
Impact ionization [1,2], or electron-hole pair creation by charged particles, has been one of the central issues of semiconductor physics and devices. However, due to its complexity of the process, most experimental studies and their analyses have been macroscopic and phenomenological. This situation prevents us from exploring the fundamental physics of impact ionization and of high-energy charged particles in semiconductors.
{"title":"Sensitive detection of holes generated by impact ionization in silicon","authors":"H. Firdaus, M. Hori, Y. Takahashi, A. Fujiwara, Y. Ono","doi":"10.23919/SNW.2017.8242281","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242281","url":null,"abstract":"Impact ionization [1,2], or electron-hole pair creation by charged particles, has been one of the central issues of semiconductor physics and devices. However, due to its complexity of the process, most experimental studies and their analyses have been macroscopic and phenomenological. This situation prevents us from exploring the fundamental physics of impact ionization and of high-energy charged particles in semiconductors.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130446690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242305
Do-Bin Kim, D. Kwon, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park
In order to obtain high channel boosting potential and to reduce a program disturbance in channel stacked type with layer selection by multi-level operation (LSM), a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. To verify the validity of the new method in LSM, TCAD simulations are performed. Through TCAD simulation, it is revealed that the program disturbance characteristics is significantly improved by the proposed scheme.
{"title":"A boosted common source line program scheme in channel stacked NAND flash memory with layer selection by multilevel operation","authors":"Do-Bin Kim, D. Kwon, Seunghyun Kim, Sang-Ho Lee, Byung-Gook Park","doi":"10.23919/SNW.2017.8242305","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242305","url":null,"abstract":"In order to obtain high channel boosting potential and to reduce a program disturbance in channel stacked type with layer selection by multi-level operation (LSM), a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. To verify the validity of the new method in LSM, TCAD simulations are performed. Through TCAD simulation, it is revealed that the program disturbance characteristics is significantly improved by the proposed scheme.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116815743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242326
Feng-Renn Juang, C. Hsaio
Highly sensitive nanotree arrays are developed on silicon by combining wet etching and hydrothermal method. Due to the large surface-to-volume ratio, the device has relative sensitivity ratio of −82% to 100ppm ethanol gas under 150°C. The response and recovery times are also shortened significantly.
{"title":"Ethanol gas sensor with nanotree arrays by hydrothermal method and wet etching","authors":"Feng-Renn Juang, C. Hsaio","doi":"10.23919/SNW.2017.8242326","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242326","url":null,"abstract":"Highly sensitive nanotree arrays are developed on silicon by combining wet etching and hydrothermal method. Due to the large surface-to-volume ratio, the device has relative sensitivity ratio of −82% to 100ppm ethanol gas under 150°C. The response and recovery times are also shortened significantly.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134383368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.
{"title":"Analysis of metal gate work-function variation for vertical nanoplate FET in 6-T SRAMs","authors":"Kyul Ko, Dokyun Son, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242297","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242297","url":null,"abstract":"In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127668487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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