The scaling limits of supply voltage (Vdd) in stochastic computing are investigated based on foundry-level 16/14nm FinFET technology, considering inherent, static and transient variations. Circuit functionality, EDP, arithmetic error are examined, indicating that transient variation induced arithmetic bias is the dominating factor.
{"title":"Investigation on the Vdd scaling limit of stochastic computing circuits based on FinFET technology","authors":"Xiaobo Jiang, Runsheng Wang, Shaofeng Guo, Ru Huang","doi":"10.23919/SNW.2017.8242341","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242341","url":null,"abstract":"The scaling limits of supply voltage (Vdd) in stochastic computing are investigated based on foundry-level 16/14nm FinFET technology, considering inherent, static and transient variations. Circuit functionality, EDP, arithmetic error are examined, indicating that transient variation induced arithmetic bias is the dominating factor.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124514937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242303
Lei Shen, S. Di, L. Yin, Xiaoyan Liu, G. Du
As the device scaling down to sub-10nm, the quasi-ballistic transport becomes important. Some previous works have suggested using DD method to involve the quasi-ballistic transport effect through modifying the transport parameters. A procedure is introduced to calibrate the transport parameters of the DD model by using the simulation results of MC device simulator.
{"title":"Parameter calibration of drift-diffusion model in quasi-ballisitc transport region with Monte Carlo method","authors":"Lei Shen, S. Di, L. Yin, Xiaoyan Liu, G. Du","doi":"10.23919/SNW.2017.8242303","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242303","url":null,"abstract":"As the device scaling down to sub-10nm, the quasi-ballistic transport becomes important. Some previous works have suggested using DD method to involve the quasi-ballistic transport effect through modifying the transport parameters. A procedure is introduced to calibrate the transport parameters of the DD model by using the simulation results of MC device simulator.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128003966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242313
Sihyun Kim, D. Kwon, Ryoongbin Lee, D. Kim, Byung-Gook Park
The temperature dependence of MOSFET and TFET-based pH sensitive ISFET was investigated through TCAD device simulation. The transfer characteristics and the pH sensitivities of both devices at various temperature were compared. TFET-based ISFET exhibits superior thermal stability in contrast with the MOSFET-based ISFET due to the difference of conduction mechanism.
{"title":"Simulation study on temprature dependence of MOSFET and TFET-based pH-sensitive ISFET","authors":"Sihyun Kim, D. Kwon, Ryoongbin Lee, D. Kim, Byung-Gook Park","doi":"10.23919/SNW.2017.8242313","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242313","url":null,"abstract":"The temperature dependence of MOSFET and TFET-based pH sensitive ISFET was investigated through TCAD device simulation. The transfer characteristics and the pH sensitivities of both devices at various temperature were compared. TFET-based ISFET exhibits superior thermal stability in contrast with the MOSFET-based ISFET due to the difference of conduction mechanism.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131985070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242306
Seunghyun Kim, Do-Bin Kim, Eunseon Yu, Sang-Ho Lee, Seongjae Cho, Byung-Gook Park
In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (Kpgm) depending on nitride layer properties is analytically studied.
{"title":"Effects of nitride trap layer properties on location of charge centroid in charge-trap flash memory","authors":"Seunghyun Kim, Do-Bin Kim, Eunseon Yu, Sang-Ho Lee, Seongjae Cho, Byung-Gook Park","doi":"10.23919/SNW.2017.8242306","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242306","url":null,"abstract":"In this study, the effects of nitride trap layer properties on location of charge centroid in charge-trap flash (CTF) memory are closely investigated. In the operations of CTF memories, charges tunnel into the nitride layer through thin oxide, unlike the floating-gate (FG) type flash memory where the charges are stored in the conductive poly-crystalline Si. Deeper understanding of distribution of the trapped charges should be beneficial in setting up an accurate compact model of CTF memory cell, where the charge centroid becomes a very practical means by which a rather large number of trapped electrons can be dealt in the more mathematical manner as a whole electron cloud. The relation between charge centroid and program voltage (Kpgm) depending on nitride layer properties is analytically studied.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242339
Zhen Dong, Z. Zhou, Z.F. Li, C. Liu, Y. Jiang, P. Huang, L.F. Liu, X.Y. Liu, J. Kang
In this work, we conduct research on optimizing schemes for the RRAM-based implementation of CNN. Our main achievements contain: 1) A concrete CNN circuit and corresponding operation methods are developed. 2) Quantification methods for utilizing binary or multilevel RRAM as synapses are proposed, and our CNN performs with 98% accuracy on the MNIST dataset using multilevel RRAM and 97% accuracy using binary RRAM. 3) Influence of the number and size of kernels, as well as the device conductance variation on final recognition accuracy is studied in detail. 4) Online learning tasks are performed using the developed CNN system with binary STDP protocol, and 94.6% accuracy on average is achieved.
{"title":"RRAM based convolutional neural networks for high accuracy pattern recognition and online learning tasks","authors":"Zhen Dong, Z. Zhou, Z.F. Li, C. Liu, Y. Jiang, P. Huang, L.F. Liu, X.Y. Liu, J. Kang","doi":"10.23919/SNW.2017.8242339","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242339","url":null,"abstract":"In this work, we conduct research on optimizing schemes for the RRAM-based implementation of CNN. Our main achievements contain: 1) A concrete CNN circuit and corresponding operation methods are developed. 2) Quantification methods for utilizing binary or multilevel RRAM as synapses are proposed, and our CNN performs with 98% accuracy on the MNIST dataset using multilevel RRAM and 97% accuracy using binary RRAM. 3) Influence of the number and size of kernels, as well as the device conductance variation on final recognition accuracy is studied in detail. 4) Online learning tasks are performed using the developed CNN system with binary STDP protocol, and 94.6% accuracy on average is achieved.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130934711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242300
Dokyun Son, Ilho Myeong, Hyunsuk Kim, Myounggon Kang, Hyungcheol Shin
Self-heating effects (SHEs) were studied on the vertical nanoplate-shaped gate-all-around (GAA) FETs (vNPFETs) as a target of 5nm node technology. The thermal properties are compared between face-up and face-down configuration. Decreasing the channel width is vulnerable to both configurations in terms of SHEs due to the reduced area of heat dissipation. It is well known that the SHE is alleviated on AC condition, while our results show that the SHE is still important in vNPFET on AC condition.
{"title":"In-depth analysis of self-heating effects in vertical nanoplate-shaped GAAFETs","authors":"Dokyun Son, Ilho Myeong, Hyunsuk Kim, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242300","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242300","url":null,"abstract":"Self-heating effects (SHEs) were studied on the vertical nanoplate-shaped gate-all-around (GAA) FETs (vNPFETs) as a target of 5nm node technology. The thermal properties are compared between face-up and face-down configuration. Decreasing the channel width is vulnerable to both configurations in terms of SHEs due to the reduced area of heat dissipation. It is well known that the SHE is alleviated on AC condition, while our results show that the SHE is still important in vNPFET on AC condition.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116547363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242309
Yuanlin Li, Reon Katsumura, Mika Grönroos, A. Tsurumaki‐Fukuchi, M. Arita, H. Andoh, T. Morie, Yasuo Takahashi
ReRAM (Resistive Random Access Memory) has been drawing attention for its neural network applications with low-power and high-speed operation. The multilevel data storage capability is inherently needed to use the ReRAM as synaptic devices. In this study, two ReRAM devices with different electrode materials in which the operation mechanisms are thought to be different was fabricated and tested. It was clarified that the multilevel resistance characteristics were achieved in both devices.
{"title":"Evaluation of multilevel memory capability of ReRAM using Ta2O5 insulator and different electrode materials","authors":"Yuanlin Li, Reon Katsumura, Mika Grönroos, A. Tsurumaki‐Fukuchi, M. Arita, H. Andoh, T. Morie, Yasuo Takahashi","doi":"10.23919/SNW.2017.8242309","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242309","url":null,"abstract":"ReRAM (Resistive Random Access Memory) has been drawing attention for its neural network applications with low-power and high-speed operation. The multilevel data storage capability is inherently needed to use the ReRAM as synaptic devices. In this study, two ReRAM devices with different electrode materials in which the operation mechanisms are thought to be different was fabricated and tested. It was clarified that the multilevel resistance characteristics were achieved in both devices.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133722215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242299
Ilho Myeong, Dokyun Son, Hyunsuk Kim, Myounggon Kang, Hyungcheol Shin
In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common spacer. Also, to release the thermal bottleneck to the substrate side, the metal pad size was adjusted and the composition of the Shallow Trench Isolation (SII) was changed.
{"title":"Analysis of self-heating effects in vertical MOSFETs according to device geometry","authors":"Ilho Myeong, Dokyun Son, Hyunsuk Kim, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242299","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242299","url":null,"abstract":"In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common spacer. Also, to release the thermal bottleneck to the substrate side, the metal pad size was adjusted and the composition of the Shallow Trench Isolation (SII) was changed.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"25 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133042319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242301
Changbeom Woo, Jongsu Kim, Myounggon Kang, Hyungcheol Shin
In this paper, we have investigated RC delay not only on single channel but also on multi-channels in lateral FET (LFET) and vertical FET (VFET). It has verified that there is always constant for SCEs regardless of the number of channels. Since all structures have the same gate length and spacer length, they have the same gate controllability. On the other hand, RC delay depends on the structure. Because VFET has more parasitic capacitance, it shows poor RC delay. As a result, LFET is more promising than VFET in high performance.
{"title":"Analysis of RC delay for high performance in LFET and VFET","authors":"Changbeom Woo, Jongsu Kim, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242301","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242301","url":null,"abstract":"In this paper, we have investigated RC delay not only on single channel but also on multi-channels in lateral FET (LFET) and vertical FET (VFET). It has verified that there is always constant for SCEs regardless of the number of channels. Since all structures have the same gate length and spacer length, they have the same gate controllability. On the other hand, RC delay depends on the structure. Because VFET has more parasitic capacitance, it shows poor RC delay. As a result, LFET is more promising than VFET in high performance.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115588628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242298
Youngsoo Seo, Myounggon Kang, Hyungcheol Shin
The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
{"title":"Analysis of parasitic capacitance and performance in gate-ail-around and tri-gate channel vertical FET","authors":"Youngsoo Seo, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242298","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242298","url":null,"abstract":"The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124839824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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