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Harmonie innovatios in semiconductor devices and computer architectures toward post “Moore-era” 面向后“摩尔时代”的半导体器件和计算机架构的和谐创新
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242327
Y. Hayashi
Simple 2D scaling of semiconductor devices by “Moore's law” will not work well soon to improve the performances and power efficiencies due to tight physical directional limits. System integrations, however, might continue to advance further by 3D structural evolutions either in monolithic on-chip integrations or heterogeneous off-chip stacks. Accelerated implementations of new architectures and new functional materials would be key factors, especially to execute machine learnings more efficiently for ΑΙ-based smart applications. Just now, we have established SDRJ (The System Device Roadmap Committee of Japan, https://www.sdrj.jp/) in JSAP collaborated with IEEE IRDS (International Roadmap for Devices and Systems, http://irds.ieee.org/) to discuss the roadmaps internationally toward the year of 2030.
由于严格的物理方向限制,根据“摩尔定律”对半导体器件进行简单的二维缩放将无法很好地提高性能和功率效率。然而,系统集成可能会继续通过单片片上集成或异质片外堆栈的3D结构演变而进一步发展。新架构和新功能材料的加速实现将是关键因素,特别是对于ΑΙ-based智能应用程序更有效地执行机器学习。刚刚,我们在JSAP中成立了SDRJ(日本系统设备路线图委员会,https://www.sdrj.jp/),并与IEEE IRDS(设备和系统国际路线图,http://irds.ieee.org/)合作,讨论了面向2030年的国际路线图。
{"title":"Harmonie innovatios in semiconductor devices and computer architectures toward post “Moore-era”","authors":"Y. Hayashi","doi":"10.23919/SNW.2017.8242327","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242327","url":null,"abstract":"Simple 2D scaling of semiconductor devices by “Moore's law” will not work well soon to improve the performances and power efficiencies due to tight physical directional limits. System integrations, however, might continue to advance further by 3D structural evolutions either in monolithic on-chip integrations or heterogeneous off-chip stacks. Accelerated implementations of new architectures and new functional materials would be key factors, especially to execute machine learnings more efficiently for ΑΙ-based smart applications. Just now, we have established SDRJ (The System Device Roadmap Committee of Japan, https://www.sdrj.jp/) in JSAP collaborated with IEEE IRDS (International Roadmap for Devices and Systems, http://irds.ieee.org/) to discuss the roadmaps internationally toward the year of 2030.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127880551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gated-thyristor DRAM cell with pillar channel structure 具有柱状通道结构的门控晶闸管DRAM单元
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242302
Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park
In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.
本文提出了一种基于柱状通道和侧壁栅极的门控晶闸管的DRAM单元,并对其进行了器件仿真研究。在基区存储的电子使读电流降低电位势垒的差异。由于其基于热注入的机制,具有10ns以下的快速写入速度和自连接字线的高可扩展性结构。
{"title":"Gated-thyristor DRAM cell with pillar channel structure","authors":"Hyungjin Kim, M. Kwon, Myung-Hyun Baek, Sungmin Hwang, Sihyun Kim, Taejin Jang, Jeong-Jun Lee, Hyun-Min Kim, Kitae Lee, Byung-Gook Park","doi":"10.23919/SNW.2017.8242302","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242302","url":null,"abstract":"In this work, a DRAM cell based on gated-thyristor having pillar channel and sidewall gate is proposed and investigated through device simulation study. Stored electrons in the base region make a difference in read current lowering potential barrier. It has a fast writing speed under 10 ns because of its mechanism based on thermal injection and highly scalable structure because of self-connected word line.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117128635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis on extension region in nanowire FET considering RC delay and electrical characteristics 考虑RC延迟和电学特性的纳米线场效应管扩展区分析
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242288
Jongsu Kim, Changbeom Woo, Myounggon Kang, Hyungcheol Shin
Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.
分析了器件在工作区、阈下区和关断区的特性,提出了纳米线场效应管的优化设计准则。首先,从RC延迟的角度研究了可拓区域的结构。此外,由于扩展区的结构对阈下摆振(SS)和栅极诱发漏漏(GIDL)的影响很大,我们还对这些特性进行了研究。因此,综合考虑器件三个区域的所有特性,发现当延伸长度为6 nm时,无重叠或有轻微的underlap时,具有最佳的特性。
{"title":"Analysis on extension region in nanowire FET considering RC delay and electrical characteristics","authors":"Jongsu Kim, Changbeom Woo, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242288","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242288","url":null,"abstract":"Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
GeSn N-FinFETs and NiGeSn contact formation by phosphorus implant 磷植入形成的GeSn n - finfet与NiGeSn触点
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242315
Y. Chuang, Hsien-chih Huang, Jiun-Yun Li
We report n-FinFETs with a high drive current of 108 Aim and the best SS of 138 mV/dec. A higher drive current was achieved by the reduction of series S/D resistance. NiGeSn/n+-GeSn contact formation was done by rapid thermal annealing below 400 °C. Contact resistivity was characterized by circular transmission line model. The contact resistance decreases with the carrier concentration or Sn fraction in GeSn films with the lowest contact resistivity of 3.8×10−8 Ω-cm2.
我们报道了高驱动电流为108 Aim和最佳SS为138 mV/dec的n- finfet。通过降低串联S/D电阻,实现了更高的驱动电流。NiGeSn/n+-GeSn接触形成通过400℃以下快速热退火完成。采用圆形传输线模型对接触电阻率进行表征。GeSn薄膜的接触电阻随载流子浓度或Sn含量的增加而减小,接触电阻最低为3.8×10−8 Ω-cm2。
{"title":"GeSn N-FinFETs and NiGeSn contact formation by phosphorus implant","authors":"Y. Chuang, Hsien-chih Huang, Jiun-Yun Li","doi":"10.23919/SNW.2017.8242315","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242315","url":null,"abstract":"We report n-FinFETs with a high drive current of 108 Aim and the best SS of 138 mV/dec. A higher drive current was achieved by the reduction of series S/D resistance. NiGeSn/n<sup>+</sup>-GeSn contact formation was done by rapid thermal annealing below 400 °C. Contact resistivity was characterized by circular transmission line model. The contact resistance decreases with the carrier concentration or Sn fraction in GeSn films with the lowest contact resistivity of 3.8×10<sup>−8</sup> Ω-cm<sup>2</sup>.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122141245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Theoretical analysis of quasi-ballistic hole transport in Ge and Si nanowires focusing on energy relaxation process 基于能量松弛过程的锗和硅纳米线准弹道空穴输运理论分析
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242284
Hajime Tanaka, J. Suda, T. Kimoto
The quasi-ballistic hole transport capabilities of Ge and Si NWs were calculated using atomistic electron-phonon coupling and Boltzmann transport equation. Analyzing the forward and backward current fluxes, it was shown that the positive impact of high mobility of Ge is canceled by its slower energy relaxation, which results in comparable transmission coefficients and current transport capabilities between Ge and Si NWs.
利用原子电子-声子耦合和玻尔兹曼输运方程计算了锗和硅NWs的准弹道空穴输运能力。对正向和反向电流通量的分析表明,Ge的高迁移率的积极影响被其较慢的能量弛豫所抵消,这使得Ge和Si NWs之间的传输系数和电流输运能力相当。
{"title":"Theoretical analysis of quasi-ballistic hole transport in Ge and Si nanowires focusing on energy relaxation process","authors":"Hajime Tanaka, J. Suda, T. Kimoto","doi":"10.23919/SNW.2017.8242284","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242284","url":null,"abstract":"The quasi-ballistic hole transport capabilities of Ge and Si NWs were calculated using atomistic electron-phonon coupling and Boltzmann transport equation. Analyzing the forward and backward current fluxes, it was shown that the positive impact of high mobility of Ge is canceled by its slower energy relaxation, which results in comparable transmission coefficients and current transport capabilities between Ge and Si NWs.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123570993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RRAM-based pattern recognition system with locally inhibited post-neurons 基于局部抑制后神经元的随机存储器模式识别系统
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242340
Zheng Zhou, Peng Huang, Yuning Jiang, Zhe Chen, Chen Liu, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang
A novel RRAM-based pattern recognition system with locally inhibited post-neurons is developed. The system is able to learn the whole MNIST training set (60,000 patterns). By using the system, the same post-neuron is fired by the similar patterns in the same training class, which causes the reduction of hardware cost. With the locally inhibited post-neuron, the system can achieve more than 90.73% recognition accuracy.
提出了一种基于随机存储器的后神经元局部抑制模式识别系统。该系统能够学习整个MNIST训练集(60,000个模式)。通过使用该系统,在相同的训练课程中使用相似的模式激发相同的后神经元,从而降低了硬件成本。通过局部抑制后神经元,系统的识别准确率达到90.73%以上。
{"title":"RRAM-based pattern recognition system with locally inhibited post-neurons","authors":"Zheng Zhou, Peng Huang, Yuning Jiang, Zhe Chen, Chen Liu, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang","doi":"10.23919/SNW.2017.8242340","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242340","url":null,"abstract":"A novel RRAM-based pattern recognition system with locally inhibited post-neurons is developed. The system is able to learn the whole MNIST training set (60,000 patterns). By using the system, the same post-neuron is fired by the similar patterns in the same training class, which causes the reduction of hardware cost. With the locally inhibited post-neuron, the system can achieve more than 90.73% recognition accuracy.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133963804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel vertical tunnel FET of band-to-band tunneling aligned with gate electric field with averaged SS of 28 mV/decade 一种新型垂直隧道场效应管,带对带隧道与栅极电场排列,平均SS为28 mV/ 10年
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242291
Pao-Chuan Shih, Hsien-chih Huang, Chien-An Wang, Jiun-Yun Li
We propose a novel vertical tunnel FET of band-to-band tunneling aligned with the gate electric field. Simulation results show high drive current and extremely sharp subthreshold swing due to excellent gate control over the tunnel junction. OFF state leakage via source-to-drain tunneling is much suppressed by the spacer layer between the source and drain layers. Furthermore, this device is fully compatible to VLSI technology.
我们提出了一种新型垂直隧道场效应管,其带对带隧穿与栅极电场对齐。仿真结果表明,由于对隧道结极好的栅极控制,驱动电流高,亚阈值摆幅极陡。通过源漏隧道的关闭状态泄漏被源漏层和漏层之间的间隔层大大抑制。此外,该器件完全兼容VLSI技术。
{"title":"A novel vertical tunnel FET of band-to-band tunneling aligned with gate electric field with averaged SS of 28 mV/decade","authors":"Pao-Chuan Shih, Hsien-chih Huang, Chien-An Wang, Jiun-Yun Li","doi":"10.23919/SNW.2017.8242291","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242291","url":null,"abstract":"We propose a novel vertical tunnel FET of band-to-band tunneling aligned with the gate electric field. Simulation results show high drive current and extremely sharp subthreshold swing due to excellent gate control over the tunnel junction. OFF state leakage via source-to-drain tunneling is much suppressed by the spacer layer between the source and drain layers. Furthermore, this device is fully compatible to VLSI technology.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133414396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of inhibitory operation in neuromorphic system 神经形态系统抑制操作的实施
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242323
Jeong-Jun Lee, M. Kwon, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park
An inhibition part of synapse-neuron connection is indispensable in a neuromorphic system for hardware implementation of artificial intelligence. First, when the system operates with the winner takes all method, a lateral inhibition is required to permit one neuron firing, thereby preventing other neurons from firing. In addition, in order to implement the negative weight, an inhibition part, which is the role of subtracting the signal, must be accompanied. Therefore, in this paper, the structure of a simple inhibition part for lateral inhibition and negative weight is presented and it is verified by simulation.
在人工智能硬件实现的神经形态系统中,突触-神经元连接的抑制部分是必不可少的。首先,当系统以赢者通吃的方式运行时,需要一个横向抑制来允许一个神经元放电,从而防止其他神经元放电。此外,为了实现负权,必须伴随着抑制部分,即减去信号的作用。因此,本文提出了一种用于横向抑制和负权重的简单抑制部件结构,并通过仿真进行了验证。
{"title":"Implementation of inhibitory operation in neuromorphic system","authors":"Jeong-Jun Lee, M. Kwon, Hyungjin Kim, Sungmin Hwang, Byung-Gook Park","doi":"10.23919/SNW.2017.8242323","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242323","url":null,"abstract":"An inhibition part of synapse-neuron connection is indispensable in a neuromorphic system for hardware implementation of artificial intelligence. First, when the system operates with the winner takes all method, a lateral inhibition is required to permit one neuron firing, thereby preventing other neurons from firing. In addition, in order to implement the negative weight, an inhibition part, which is the role of subtracting the signal, must be accompanied. Therefore, in this paper, the structure of a simple inhibition part for lateral inhibition and negative weight is presented and it is verified by simulation.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122188552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of two divided component of NBTI framework using TCAD simulation 利用TCAD仿真分析NBTI框架的两分分量
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242311
Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, Hyungcheol Shin
In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided design (TCAD) software.
本文将两种负偏置温度不稳定性(NBTI)框架组件分为界面陷阱生成(Δ Vit)和已有缺陷中的空穴捕获(Δ Vht)。阈值电压漂移(ΔVT)的贡献由两个分割分量验证并独立研究。利用计算机辅助设计(TCAD)软件模拟了NBTI应力作用下层间层厚度的影响。
{"title":"Analysis of two divided component of NBTI framework using TCAD simulation","authors":"Shinkeun Kim, Youngsoo Seo, Dokyun Son, Myounggon Kang, Hyungcheol Shin","doi":"10.23919/SNW.2017.8242311","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242311","url":null,"abstract":"In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided design (TCAD) software.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new operation scheme to obtain 3-bit capacity per cell in HfO2 based RRAM with high uniformity 提出了一种在高均匀性的HfO2 RRAM中获得每单元3位容量的新操作方案
Pub Date : 2017-06-01 DOI: 10.23919/SNW.2017.8242308
D. Zhu, Xiangxiang Ding, Peng Huang, Zheng Zhou, Xiaolu Ma, Lifeng Liu, Jinfeng Kang, Xing Zhang
In this work, HfO2 based resistive random access memory (RRAM) is fabricated and 3-bit storage capacity per cell is demonstrated under both DC and AC mode. In the AC mode, a new operation scheme of balancing set process and reset process is proposed to improve the resistance distribution uniformity (relative standard deviation about 21.1%). The relatives between set and reset parameters are also discussed and a simple model is used to explain these results.
在这项工作中,制作了基于HfO2的电阻式随机存取存储器(RRAM),并在直流和交流模式下验证了每个单元的3位存储容量。在交流模式下,为了提高电阻分布均匀性(相对标准偏差约为21.1%),提出了一种新的设置过程和复位过程平衡的运行方案。还讨论了设定参数和重置参数之间的关系,并用一个简单的模型来解释这些结果。
{"title":"A new operation scheme to obtain 3-bit capacity per cell in HfO2 based RRAM with high uniformity","authors":"D. Zhu, Xiangxiang Ding, Peng Huang, Zheng Zhou, Xiaolu Ma, Lifeng Liu, Jinfeng Kang, Xing Zhang","doi":"10.23919/SNW.2017.8242308","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242308","url":null,"abstract":"In this work, HfO2 based resistive random access memory (RRAM) is fabricated and 3-bit storage capacity per cell is demonstrated under both DC and AC mode. In the AC mode, a new operation scheme of balancing set process and reset process is proposed to improve the resistance distribution uniformity (relative standard deviation about 21.1%). The relatives between set and reset parameters are also discussed and a simple model is used to explain these results.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116957269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
期刊
2017 Silicon Nanoelectronics Workshop (SNW)
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