Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242324
M. Kwon, Sungmin Hwang, Myung-Hyun Baek, Seongjae Cho, Byung-Gook Park
In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed in analog circuit.
{"title":"Dual gate positive feedback field-effect transistor for low power analog circuit","authors":"M. Kwon, Sungmin Hwang, Myung-Hyun Baek, Seongjae Cho, Byung-Gook Park","doi":"10.23919/SNW.2017.8242324","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242324","url":null,"abstract":"In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed in analog circuit.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116212047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242278
B. Weber, Y. Hsueh, T. Watson, Ruoyu Li, A. Hamilton, L. Hollenberg, R. Rahman, M. Simmons
We demonstrate the single-shot spin read-out of single donors and few-donor clusters, positioned with atomic precision by scanning tunneling microscopy (STM) in atomically engineered silicon devices [1-3]. In donor clusters, we measure spin lifetimes of up to half a minute, recorded at a read-out fidelity of up to 99.8% [2]. Importantly, measuring spin relaxations rates of electrons bound to a single P donor in orientation-dependent electric and magnetic fields, we identify a previously unreported spin relaxation pathway for donor-based qubits in silicon [1].
{"title":"Electron spin relaxation of single phosphorus donors and donor clusters in atomically engineered silicon devices","authors":"B. Weber, Y. Hsueh, T. Watson, Ruoyu Li, A. Hamilton, L. Hollenberg, R. Rahman, M. Simmons","doi":"10.23919/SNW.2017.8242278","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242278","url":null,"abstract":"We demonstrate the single-shot spin read-out of single donors and few-donor clusters, positioned with atomic precision by scanning tunneling microscopy (STM) in atomically engineered silicon devices [1-3]. In donor clusters, we measure spin lifetimes of up to half a minute, recorded at a read-out fidelity of up to 99.8% [2]. Importantly, measuring spin relaxations rates of electrons bound to a single P donor in orientation-dependent electric and magnetic fields, we identify a previously unreported spin relaxation pathway for donor-based qubits in silicon [1].","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129296745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242333
T. Iwasaki, Zhongwang Wang, J. Reynolds, M. Muruganathan, H. Mizuta
We report the single carrier transport properties in the p-doped/less-doped graphene nanoconstriction structures. In the doped graphene devices, the overlapped Coulomb diamond characteristics are observed around the charge neutrality point (CNF) at 5 K. Reducing doping in graphene by annealing, the periodic peaks appear in the certain gate voltage range around the CNP. Additionally, the non-overlapped Coulomb diamond characteristic is observed. These results suggest that unintentional charging island formation in graphene nanodevices can be avoided by decreasing the doping concentration.
{"title":"Physisorption doping induced multiple dots behavior in graphene nanoconstrictions","authors":"T. Iwasaki, Zhongwang Wang, J. Reynolds, M. Muruganathan, H. Mizuta","doi":"10.23919/SNW.2017.8242333","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242333","url":null,"abstract":"We report the single carrier transport properties in the p-doped/less-doped graphene nanoconstriction structures. In the doped graphene devices, the overlapped Coulomb diamond characteristics are observed around the charge neutrality point (CNF) at 5 K. Reducing doping in graphene by annealing, the periodic peaks appear in the certain gate voltage range around the CNP. Additionally, the non-overlapped Coulomb diamond characteristic is observed. These results suggest that unintentional charging island formation in graphene nanodevices can be avoided by decreasing the doping concentration.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127908425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242294
Dong Keun Lee, Sungjun Kim, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Byung-Gook Park
Nano-wedge structured resistive switching memory is fabricated through modifying bottom electrode structure and the DC characteristics of devices are analyzed. Excellent data storage capability is proved through retention test by setting at high temperature over 104 seconds in both low and high resistance states (LRS and HRS). Endurance test is also performed to demonstrate outstanding characteristics of the resistive switching memory device.
{"title":"Fabrication of nano-wedge resistive switching memory and analysis on its switching characteristics","authors":"Dong Keun Lee, Sungjun Kim, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Byung-Gook Park","doi":"10.23919/SNW.2017.8242294","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242294","url":null,"abstract":"Nano-wedge structured resistive switching memory is fabricated through modifying bottom electrode structure and the DC characteristics of devices are analyzed. Excellent data storage capability is proved through retention test by setting at high temperature over 104 seconds in both low and high resistance states (LRS and HRS). Endurance test is also performed to demonstrate outstanding characteristics of the resistive switching memory device.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242322
Wei-Min Tu, H. Tseng
Thermal-management design for power devices by placing the 2D graphene heat spreader (GHS) at the backside of collector-up heteroj unction bipolar transistors (HBTs) is presented. Temperature distribution in the GHS and the application of these spreaders to ameliorate thermal-coupling effects on multi-finger transistors were discussed. Compared to the npn device, the pnp device exhibits greater thermal-stability enhancement results, which are extraordinary and reproducible. Both numerical simulation and experimental measurement were achieved to scrutinize thermal performance of the GHS.
{"title":"Graphene heat spreaders for thermal management of HBTs","authors":"Wei-Min Tu, H. Tseng","doi":"10.23919/SNW.2017.8242322","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242322","url":null,"abstract":"Thermal-management design for power devices by placing the 2D graphene heat spreader (GHS) at the backside of collector-up heteroj unction bipolar transistors (HBTs) is presented. Temperature distribution in the GHS and the application of these spreaders to ameliorate thermal-coupling effects on multi-finger transistors were discussed. Compared to the npn device, the pnp device exhibits greater thermal-stability enhancement results, which are extraordinary and reproducible. Both numerical simulation and experimental measurement were achieved to scrutinize thermal performance of the GHS.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132638621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242271
Jixuan Wu, Z. Fan, Jiezhi Chen, Xiangwei Jiang
Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(Vw) defect is systematically studied in this work. Impacts of Vw defect's positions are characterized in WSe2 TTETs by using rigorous ab initio simulations. It is found that Vw defect that locates in the tunnel junction will increase Ion, while it has no impact on Toff. Further discussions are also made with focus on the variation of defect position in TFET and the fluctuations of device performance for robust circuit design.
{"title":"A study on W vacancy defect in mono-layer transition-metal dichalcogenide (TMD) TFETs through systematic ab initio calculations","authors":"Jixuan Wu, Z. Fan, Jiezhi Chen, Xiangwei Jiang","doi":"10.23919/SNW.2017.8242271","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242271","url":null,"abstract":"Aiming at performance enhancements and robust reliability design of mono-layer transition-metal dichalcogenide (TMD) tunneling FET(TFET), W vacancy(V<inf>w</inf>) defect is systematically studied in this work. Impacts of V<inf>w</inf> defect's positions are characterized in WSe<inf>2</inf> TTETs by using rigorous ab initio simulations. It is found that V<inf>w</inf> defect that locates in the tunnel junction will increase I<inf>on</inf>, while it has no impact on T<inf>off</inf>. Further discussions are also made with focus on the variation of defect position in TFET and the fluctuations of device performance for robust circuit design.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123916732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242280
G. Prabhudesai, G. Greeshma, M. Shibuya, M. Manoharan, H. Mizuta, M. Tabe, D. Moraru
Inter-band tunneling in Si is a key mechanism for Esaki diodes and tunnel FETs. In nanoscale devices, the dopant states under high built-in electric field may significantly affect inter-band tunneling transport. Here, we introduce firsttime observations from measurements of nanoscale Si tunnel diodes of two main effects: (i) splitting of dopant minibands in high electric field, similarly to the Wannier-Stark ladder; (ii) single-charge tunneling transport via donor-acceptor pairs aligned by the electric field. These phenomena produce distinguishable effects to enhance inter-band tunneling current.
{"title":"Inter-band tunneling mechanisms via dopant-induced energy states in low-dimensional si tunnel diodes","authors":"G. Prabhudesai, G. Greeshma, M. Shibuya, M. Manoharan, H. Mizuta, M. Tabe, D. Moraru","doi":"10.23919/SNW.2017.8242280","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242280","url":null,"abstract":"Inter-band tunneling in Si is a key mechanism for Esaki diodes and tunnel FETs. In nanoscale devices, the dopant states under high built-in electric field may significantly affect inter-band tunneling transport. Here, we introduce firsttime observations from measurements of nanoscale Si tunnel diodes of two main effects: (i) splitting of dopant minibands in high electric field, similarly to the Wannier-Stark ladder; (ii) single-charge tunneling transport via donor-acceptor pairs aligned by the electric field. These phenomena produce distinguishable effects to enhance inter-band tunneling current.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122464069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242279
A. Afiff, A. Samanta, T. Hasan, A. Udhiarto, D. Hartanto, H. Sudibyo, M. Tabe, D. Moraru
We have recently reported single-electron tunneling (SET) via a-few-donor QDs at high temperatures in high-concentration selectively-doped SOI-FETs. A central QD works by SET mechanism above 150 Κ at small source-drain bias due to enhanced tunnel barrier. For tuning the tunnel barrier, it becomes critical to understand the impact of the donor-QD location on the SET transport. Here, we report the possibility of probing donor-QDs from center to near the lead edge using high-bias stability diagrams. We also observe and model the changes due to purposely shifted positions of the selectively-doped area.
{"title":"Probing the impact of donor quantum dots with high-bias stability diagrams in selectively-doped Si nanoscale transistors","authors":"A. Afiff, A. Samanta, T. Hasan, A. Udhiarto, D. Hartanto, H. Sudibyo, M. Tabe, D. Moraru","doi":"10.23919/SNW.2017.8242279","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242279","url":null,"abstract":"We have recently reported single-electron tunneling (SET) via a-few-donor QDs at high temperatures in high-concentration selectively-doped SOI-FETs. A central QD works by SET mechanism above 150 Κ at small source-drain bias due to enhanced tunnel barrier. For tuning the tunnel barrier, it becomes critical to understand the impact of the donor-QD location on the SET transport. Here, we report the possibility of probing donor-QDs from center to near the lead edge using high-bias stability diagrams. We also observe and model the changes due to purposely shifted positions of the selectively-doped area.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132366140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.23919/SNW.2017.8242304
Shamik Das, Nicolas S. Arango
This paper presents models, designs, and simulation results for logic circuits based upon graphene ballistic deflection transistors (GBDTs). The use of graphene in conventional semiconductor circuits has proved difficult due to its negligible bandgap. GBDTs might avoid this deficiency by electrostatically steering currents through graphene's highly conductive two-dimensional charge transport medium. Simulation results are presented for a GBDT-based inverter and full adder that are predicted to operate twice as fast as conventional CMOS circuits, at the cost of much lower transistor density. The GBDT-based circuits presented in this paper would be well suited for high-speed, high-duty-cycle applications, including high-throughput networking and high-performance computing.
{"title":"Performance assessment of a graphene-based ballistic switch design","authors":"Shamik Das, Nicolas S. Arango","doi":"10.23919/SNW.2017.8242304","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242304","url":null,"abstract":"This paper presents models, designs, and simulation results for logic circuits based upon graphene ballistic deflection transistors (GBDTs). The use of graphene in conventional semiconductor circuits has proved difficult due to its negligible bandgap. GBDTs might avoid this deficiency by electrostatically steering currents through graphene's highly conductive two-dimensional charge transport medium. Simulation results are presented for a GBDT-based inverter and full adder that are predicted to operate twice as fast as conventional CMOS circuits, at the cost of much lower transistor density. The GBDT-based circuits presented in this paper would be well suited for high-speed, high-duty-cycle applications, including high-throughput networking and high-performance computing.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125841317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Positive bias temperature instability (PBTI) of tunnel thin-film transistor (TFT) with poly-Si channel film is proposed for the first time. The novel interband tunneling transport mechanism of tunnel-TFT results in special PBTI behavior. For PBTI at 75 °C with stress voltage 10 V, tunnel-TFT exhibit excellent PBTI immunity compared to conventional TFT. However, the degradation of tunnel-TFT is getting worse when the temperature of PBTI is reduced. It may be because the interband tunneling is more sensitive at low temperature due to the deep trap characteristics, which affects the transport behavior of tunneling electrons. It would be helpful for the development of tunnel transistors.
{"title":"Positive bias temperature instability of tunnel thin-film transistor for applications of system-on-panel and three-dimension integrated circuits","authors":"William Cheng-Yu Ma, Hui-Shun Hsu, Che-Yu Jao, C.-C. Fang, Tzu-Han Liao","doi":"10.23919/SNW.2017.8242329","DOIUrl":"https://doi.org/10.23919/SNW.2017.8242329","url":null,"abstract":"Positive bias temperature instability (PBTI) of tunnel thin-film transistor (TFT) with poly-Si channel film is proposed for the first time. The novel interband tunneling transport mechanism of tunnel-TFT results in special PBTI behavior. For PBTI at 75 °C with stress voltage 10 V, tunnel-TFT exhibit excellent PBTI immunity compared to conventional TFT. However, the degradation of tunnel-TFT is getting worse when the temperature of PBTI is reduced. It may be because the interband tunneling is more sensitive at low temperature due to the deep trap characteristics, which affects the transport behavior of tunneling electrons. It would be helpful for the development of tunnel transistors.","PeriodicalId":424135,"journal":{"name":"2017 Silicon Nanoelectronics Workshop (SNW)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115192043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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