Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635381
K. Yeo, W. Goh, M. Phyu
In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.
{"title":"Area Efficient Low-Power Static Explicit-Pulsed Flip-Flop with Local Feedback","authors":"K. Yeo, W. Goh, M. Phyu","doi":"10.1109/EDSSC.2005.1635381","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635381","url":null,"abstract":"In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-μm CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132660807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635213
W. Yeh, Chieh-Ming Lai, C. Lin, Y. Fang, H.-H. Hu, K. Chen, G. Huang
For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device's characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45μm∼4.5μm) and width (0.18μm∼10μm) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5μm LOD (low compressive stress) and 0.18μm gate width (narrow width) possess the better performance.
{"title":"The impact of mobility modulation technology on device performance and reliability for sub-90nm SOI MOSFETs","authors":"W. Yeh, Chieh-Ming Lai, C. Lin, Y. Fang, H.-H. Hu, K. Chen, G. Huang","doi":"10.1109/EDSSC.2005.1635213","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635213","url":null,"abstract":"For nMOSFET, utilizing the high tensile stress gate capping layer (GC layer) and length of diffusion (LOD) to control the tensile and compressive stress in channel regions were developed. In this work, in order to investigate the interactive stress effects of GC layer film thickness, LOD and gate width on device's characteristic and hot-carrier reliability; devices with various GC layer (1100A, 700A, SiN380), LOD (0.45μm∼4.5μm) and width (0.18μm∼10μm) were fabricated. It is found that devices with 700A GC layer layer (appropriate tensile stress), 4.5μm LOD (low compressive stress) and 0.18μm gate width (narrow width) possess the better performance.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131474887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635241
Jingfeng Ding, Zhigong Wang, Yinghua Qiu, Gui Wang
An integrated demultiplexer (DEMUX) for ultra high speed optical fiber communication systems has been described. The fabricated DEMUX operates error free at 20 Gb/s by 231-1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rms and p-p jitters of the output eye- diagram are just 1.2 ps and 5.6 ps respectively. The chip size is 1.8x0.9 mm2and its power dissipation is 720 mW.
{"title":"A Low Jitter 0.2 μm PHEMT 20 Gb/s 1:2 Demultiplexer","authors":"Jingfeng Ding, Zhigong Wang, Yinghua Qiu, Gui Wang","doi":"10.1109/EDSSC.2005.1635241","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635241","url":null,"abstract":"An integrated demultiplexer (DEMUX) for ultra high speed optical fiber communication systems has been described. The fabricated DEMUX operates error free at 20 Gb/s by 231-1 pseudorandom bit sequences (PRBS) via on-wafer testing. The measured rms and p-p jitters of the output eye- diagram are just 1.2 ps and 5.6 ps respectively. The chip size is 1.8x0.9 mm2and its power dissipation is 720 mW.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130932036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635219
P. Lai, C.X. Li, J. Xu, X. Zou, C. Chan
Wet NO oxidation with wet N2anneal is used to grow GeON gate dielectric on Ge substrate. As compared to dry NO oxidation, negligible growth of GeOxinterlayer and thus a near-perfect GeON dielectric can be obtained by the wet NO oxidation. As a result, MOS capacitors prepared by this method show greatly reduced interface-state and oxide-charge densities and gate leakage current. This should be attributed to the hydrolysable property of GeOxin water-containing atmosphere.
{"title":"Suppressed Growth of Interlayer GeOxin Ge MOS Capacitors with Gate Dielectric Prepared in Wet NO Ambient","authors":"P. Lai, C.X. Li, J. Xu, X. Zou, C. Chan","doi":"10.1109/EDSSC.2005.1635219","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635219","url":null,"abstract":"Wet NO oxidation with wet N2anneal is used to grow GeON gate dielectric on Ge substrate. As compared to dry NO oxidation, negligible growth of GeOxinterlayer and thus a near-perfect GeON dielectric can be obtained by the wet NO oxidation. As a result, MOS capacitors prepared by this method show greatly reduced interface-state and oxide-charge densities and gate leakage current. This should be attributed to the hydrolysable property of GeOxin water-containing atmosphere.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125581024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635386
Wenfa Zhan, Rui Wang, Duoli Zhang, Bing Lu
As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.
{"title":"Bus-based IP Reusable Verification Platform","authors":"Wenfa Zhan, Rui Wang, Duoli Zhang, Bing Lu","doi":"10.1109/EDSSC.2005.1635386","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635386","url":null,"abstract":"As the VLSI design scale shrinks, traditional verification methods can not satisfy the verification request, because they do not provide enough ability to check the function correctness and can not ensure the product quality. Verification has become the bottleneck of integrated circuit design. A method of bus based verification platform is presented and the reusable efficience can be improved 80% at least. The focus is to increase the productivity of the verification engineer by providing a framework to reuse verification unit.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123166982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635249
H. Hsu, Zhi Wang, G. Ma
This paper presents the design and implementation of a power amplifier for full-band UWB communication system by TSMC CMOS 0.18um technology. We use common source topology with an improved wideband RLC filter method and multilevel RLC matching method to achieve the wideband input/output matching and broadband power gain requirements. In order to increase the bandwidth, we also use both the cascade and cascade stage to increase the gain and gain flatness. Die-on-PCB measurements has shown this PA provides an average power gain of 10dB which from 3.1GHz-9GHz, average Pout_ldB of 0dBm in full-band(3.1GHz-10.6GHz), along with the power consumption of 25.2mW.
{"title":"A Low Power CMOS Full-Band UWB Power Amplifier Using Wideband RLC Matching Method","authors":"H. Hsu, Zhi Wang, G. Ma","doi":"10.1109/EDSSC.2005.1635249","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635249","url":null,"abstract":"This paper presents the design and implementation of a power amplifier for full-band UWB communication system by TSMC CMOS 0.18um technology. We use common source topology with an improved wideband RLC filter method and multilevel RLC matching method to achieve the wideband input/output matching and broadband power gain requirements. In order to increase the bandwidth, we also use both the cascade and cascade stage to increase the gain and gain flatness. Die-on-PCB measurements has shown this PA provides an average power gain of 10dB which from 3.1GHz-9GHz, average Pout_ldB of 0dBm in full-band(3.1GHz-10.6GHz), along with the power consumption of 25.2mW.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635388
B. Harish, M. Patil, N. Bhat
A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.
{"title":"Modeling of the Effects of Process Variations on Circuit Delay at 65nm","authors":"B. Harish, M. Patil, N. Bhat","doi":"10.1109/EDSSC.2005.1635388","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635388","url":null,"abstract":"A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121710295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635303
Zhiying Zhang, Xiaobo Wu, Xiaolang Yan
To fit some applications like in Power Management IC (Integrated Circuit), ahigh gain low offset BiCMOS op amp was proposed in this paper. A complementary input stage was adopted to meet a rail-to-rail ICMR (Input Common-Mode Range). And a special circuit configuration was introduced into the rail-to-rail amplifier to keep its gain constant. Simulation showed that the variation of gmwas maintained within 2% over the whole input range. Meanwhile, by using bipolar input stage and current compensating circuit, the offset voltage of the op amp was reduced to less than 0.5mV.
{"title":"A high gain low offset amplifier with rail-to-rail inputs","authors":"Zhiying Zhang, Xiaobo Wu, Xiaolang Yan","doi":"10.1109/EDSSC.2005.1635303","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635303","url":null,"abstract":"To fit some applications like in Power Management IC (Integrated Circuit), ahigh gain low offset BiCMOS op amp was proposed in this paper. A complementary input stage was adopted to meet a rail-to-rail ICMR (Input Common-Mode Range). And a special circuit configuration was introduced into the rail-to-rail amplifier to keep its gain constant. Simulation showed that the variation of gmwas maintained within 2% over the whole input range. Meanwhile, by using bipolar input stage and current compensating circuit, the offset voltage of the op amp was reduced to less than 0.5mV.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116906130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635295
Tan Kok-Siang, M.S. Sulainian, Tan Soon-Hwei, M. Reaz, F. Mohd-Yasin
This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-μm CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ±1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.
本文提出了一种半速率5Gb/s时钟和数据恢复电路。数据的重定时是由线性PD完成的，它几乎没有为感兴趣的频带提供系统偏移。该电路采用0.18 μm CMOS工艺设计，有效面积为0.2 x 0.32 mm2。CDR的RMS抖动为±1.2 ps，峰间抖动为5ps。1.8 v电源的功耗为97mW。
{"title":"A 5Gbit/s CMOS Clock and Data Recovery Circuit","authors":"Tan Kok-Siang, M.S. Sulainian, Tan Soon-Hwei, M. Reaz, F. Mohd-Yasin","doi":"10.1109/EDSSC.2005.1635295","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635295","url":null,"abstract":"This paper presents a half-rate 5Gb/s clock and data recovery circuit. Retiming of data is done by the linear PD that provides practically no systematic offset for the frequency band of interest. The circuit was designed in a 0.18-μm CMOS process and occupies an active area of 0.2 x 0.32 mm2. The CDR exhibits an RMS jitter of ±1.2 ps and a peak-to-peak jitter of 5ps. The power dissipation is 97mW from a 1.8-V supply.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123176170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-19DOI: 10.1109/EDSSC.2005.1635211
Ru Huang, Yu Tian, Han Xiao, Weihai Bu, Chuguang Feng, M. Chan, Xing Zhang, Yangyuan Wang
In this paper two kinds of novel localized-SOI structure devices, named as Quasi-SOI MOSFET and source-drain -on-nothing(SDON)/source-drain-on-insulator (SDOI) MOSFET, are demonstrated which can combine the advantages of SOI and bulk substrates. In the Quasi-SOI structure with the source/drain regions quasi-surrounded with insulator and the channel region directly connected with the bulk substrate, short channel effects (SCE), parasitic capacitance and self-heating effects (SHE) can be effectively reduced. The problem of degraded mobility and increased threshold voltage due to ultra-thin body in UTB SOI MOSFET's can also be solved. A method to fabricate the Quasi-SOI MOSFET is put forward. Process-device co-simulation results further show good scaling capability and excellent heat dissipation of the Quasi-SOI devices. In the SDON/SDOI device with the recessed S/D extension regions and source-drain staying on the partially buried layers, the advantages of quasi-SOI MOSFET can be maintained with the parasitic capacitance further reduced and the fabrication technology basically compatible with the standard CMOS technology. The proposed two structures can be considered as good candidates for highly-scaled devices.
本文展示了两种新型局域化SOI结构器件，即准SOI MOSFET和无源漏极(SDON)/绝缘子漏极(SDOI) MOSFET，它们结合了SOI和块状衬底的优点。在源极/漏极区被绝缘体包围，沟道区与体基板直接相连的准soi结构中，可以有效地降低短沟道效应(SCE)、寄生电容和自热效应(SHE)。UTB SOI MOSFET的超薄体导致迁移率下降和阈值电压升高的问题也可以得到解决。提出了一种制备准soi MOSFET的方法。制程-器件联合仿真结果进一步表明，准soi器件具有良好的缩放性能和良好的散热性能。在嵌入S/D扩展区、源极漏极停留在部分埋置层的SDON/SDOI器件中，寄生电容进一步减小，且制造工艺与标准CMOS工艺基本兼容，保持了准soi MOSFET的优势。提出的两种结构可以被认为是高规模器件的良好候选者。
{"title":"Novel Localized-SOI MOSFET's Combining the Advantages of SOI and Bulk Substrates for Highly-Scaled Devices","authors":"Ru Huang, Yu Tian, Han Xiao, Weihai Bu, Chuguang Feng, M. Chan, Xing Zhang, Yangyuan Wang","doi":"10.1109/EDSSC.2005.1635211","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635211","url":null,"abstract":"In this paper two kinds of novel localized-SOI structure devices, named as Quasi-SOI MOSFET and source-drain -on-nothing(SDON)/source-drain-on-insulator (SDOI) MOSFET, are demonstrated which can combine the advantages of SOI and bulk substrates. In the Quasi-SOI structure with the source/drain regions quasi-surrounded with insulator and the channel region directly connected with the bulk substrate, short channel effects (SCE), parasitic capacitance and self-heating effects (SHE) can be effectively reduced. The problem of degraded mobility and increased threshold voltage due to ultra-thin body in UTB SOI MOSFET's can also be solved. A method to fabricate the Quasi-SOI MOSFET is put forward. Process-device co-simulation results further show good scaling capability and excellent heat dissipation of the Quasi-SOI devices. In the SDON/SDOI device with the recessed S/D extension regions and source-drain staying on the partially buried layers, the advantages of quasi-SOI MOSFET can be maintained with the parasitic capacitance further reduced and the fabrication technology basically compatible with the standard CMOS technology. The proposed two structures can be considered as good candidates for highly-scaled devices.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129969801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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