Pub Date : 2022-08-01DOI: 10.31399/asm.edfa.2022-3.p004
David Potts, S. Hildreth, Binod Kumar G. Nair
Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance structure under which different physical mechanisms exhibit varying sensitivities to site-to-site, wafer-to-wafer, and lot-to-lot variations. This article uses Monte Carlo simulations to explore the impacts these hierarchical variance components can exert on perceptions of WET performance.
{"title":"Impacts of Nested Variance Components on Semiconductor Electrical Test Sampling","authors":"David Potts, S. Hildreth, Binod Kumar G. Nair","doi":"10.31399/asm.edfa.2022-3.p004","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-3.p004","url":null,"abstract":"\u0000 Inline wafer electrical testing (WET) offers an early read on semiconductor manufacturing processes via measurements taken on test structures placed throughout the wafer. Interpreting the data can be challenging, however. In many cases, only a sample of the test sites are monitored in production. Complex manufacturing requirements further complicate the problem because some operations are iteratively executed within subregions across a given wafer, while others are run on the entire wafer at once, and still others are applied to wafers in batches. This results in a nested variance structure under which different physical mechanisms exhibit varying sensitivities to site-to-site, wafer-to-wafer, and lot-to-lot variations. This article uses Monte Carlo simulations to explore the impacts these hierarchical variance components can exert on perceptions of WET performance.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116935879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.31399/asm.edfa.2022-3.p032
S. Lau, S. Gul, J. Gelb, Tianzhu Qin, G. Zan, Katie Matusik, D. Vine, S. Lewis, W. Yun
This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.
{"title":"High Speed X-ray Tomography with Submicron Resolution for FA and Reverse Engineering of Packages, PCBs, and 300 mm Wafers","authors":"S. Lau, S. Gul, J. Gelb, Tianzhu Qin, G. Zan, Katie Matusik, D. Vine, S. Lewis, W. Yun","doi":"10.31399/asm.edfa.2022-3.p032","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-3.p032","url":null,"abstract":"\u0000 This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115143580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-01DOI: 10.31399/asm.edfa.2022-3.p024
R. Coq Germanicus, U. Lüders
This article demonstrates the value of atomic force microscopes, particularly the different electrical modes, for characterizing complex microelectronic structures. It presents experimental results obtained from deep trench isolation (DTI) structures using SCM and SSRM analysis with emphasis on the voltage applied by the AFM. From these measurements, a failure analysis workflow is proposed that facilitates AFM voltage optimization to reveal the structure of cross-sectioned samples, make comparisons, and determine the underlying cause of failures.
{"title":"Electrical Characterizations Based on AFM: SCM and SSRM Measurements with a Multidimensional Approach","authors":"R. Coq Germanicus, U. Lüders","doi":"10.31399/asm.edfa.2022-3.p024","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-3.p024","url":null,"abstract":"\u0000 This article demonstrates the value of atomic force microscopes, particularly the different electrical modes, for characterizing complex microelectronic structures. It presents experimental results obtained from deep trench isolation (DTI) structures using SCM and SSRM analysis with emphasis on the voltage applied by the AFM. From these measurements, a failure analysis workflow is proposed that facilitates AFM voltage optimization to reveal the structure of cross-sectioned samples, make comparisons, and determine the underlying cause of failures.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125541601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The failure of a white LED backlight module in a portable computer illustrates the challenges that component and system suppliers must overcome in order to determine root-cause failure mechanisms and take corrective actions that address the problem.
{"title":"Challenges for System Supplier Failure Analysis on Subsystem Components","authors":"Xuming Deng, Weidong Huang, Changho Yu, Xiongjian Wu, Yang Xu, Xiaole Zhao, Qing Gu","doi":"10.31399/asm.edfa.2022-2.p004","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-2.p004","url":null,"abstract":"\u0000 The failure of a white LED backlight module in a portable computer illustrates the challenges that component and system suppliers must overcome in order to determine root-cause failure mechanisms and take corrective actions that address the problem.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129224469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.31399/asm.edfa.2022-2.p012
A. Rummel, Andrew Smith
This article discusses the challenges associated with nanoprobing advanced technology node devices and explains how to optimize SEM images for beam voltages of 100 eV or less.
{"title":"Nanoprobing at Low Beam Energy, Addressing Current and Future Nodes","authors":"A. Rummel, Andrew Smith","doi":"10.31399/asm.edfa.2022-2.p012","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-2.p012","url":null,"abstract":"\u0000 This article discusses the challenges associated with nanoprobing advanced technology node devices and explains how to optimize SEM images for beam voltages of 100 eV or less.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131974983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.31399/asm.edfa.2022-2.p024
Aslam A. Khan, Chengjie Xi, N. Asadizanjani
Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.
{"title":"Physical Security Roadmap for Heterogeneous Integration Technology","authors":"Aslam A. Khan, Chengjie Xi, N. Asadizanjani","doi":"10.31399/asm.edfa.2022-2.p024","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-2.p024","url":null,"abstract":"\u0000 Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.31399/asm.edfa.2022-2.p051
N. Antoniou
Failure analysis has become a critical enabler of semiconductor technology innovations. Logic and memory scaling continues at an unabated pace with new materials and transistor architectures being introduced. The integration of advanced packaging technologies like chiplets, 2.5D, and 3D in mainstream devices is exploding. To address these challenges, a new industry-wide FA Technology Roadmap was created and approved by the EDFAS Board in 2020. This column discusses the planned next steps in the Roadmap project.
{"title":"The EDFAS FA Technology Roadmap—Advancing Our Community","authors":"N. Antoniou","doi":"10.31399/asm.edfa.2022-2.p051","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-2.p051","url":null,"abstract":"\u0000 Failure analysis has become a critical enabler of semiconductor technology innovations. Logic and memory scaling continues at an unabated pace with new materials and transistor architectures being introduced. The integration of advanced packaging technologies like chiplets, 2.5D, and 3D in mainstream devices is exploding. To address these challenges, a new industry-wide FA Technology Roadmap was created and approved by the EDFAS Board in 2020. This column discusses the planned next steps in the Roadmap project.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127109472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-01DOI: 10.31399/asm.edfa.2022-2.p018
N. Adhikari, P. Kaszuba, Gaitan Mathieu, D. Dahanayaka
Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.
{"title":"A Strategic Review of Novel Sample Preparation Method for Dopant Profiling of Advanced Node FinFET Devices with Scanning Capacitance Microscopy","authors":"N. Adhikari, P. Kaszuba, Gaitan Mathieu, D. Dahanayaka","doi":"10.31399/asm.edfa.2022-2.p018","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-2.p018","url":null,"abstract":"\u0000 Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133545072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.31399/asm.edfa.2022-1.p033
The 47th International Symposium for Testing and Failure Analysis (ISTFA 2021) was held in Phoenix, Ariz., from October 31 to November 4, 2011. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User Group meetings, and the Women in Electronics Failure Analysis (WEFA) event.
{"title":"ISTFA 2021 Highlights","authors":"","doi":"10.31399/asm.edfa.2022-1.p033","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-1.p033","url":null,"abstract":"\u0000 The 47th International Symposium for Testing and Failure Analysis (ISTFA 2021) was held in Phoenix, Ariz., from October 31 to November 4, 2011. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User Group meetings, and the Women in Electronics Failure Analysis (WEFA) event.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128660567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.31399/asm.edfa.2022-1.p017
Yasuo Cho
Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, dC/dV-V, and DLTS data from SiO2/SiC interface samples.
{"title":"Simultaneous Local Capacitance-Voltage Profiling and Deep Level Transient Spectroscopy Using Time-Resolved Scanning Nonlinear Dielectric Microscopy","authors":"Yasuo Cho","doi":"10.31399/asm.edfa.2022-1.p017","DOIUrl":"https://doi.org/10.31399/asm.edfa.2022-1.p017","url":null,"abstract":"\u0000 Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, dC/dV-V, and DLTS data from SiO2/SiC interface samples.","PeriodicalId":431761,"journal":{"name":"EDFA Technical Articles","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125754358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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