Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734663
H. Lue, S. Lai, T. Hsu, Y. Hsiao, P. Du, Szu-Yu Wang, K. Hsieh, R. Liu, Chih-Yuan Lu
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in determining the programming/erasing and reliability characteristics. Erase saturation and incremental-step-pulse programming (ISPP) characteristics are strongly affected by the STI edge effects. Our analysis of recent progress provides a clear understanding to charge-trapping NAND devices and serves as a guideline for future development.
{"title":"A critical review of charge-trapping NAND flash devices","authors":"H. Lue, S. Lai, T. Hsu, Y. Hsiao, P. Du, Szu-Yu Wang, K. Hsieh, R. Liu, Chih-Yuan Lu","doi":"10.1109/ICSICT.2008.4734663","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734663","url":null,"abstract":"This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in determining the programming/erasing and reliability characteristics. Erase saturation and incremental-step-pulse programming (ISPP) characteristics are strongly affected by the STI edge effects. Our analysis of recent progress provides a clear understanding to charge-trapping NAND devices and serves as a guideline for future development.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132135045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734953
Zhen Liu, S. Jia, Y. Wang, L. Ji, Xing Zhang
An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.
{"title":"Efficient encoding scheme for folding ADC","authors":"Zhen Liu, S. Jia, Y. Wang, L. Ji, Xing Zhang","doi":"10.1109/ICSICT.2008.4734953","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734953","url":null,"abstract":"An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125329694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734571
T. Fjeldly, H. Berli
Precise two-dimensional current and capacitance modeling of short-channel, nanoscale multigate MOSFETs is presented. The model covers a wide range of operating regimes, geometries and material combinations. The modeling in the subthreshold regime is based on conformal mapping techniques. In moderate to strong inversion, we obtain self-consistent results based on the 2-D Poisson¿s equation. The results are in excellent agreement with numerical simulations.
{"title":"2-D modeling of nanoscale multigate MOSFETs","authors":"T. Fjeldly, H. Berli","doi":"10.1109/ICSICT.2008.4734571","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734571","url":null,"abstract":"Precise two-dimensional current and capacitance modeling of short-channel, nanoscale multigate MOSFETs is presented. The model covers a wide range of operating regimes, geometries and material combinations. The modeling in the subthreshold regime is based on conformal mapping techniques. In moderate to strong inversion, we obtain self-consistent results based on the 2-D Poisson¿s equation. The results are in excellent agreement with numerical simulations.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126311368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734805
Pan Xiaofeng, Shen Ya
This paper describes design consideration and performance of a Ku-band monolithic phase shifter utilizing 0.25-¿m PHEMT switches. The developed 6-bit phase shifter demonstrates an overall phase deviation less than 1.5 rms and an insertion loss variation less than 0.35 dB rms from 12 to 15 GHz. For all 64 states, the insertion loss is measured to be 9 dB and the VSWR is less than 1.4. The chip size of the monolithic phase shifter is 3.1 mm × 1 mm.
本文介绍了一种采用0.25 m PHEMT开关的ku波段单片移相器的设计思想和性能。开发的6位移相器显示，在12至15 GHz范围内，总体相位偏差小于1.5 rms，插入损耗变化小于0.35 dB rms。在所有64种状态下，测量到的插入损耗为9 dB，驻波比小于1.4。单片移相器的芯片尺寸为3.1 mm × 1mm。
{"title":"Design and performance of a Ku-band 6-bit MMIC phase-shifter","authors":"Pan Xiaofeng, Shen Ya","doi":"10.1109/ICSICT.2008.4734805","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734805","url":null,"abstract":"This paper describes design consideration and performance of a Ku-band monolithic phase shifter utilizing 0.25-¿m PHEMT switches. The developed 6-bit phase shifter demonstrates an overall phase deviation less than 1.5 rms and an insertion loss variation less than 0.35 dB rms from 12 to 15 GHz. For all 64 states, the insertion loss is measured to be 9 dB and the VSWR is less than 1.4. The chip size of the monolithic phase shifter is 3.1 mm × 1 mm.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126539892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735106
Huikai Xie
Micromirrors with large scan ranges, large aperture sizes, fast speeds, low voltages and low cost are needed for optical switching, displays and biomedical imaging, but it is very challenging to simultaneously meet all the requirements. This paper introduces electrothermal bimorph based micromirrors that can overcome the challenge. For example, a large-vertical-displacement (LVD) micromirror scans 0.7 mm vertically at less than 25 Vdc. A lateral-shift-free (LSF) LVD generates a piston motion of 0.6 mm and scans more than 30° about two axes at less than 8 Vdc. An inverted-series-connected (ISC) micromirror scans ±30° about two axes with no rotation axis shifts. All these mirrors have an optical aperture of 1 mm. Their resonant frequencies range from 300 Hz to 2 kHz. Some of these micromirrors have been applied in biomedical imaging applications.
{"title":"Large-range large-aperture MEMS micromirrors for biomedical imaging applications","authors":"Huikai Xie","doi":"10.1109/ICSICT.2008.4735106","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735106","url":null,"abstract":"Micromirrors with large scan ranges, large aperture sizes, fast speeds, low voltages and low cost are needed for optical switching, displays and biomedical imaging, but it is very challenging to simultaneously meet all the requirements. This paper introduces electrothermal bimorph based micromirrors that can overcome the challenge. For example, a large-vertical-displacement (LVD) micromirror scans 0.7 mm vertically at less than 25 Vdc. A lateral-shift-free (LSF) LVD generates a piston motion of 0.6 mm and scans more than 30° about two axes at less than 8 Vdc. An inverted-series-connected (ISC) micromirror scans ±30° about two axes with no rotation axis shifts. All these mirrors have an optical aperture of 1 mm. Their resonant frequencies range from 300 Hz to 2 kHz. Some of these micromirrors have been applied in biomedical imaging applications.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734874
Jia-you Song, Xiao-Yang Liu, Zhigong Wang
This paper describes the design of a polyphase filter in GSM receiver with low-IF topologies, using the circuit scheme of active-RC with the performance of single chip integrated. Based on TSMC 0.18 ¿m CMOS process, the Spectre simulation results indicate that the filter is centered at 110 kHz with 200 kHz of bandwidth. It has a voltage gain of about 30 dB, an image rejection ratio of about 38 dB. The power consumption is 4.2 mW under a 3 V power supply.
{"title":"Design of an active polyphase filter in GSM receiver with low-IF topologies","authors":"Jia-you Song, Xiao-Yang Liu, Zhigong Wang","doi":"10.1109/ICSICT.2008.4734874","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734874","url":null,"abstract":"This paper describes the design of a polyphase filter in GSM receiver with low-IF topologies, using the circuit scheme of active-RC with the performance of single chip integrated. Based on TSMC 0.18 ¿m CMOS process, the Spectre simulation results indicate that the filter is centered at 110 kHz with 200 kHz of bandwidth. It has a voltage gain of about 30 dB, an image rejection ratio of about 38 dB. The power consumption is 4.2 mW under a 3 V power supply.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114170060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734867
W. Yan, C. Park
With a simple analysis of phase noise in voltage-controlled oscillators, a 2.4 GHz CMOS LC VCO is designed in 0.18 ¿m CMOS technology. The proposed VCO uses three filters to remove noise from the tail current source, the reference current source, and the output node of VCO core. The VCO has a tuning range from 2.29 GHz to 2.59 GHz, while the VCO core draws 3 mA of current from 1.8 V power supply. The achieved phase noise is -138 dBc/Hz at 3 MHz offset and -103.1 dBc/Hz at 100 kHz offset frequency.
{"title":"Filtering technique to lower phase noise for 2.4GHz CMOS VCO","authors":"W. Yan, C. Park","doi":"10.1109/ICSICT.2008.4734867","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734867","url":null,"abstract":"With a simple analysis of phase noise in voltage-controlled oscillators, a 2.4 GHz CMOS LC VCO is designed in 0.18 ¿m CMOS technology. The proposed VCO uses three filters to remove noise from the tail current source, the reference current source, and the output node of VCO core. The VCO has a tuning range from 2.29 GHz to 2.59 GHz, while the VCO core draws 3 mA of current from 1.8 V power supply. The achieved phase noise is -138 dBc/Hz at 3 MHz offset and -103.1 dBc/Hz at 100 kHz offset frequency.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4735107
Zhihong Li, Xu Ji, Lu Wang, Jianzhong Xi
A promising combination of the semiconductor integrated system-on-a-chip (SoC) with the lab-on-a-chip (LOC) is brought in this paper. In this paper, we propose a new technology which enables monolithic integration of the self-assembled biological system, the MEMS structure, the microfluidic system, and CMOS electronic circuits together. Utilizing this approach, more functionality is introduced into the SoC, while the LOC becomes more intelligent and controllable. A post-CMOS fabrication approach that meets the requirements is demonstrated to validate the idea.
{"title":"Merging SoC and LOC together","authors":"Zhihong Li, Xu Ji, Lu Wang, Jianzhong Xi","doi":"10.1109/ICSICT.2008.4735107","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4735107","url":null,"abstract":"A promising combination of the semiconductor integrated system-on-a-chip (SoC) with the lab-on-a-chip (LOC) is brought in this paper. In this paper, we propose a new technology which enables monolithic integration of the self-assembled biological system, the MEMS structure, the microfluidic system, and CMOS electronic circuits together. Utilizing this approach, more functionality is introduced into the SoC, while the LOC becomes more intelligent and controllable. A post-CMOS fabrication approach that meets the requirements is demonstrated to validate the idea.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114211614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734564
F. Crupi, P. Magnone, G. Iannaccone, G. Giusi, C. Pace, E. Simoen, C. Claeys
In this work we propose an analytical model for the gate current 1/f noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current 1/f noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.
{"title":"Modeling the gate current 1/f noise and its application to advanced CMOS devices","authors":"F. Crupi, P. Magnone, G. Iannaccone, G. Giusi, C. Pace, E. Simoen, C. Claeys","doi":"10.1109/ICSICT.2008.4734564","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734564","url":null,"abstract":"In this work we propose an analytical model for the gate current 1/f noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current 1/f noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115979477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-30DOI: 10.1109/ICSICT.2008.4734924
Jeong Beom Kim
This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.
{"title":"A CMOS quaternary-to-binary logic decoder","authors":"Jeong Beom Kim","doi":"10.1109/ICSICT.2008.4734924","DOIUrl":"https://doi.org/10.1109/ICSICT.2008.4734924","url":null,"abstract":"This paper proposes a quaternary-to-binary logic decoder using current-mode multiple-valued logic (MVL) CMOS circuits. The circuit is achieved a device reduction of 23.5%, an interconnection reduction of 25.0%, and a power-delay-product reduction of 43.1%. Therefore, this circuit is superior to the previous circuit in both the circuit occupied area and the reliability. The validity and effectiveness of the proposed circuits are verified through the HSPICE under Hynix 0.25 um standard CMOS technology with the supply voltage 2.5 V.","PeriodicalId":436457,"journal":{"name":"2008 9th International Conference on Solid-State and Integrated-Circuit Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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