Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012134
C. Brej, D. Edwards
Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. This paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs. This is shown to be highly advantageous in cases where the previous style performed poorly. Because the two styles can be mixed, the designs no longer suffer from very poor performance of some QDI constructions.
{"title":"Forward and backward guarding in early output logic","authors":"C. Brej, D. Edwards","doi":"10.1109/DDECS.2009.5012134","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012134","url":null,"abstract":"Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologies using this system have always yielded very slow designs. Early output logic is a method which aims to improve the performance of QDI circuits without decreasing their robustness. In order to force QDI restrictions on early output circuits a form of guarding is necessary. This paper presents a new form of guarding which allows partial stage completion allowing desynchronisation of inputs. This is shown to be highly advantageous in cases where the previous style performed poorly. Because the two styles can be mixed, the designs no longer suffer from very poor performance of some QDI constructions.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"60 1","pages":"226-229"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85339376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012101
I. Lemberski, P. Fiser
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.
{"title":"Asynchronous two-level logic of reduced cost","authors":"I. Lemberski, P. Fiser","doi":"10.1109/DDECS.2009.5012101","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012101","url":null,"abstract":"We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"42 1","pages":"68-73"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75396007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012090
J. Brenkus, V. Stopjaková, Ronny Vanhooren, A. Chichkov
An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.
{"title":"Comparison of different test strategies on a mixed-signal circuit","authors":"J. Brenkus, V. Stopjaková, Ronny Vanhooren, A. Chichkov","doi":"10.1109/DDECS.2009.5012090","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012090","url":null,"abstract":"An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"1 1","pages":"16-19"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84746013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012137
Krzysztof Marcinek, A. W. Luczyk, W. Pleskacz
Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.
{"title":"Enhanced LEON3 core for superscalar processing","authors":"Krzysztof Marcinek, A. W. Luczyk, W. Pleskacz","doi":"10.1109/DDECS.2009.5012137","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012137","url":null,"abstract":"Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"20 1","pages":"238-241"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89692206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012091
E. D. Mulder, W. Aerts, B. Preneel, I. Verbauwhede, G. Vandenbosch
This paper reports on the design and implementation of a class E push-pull amplifier in order to increase the reading range of an ISO-14443A RFID system. With the aid of classical design formulas and some alterations due to parasitic and intrinsic capacitances, a working implementation was made that can provide the loop with an amplified modulated current wave.
{"title":"Case Study : A class E power amplifier for ISO-14443A","authors":"E. D. Mulder, W. Aerts, B. Preneel, I. Verbauwhede, G. Vandenbosch","doi":"10.1109/DDECS.2009.5012091","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012091","url":null,"abstract":"This paper reports on the design and implementation of a class E push-pull amplifier in order to increase the reading range of an ISO-14443A RFID system. With the aid of classical design formulas and some alterations due to parasitic and intrinsic capacitances, a working implementation was made that can provide the loop with an amplified modulated current wave.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"17 1","pages":"20-23"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87644265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012138
Y. Berg, O. Mirmotahari
In this paper we present a continuous time ultra low voltage current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 250mV and in continuous time. The current mirror performs an auto zero (chopper) function. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process. We have included an ultra low voltage current mirror with adjustable current levels.
{"title":"Ultra low-voltage switched current mirror","authors":"Y. Berg, O. Mirmotahari","doi":"10.1109/DDECS.2009.5012138","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012138","url":null,"abstract":"In this paper we present a continuous time ultra low voltage current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 250mV and in continuous time. The current mirror performs an auto zero (chopper) function. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process. We have included an ultra low voltage current mirror with adjustable current levels.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"58 1","pages":"242-245"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82901957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.
{"title":"0.5V 160-MHz 260uW all digital phase-locked loop","authors":"Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng","doi":"10.1109/DDECS.2009.5012125","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012125","url":null,"abstract":"A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"42 1","pages":"186-193"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90887172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012100
T. Panhofer, W. Friesenbichler, M. Delvai
Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In particular for applications with long mission times and where no repair is possible, complex fault tolerance mechanisms are required, leading to a dramatic increase of design and system costs. Runtime reconfiguration seems to be a promising way to obtain a circuit which is able to handle these challenges. In previous papers we presented a self-healing approach based on asynchronous Four-State Logic (FSL) and using reconfigurable circuit elements, called Self-Healing Cells (SHCs). These SHCs allow to bypass defect resources and to recover from multiple permanent faults. While the combinational logic can be easily reconfigured this way, the application of SHCs in an asynchronous pipeline requires special treatment of the handshake signals. In this paper we present a self-healing pipeline architecture and analyse different SHC architectures with respect to resource occupation, fault tolerance and reconfiguration speed.
{"title":"Optimization concepts for self-healing asynchronous circuits","authors":"T. Panhofer, W. Friesenbichler, M. Delvai","doi":"10.1109/DDECS.2009.5012100","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012100","url":null,"abstract":"Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In particular for applications with long mission times and where no repair is possible, complex fault tolerance mechanisms are required, leading to a dramatic increase of design and system costs. Runtime reconfiguration seems to be a promising way to obtain a circuit which is able to handle these challenges. In previous papers we presented a self-healing approach based on asynchronous Four-State Logic (FSL) and using reconfigurable circuit elements, called Self-Healing Cells (SHCs). These SHCs allow to bypass defect resources and to recover from multiple permanent faults. While the combinational logic can be easily reconfigured this way, the application of SHCs in an asynchronous pipeline requires special treatment of the handshake signals. In this paper we present a self-healing pipeline architecture and analyse different SHC architectures with respect to resource occupation, fault tolerance and reconfiguration speed.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"67 1","pages":"62-67"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74608885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. This paper presents a technique for improving clock gating by optimizing the enable functions. The problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. Then the optimal set of enable functions is found with partition method. This paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. The experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.
{"title":"Improve clock gating through power-optimal enable function selection","authors":"Juanjuan Chen, Xing Wei, Yunjian Jiang, Qiang Zhou","doi":"10.1109/DDECS.2009.5012094","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012094","url":null,"abstract":"Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved. This paper presents a technique for improving clock gating by optimizing the enable functions. The problem of improving clock gating is formulated as finding the optimal set of enable functions in the shared logic cone that leads to best power reduction on flip flops. First, enable functions are identified by random simulation and SAT. Then the optimal set of enable functions is found with partition method. This paper demonstrates the effectiveness of the approach through testing on MCNC benchmarks and industrial circuits. The experimental results show that the algorithm will get as much power saving as 3 times of that of the original clock gating circuits, and all benchmarks can run in tens of seconds.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"12 1 1","pages":"30-33"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76906721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-15DOI: 10.1109/DDECS.2009.5012087
Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann
An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.
{"title":"An SOC platform for ADC test and measurement","authors":"Brendan Mullane, Vincent O’Brien, Ciaran MacNamee, Thomas Fleischmann","doi":"10.1109/DDECS.2009.5012087","DOIUrl":"https://doi.org/10.1109/DDECS.2009.5012087","url":null,"abstract":"An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.","PeriodicalId":6325,"journal":{"name":"2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems","volume":"45 1","pages":"4-7"},"PeriodicalIF":0.0,"publicationDate":"2009-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74489745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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