Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243809
A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, T. Yabe
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.
{"title":"A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs","authors":"A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, F. Tachibana, Y. Niki, S. Sasaki, T. Yabe","doi":"10.1109/VLSIC.2012.6243809","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243809","url":null,"abstract":"A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monitors all the bitline delays and generates the worst timing from the delay distribution. The proposed timing generators have been implemented in 28nm and 40nm SRAMs. The 47% access time reduction has been confirmed in measured results.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84079231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243793
S. Mitra, Jiawei Xu, Akinori Matsumoto, K. Makinwa, C. Hoof, R. Yazicioglu
A 700μW 8-channel active-electrode (AE) based EEG monitoring system is presented. The complete system consists of 9 AEs and a back-end analog signal processor. It is capable of continuously recording EEG signals and electrode-tissue contact impedance (ETI). The EEG channels have 1.2GΩ input impedance, 1.75μVrms noise (0.5-100Hz), 84dB CMRR, and can reject ±250mV of electrode offset, while consuming less than <;87μW (including ETI measurement). The system facilitates ambulatory use and patient comfort, while delivering high quality EEG signals.
{"title":"A 700µW 8-channel EEG/contact-impedance acquisition system for dry-electrodes","authors":"S. Mitra, Jiawei Xu, Akinori Matsumoto, K. Makinwa, C. Hoof, R. Yazicioglu","doi":"10.1109/VLSIC.2012.6243793","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243793","url":null,"abstract":"A 700μW 8-channel active-electrode (AE) based EEG monitoring system is presented. The complete system consists of 9 AEs and a back-end analog signal processor. It is capable of continuously recording EEG signals and electrode-tissue contact impedance (ETI). The EEG channels have 1.2GΩ input impedance, 1.75μVrms noise (0.5-100Hz), 84dB CMRR, and can reject ±250mV of electrode offset, while consuming less than <;87μW (including ETI measurement). The system facilitates ambulatory use and patient comfort, while delivering high quality EEG signals.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90834751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243836
Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, S. Goto
An H.264/AVC intra-frame video encoder is implemented in 65 nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991 Mpixels/s for 7680×4320 p 60 fps video, 9.4× to 32× faster than previous designs. The encoder also incorporates a 1.41 Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2 mW at 0.8 V and 9 MHz.
在65nm CMOS中实现了H.264/AVC帧内视频编码器。凭借高效的帧内预测设计，对于7680×4320 p 60 fps视频，其最大吞吐量达到1991 Mpixels/s，比以前的设计快9.4到32倍。编码器还集成了1.41 gbps的CABAC架构，增强了31%。此外，该设计的并行度高，硬件效率高，能耗低。1080p30编码在0.8 V和9 MHz时仅耗散2 mW。
{"title":"A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC","authors":"Dajiang Zhou, Gang He, Wei Fei, Zhixiang Chen, Jinjia Zhou, S. Goto","doi":"10.1109/VLSIC.2012.6243836","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243836","url":null,"abstract":"An H.264/AVC intra-frame video encoder is implemented in 65 nm CMOS. With an efficient intra prediction design, its maximum throughput reaches 1991 Mpixels/s for 7680×4320 p 60 fps video, 9.4× to 32× faster than previous designs. The encoder also incorporates a 1.41 Gbins/s CABAC architecture that has been enhanced by 31%. Moreover, low energy consumption is achieved by the high parallelism and hardware efficiency of this design. 1080p30 encoding dissipates only 2 mW at 0.8 V and 9 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89421309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243776
A. Paidimarri, P. Nadeau, P. Mercier, A. Chandrakasan
A 2.4GHz TX in 65nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132dBc/Hz phase noise at 1MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈-10dBm, a fully-integrated PA implements 7.5dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440pJ/bit at 1Mb/s.
{"title":"A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PA","authors":"A. Paidimarri, P. Nadeau, P. Mercier, A. Chandrakasan","doi":"10.1109/VLSIC.2012.6243776","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243776","url":null,"abstract":"A 2.4GHz TX in 65nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132dBc/Hz phase noise at 1MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈-10dBm, a fully-integrated PA implements 7.5dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440pJ/bit at 1Mb/s.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89839019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243851
Yi Zhang, Hai-jin Chen, D. Ma
A CMOS RGB LED driver is presented, using cost-effective, single-converter, reconfigurable structure to bias RGB color LEDs accurately and adaptively. Automatic ΔVO detection and fast VO-hopping techniques are proposed, achieving 198-ns/V VO-hopping speed on 0.35μm CMOS. This is at least one order faster than the state-of-arts. While predictive peak current control and burst-mode operation are employed for robust operation, switching frequency is still stabilized around 1MHz by an adaptive off-timer for switching noise spectrum control. The driver consumes 8.6 times less headroom power than its fixed-output counterparts.
{"title":"A 198-ns/V VO-hopping reconfigurable RGB LED driver with automatic ΔVO detection and quasi-constant-frequency predictive peak current control","authors":"Yi Zhang, Hai-jin Chen, D. Ma","doi":"10.1109/VLSIC.2012.6243851","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243851","url":null,"abstract":"A CMOS RGB LED driver is presented, using cost-effective, single-converter, reconfigurable structure to bias RGB color LEDs accurately and adaptively. Automatic ΔVO detection and fast VO-hopping techniques are proposed, achieving 198-ns/V VO-hopping speed on 0.35μm CMOS. This is at least one order faster than the state-of-arts. While predictive peak current control and burst-mode operation are employed for robust operation, switching frequency is still stabilized around 1MHz by an adaptive off-timer for switching noise spectrum control. The driver consumes 8.6 times less headroom power than its fixed-output counterparts.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78662994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243835
Yi-Min Tsai, Tien-Ju Yang, Chih-Chung Tsai, K. Huang, Liang-Gee Chen
A machine-learning based intelligent vision SoC implemented on a 9.3 mm2 die in a 40nm CMOS process is presented. The architecture realizes 140 meters active distance at 60fps and 60 meters at 300fps under Quad-VGA (1280×960) resolution while maintaining above 90% detection rate for versatile automotive applications. The system supports 64 object tracking and prediction. It raises 1.62× improvement on power efficiency and at least 1.79× increase on frame rate with the proposed knowledge-based tracking processor. The chip achieves 354.2fps/W and 3.01TOPS/W power efficiency with 69mW average power consumption.
{"title":"A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applications","authors":"Yi-Min Tsai, Tien-Ju Yang, Chih-Chung Tsai, K. Huang, Liang-Gee Chen","doi":"10.1109/VLSIC.2012.6243835","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243835","url":null,"abstract":"A machine-learning based intelligent vision SoC implemented on a 9.3 mm2 die in a 40nm CMOS process is presented. The architecture realizes 140 meters active distance at 60fps and 60 meters at 300fps under Quad-VGA (1280×960) resolution while maintaining above 90% detection rate for versatile automotive applications. The system supports 64 object tracking and prediction. It raises 1.62× improvement on power efficiency and at least 1.79× increase on frame rate with the proposed knowledge-based tracking processor. The chip achieves 354.2fps/W and 3.01TOPS/W power efficiency with 69mW average power consumption.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87047393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243842
Gerry Taylor, I. Galton
A 0.075 mm2 65 nm CMOS VCO-based ΔΣ modulator ADC that operates from a single 0.9-1.2 V supply is presented. Its sample-rate, fs, is tunable from 1.3-2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR + 10 log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.
{"title":"A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB","authors":"Gerry Taylor, I. Galton","doi":"10.1109/VLSIC.2012.6243842","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243842","url":null,"abstract":"A 0.075 mm<sup>2</sup> 65 nm CMOS VCO-based ΔΣ modulator ADC that operates from a single 0.9-1.2 V supply is presented. Its sample-rate, f<sub>s</sub>, is tunable from 1.3-2.4 GHz over which the SNDR spans 70-75 dB, the bandwidth spans 5-37.5 MHz, and the minimum SNDR + 10 log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90915350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243777
V. Majidzadeh, A. Schmid, Y. Leblebici, J. Rabaey
A pulsed UWB transmitter (Tx) using finite impulse response synthesis of the raised-cosine pulse is presented. Symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) for aggressive duty-cycling of the Tx. The chip is fabricated with 90nm CMOS technology and consumes 540 μW from 1 V power supply resulting in 45 pJ/bit energy efficiency with -26 dBm of output power.
{"title":"An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements","authors":"V. Majidzadeh, A. Schmid, Y. Leblebici, J. Rabaey","doi":"10.1109/VLSIC.2012.6243777","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243777","url":null,"abstract":"A pulsed UWB transmitter (Tx) using finite impulse response synthesis of the raised-cosine pulse is presented. Symmetric pulse combining technique is proposed to reduce the number of power amplifier elements by half. A novel all-digital delay locked loop (AD-DLL) serves as an 8-array pulse position modulator (PPM) for aggressive duty-cycling of the Tx. The chip is fabricated with 90nm CMOS technology and consumes 540 μW from 1 V power supply resulting in 45 pJ/bit energy efficiency with -26 dBm of output power.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86518893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243845
H. Partovi, A. Yeung, L. Ravezzi, M. Horowitz
This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.
{"title":"A 3-stage Pseudo Single-phase Flip-flop family","authors":"H. Partovi, A. Yeung, L. Ravezzi, M. Horowitz","doi":"10.1109/VLSIC.2012.6243845","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243845","url":null,"abstract":"This paper presents an energy-efficient 3-stage Pseudo Single-phase family of Flip-flops (PSPFF) targeted for use in a 3GHz microprocessor in a 40nm, 0.9V CMOS technology. With latencies in line with the fast pulsed-latch and an average switching energy comparable to the master-slave flip-flop, PSPFF achieves an energy-delay product (EDP) which is 42% and 24% lower than the pulsed-latch and the master-slave flip-flop respectively. Measurement results confirm an improvement of at least 300MHz in operating frequency when using the PSPFF in place of the master-slave flip-flop.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87309970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243812
T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura
A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.
{"title":"A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS","authors":"T. Takemoto, H. Yamashita, Takehito Kamimura, F. Yuki, N. Masuda, H. Toyoda, N. Chujo, K. Kogo, Yong Lee, S. Tsuji, S. Nishimura","doi":"10.1109/VLSIC.2012.6243812","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243812","url":null,"abstract":"A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential LDD are proposed. The noise canceller decreases power-supply variations by 98%. Total power consumption was only 2.2W.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83961523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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