Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243773
Colin Weltin-Wu, Y. Tsividis
A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.
{"title":"An event-driven, alias-free ADC with signal-dependent resolution","authors":"Colin Weltin-Wu, Y. Tsividis","doi":"10.1109/VLSIC.2012.6243773","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243773","url":null,"abstract":"A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"30 1","pages":"28-29"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90565847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243771
Z. Tan, Youngcheol Chae, R. Daamen, A. Humbert, Youri Ponomarev, M. Pertijs
A CMOS fully-integrated humidity sensor for a RFID sensor platform has been realized in 0.16μm CMOS technology. It consists of a top-metal finger capacitor, covered by a humidity-sensitive polyimide layer, and an energy-efficient inverter-based capacitance-to-digital converter (CDC). Measurements show that the CDC performs a 12.5-bit conversion in 0.8ms while consuming only 8.6μA from a 1.2V supply. Together with the co-integrated humidity sensor, this translates into a resolution of 0.05% RH in the range of 30% RH to 90% RH, at an energy consumption of only 8.3nJ per measurement.
{"title":"A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applications","authors":"Z. Tan, Youngcheol Chae, R. Daamen, A. Humbert, Youri Ponomarev, M. Pertijs","doi":"10.1109/VLSIC.2012.6243771","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243771","url":null,"abstract":"A CMOS fully-integrated humidity sensor for a RFID sensor platform has been realized in 0.16μm CMOS technology. It consists of a top-metal finger capacitor, covered by a humidity-sensitive polyimide layer, and an energy-efficient inverter-based capacitance-to-digital converter (CDC). Measurements show that the CDC performs a 12.5-bit conversion in 0.8ms while consuming only 8.6μA from a 1.2V supply. Together with the co-integrated humidity sensor, this translates into a resolution of 0.05% RH in the range of 30% RH to 90% RH, at an energy consumption of only 8.3nJ per measurement.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"21 1","pages":"24-25"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87399271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243783
Jung‐Dong Park, Shinwon Kang, S. V. Thyagarajan, E. Alon, A. Niknejad
A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.
{"title":"A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication","authors":"Jung‐Dong Park, Shinwon Kang, S. V. Thyagarajan, E. Alon, A. Niknejad","doi":"10.1109/VLSIC.2012.6243783","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243783","url":null,"abstract":"A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"13 1","pages":"48-49"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90047640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243833
A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De
A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).
{"title":"A fully-digital phase-locked low dropout regulator in 32nm CMOS","authors":"A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De","doi":"10.1109/VLSIC.2012.6243833","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243833","url":null,"abstract":"A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"47 1","pages":"148-149"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82950439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243855
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, Seonghwan Cho
This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.
{"title":"A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier","authors":"KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, Seonghwan Cho","doi":"10.1109/VLSIC.2012.6243855","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243855","url":null,"abstract":"This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"3 1","pages":"192-193"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83550258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243766
Keng-Jan Hsiao
A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from -20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.
{"title":"A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation","authors":"Keng-Jan Hsiao","doi":"10.1109/VLSIC.2012.6243766","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243766","url":null,"abstract":"A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from -20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"85 1","pages":"14-15"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83471735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243788
N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.
{"title":"A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS","authors":"N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki","doi":"10.1109/VLSIC.2012.6243788","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243788","url":null,"abstract":"A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"106 1","pages":"58-59"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88056502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243814
J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver
The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.
{"title":"Isolated Preset Architecture for a 32nm SOI embedded DRAM macro","authors":"J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver","doi":"10.1109/VLSIC.2012.6243814","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243814","url":null,"abstract":"The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"21 1","pages":"110-111"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81895510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243791
Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang
Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.
{"title":"A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays","authors":"Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang","doi":"10.1109/VLSIC.2012.6243791","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243791","url":null,"abstract":"Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"71 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87699827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243859
Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester
A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.
{"title":"A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold","authors":"Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2012.6243859","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243859","url":null,"abstract":"A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"19 1","pages":"200-201"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89417548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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