Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243773
Colin Weltin-Wu, Y. Tsividis
A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.
{"title":"An event-driven, alias-free ADC with signal-dependent resolution","authors":"Colin Weltin-Wu, Y. Tsividis","doi":"10.1109/VLSIC.2012.6243773","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243773","url":null,"abstract":"A clockless 8b ADC in 130nm CMOS uses a time-varying comparison window to dynamically vary resolution, and input-dependent dynamic bias, to maintain SNDR while saving power. Alias-free operation with SNDR in the range of 47-54dB, which partly exceeds the theoretical limit of 8b conventional converters, is achieved over a 20kHz bandwidth with 3-9μW power from a 0.8V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90565847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243771
Z. Tan, Youngcheol Chae, R. Daamen, A. Humbert, Youri Ponomarev, M. Pertijs
A CMOS fully-integrated humidity sensor for a RFID sensor platform has been realized in 0.16μm CMOS technology. It consists of a top-metal finger capacitor, covered by a humidity-sensitive polyimide layer, and an energy-efficient inverter-based capacitance-to-digital converter (CDC). Measurements show that the CDC performs a 12.5-bit conversion in 0.8ms while consuming only 8.6μA from a 1.2V supply. Together with the co-integrated humidity sensor, this translates into a resolution of 0.05% RH in the range of 30% RH to 90% RH, at an energy consumption of only 8.3nJ per measurement.
{"title":"A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applications","authors":"Z. Tan, Youngcheol Chae, R. Daamen, A. Humbert, Youri Ponomarev, M. Pertijs","doi":"10.1109/VLSIC.2012.6243771","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243771","url":null,"abstract":"A CMOS fully-integrated humidity sensor for a RFID sensor platform has been realized in 0.16μm CMOS technology. It consists of a top-metal finger capacitor, covered by a humidity-sensitive polyimide layer, and an energy-efficient inverter-based capacitance-to-digital converter (CDC). Measurements show that the CDC performs a 12.5-bit conversion in 0.8ms while consuming only 8.6μA from a 1.2V supply. Together with the co-integrated humidity sensor, this translates into a resolution of 0.05% RH in the range of 30% RH to 90% RH, at an energy consumption of only 8.3nJ per measurement.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87399271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243783
Jung‐Dong Park, Shinwon Kang, S. V. Thyagarajan, E. Alon, A. Niknejad
A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.
{"title":"A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication","authors":"Jung‐Dong Park, Shinwon Kang, S. V. Thyagarajan, E. Alon, A. Niknejad","doi":"10.1109/VLSIC.2012.6243783","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243783","url":null,"abstract":"A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90047640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243833
A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De
A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).
{"title":"A fully-digital phase-locked low dropout regulator in 32nm CMOS","authors":"A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De","doi":"10.1109/VLSIC.2012.6243833","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243833","url":null,"abstract":"A fully-digital phase-locked low dropout regulator (LDO) has been designed in 32nm CMOS for fine-grained power delivery to multi-Vcc digital circuits. Measurements across a wide range of input voltages and currents exhibit that the LDO offers excellent load regulation and efficiency close to 97% of ideal efficiency at nominal load current conditions (ILOAD=3mA).","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82950439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243855
KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, Seonghwan Cho
This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.
{"title":"A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier","authors":"KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, Seonghwan Cho","doi":"10.1109/VLSIC.2012.6243855","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243855","url":null,"abstract":"This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83550258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243766
Keng-Jan Hsiao
A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from -20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.
{"title":"A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation","authors":"Keng-Jan Hsiao","doi":"10.1109/VLSIC.2012.6243766","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243766","url":null,"abstract":"A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from -20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83471735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243788
N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki
A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.
{"title":"A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS","authors":"N. Maeda, S. Komatsu, M. Morimoto, Y. Shimazaki","doi":"10.1109/VLSIC.2012.6243788","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243788","url":null,"abstract":"A high-performance and low-leakage current embedded SRAM for mobile phones is proposed. The proposed SRAM has a low-voltage resume-standby mode to reduce the standby leakage. An all digital current comparator is also proposed to choose a suitable standby mode. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 Kb SRAM achives 0.41 μA standby leakage which is half of the conventional value, with 420 ps access.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88056502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243796
D. Miyashita, K. Agawa, H. Kajihara, K. Sami, Masaomi Iwanaga, Y. Ogasawara, Tomohiko Ito, Daisuke Kurose, N. Koide, Toru Hashimoto, H. Sakurai, T. Yamaji, T. Kurihara, Kazumi Sato, I. Seto, H. Yoshida, R. Fujimoto, Y. Unekawa
TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the world's smallest module prototype using the SoC, which is suitable for small mobile devices.
{"title":"A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS","authors":"D. Miyashita, K. Agawa, H. Kajihara, K. Sami, Masaomi Iwanaga, Y. Ogasawara, Tomohiko Ito, Daisuke Kurose, N. Koide, Toru Hashimoto, H. Sakurai, T. Yamaji, T. Kurihara, Kazumi Sato, I. Seto, H. Yoshida, R. Fujimoto, Y. Unekawa","doi":"10.1109/VLSIC.2012.6243796","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243796","url":null,"abstract":"TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the world's smallest module prototype using the SoC, which is suitable for small mobile devices.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73318068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243789
S. Moriwaki, Yasuhiro Yamamoto, A. Kawasumi, Toshikazu Suzuki, S. Miyano, T. Sakurai, H. Shinohara
1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.
{"title":"A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges","authors":"S. Moriwaki, Yasuhiro Yamamoto, A. Kawasumi, Toshikazu Suzuki, S. Miyano, T. Sakurai, H. Shinohara","doi":"10.1109/VLSIC.2012.6243789","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243789","url":null,"abstract":"1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89582445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243847
M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, Soner Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, D. Friedman
A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.
{"title":"An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS","authors":"M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, Soner Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, D. Friedman","doi":"10.1109/VLSIC.2012.6243847","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243847","url":null,"abstract":"A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84918429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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