Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243843
M. Gande, N. Maghari, Taehwan Oh, U. Moon
A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.
{"title":"A 71dB dynamic range third-order ΔΣ TDC using charge-pump","authors":"M. Gande, N. Maghari, Taehwan Oh, U. Moon","doi":"10.1109/VLSIC.2012.6243843","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243843","url":null,"abstract":"A high resolution time-to-digital converter (TDC) architecture is proposed. The architecture combines the principles of noise-shaping quantization and charge-pump to build a third-order ΔΣ TDC with a dedicated feedback DAC. Fabricated in a 0.13μm CMOS process, the prototype TDC achieves better than 71dB DR and 67dB SNDR in 2.81MHz signal bandwidth (OSR=16) and consumes 2.58mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"36 1","pages":"168-169"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81259026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243834
Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori
A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.
{"title":"A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications","authors":"Hui Xu, J. Tanabe, Hiroyuki Usui, Soichiro Hosoda, T. Sano, Kazumasa Yamamoto, T. Kodaka, N. Nonogaki, Nau Ozaki, T. Miyamori","doi":"10.1109/VLSIC.2012.6243834","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243834","url":null,"abstract":"A low-power many-core SoC for multimedia applications is implemented in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications, such as the H.264 1080p 30fps decoding under 500mW and the super resolution 4K2K 15fps image processing under 800mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"35 1","pages":"150-151"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79101220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243802
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins
An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration.
{"title":"A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure","authors":"Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, U. Seng-Pan, R. Martins","doi":"10.1109/VLSIC.2012.6243802","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243802","url":null,"abstract":"An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"32 1","pages":"86-87"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82807154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243821
Che-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, C. Ho, Fu-Liang Yang, H. Tsai, H. Liao, Y. Juang, Chorng-Kuang Wang, Chih-Ting Lin, Shey-Shi Lu
Polysilicon nanowire (poly-Si NW) based biosensor is integrated with the wireless acquisition circuits in a standard CMOS SoC for the first time. To improve detection quality, a chopper DDA-based analog front-end with features of low noise, high CMRR, and rail-to-rail input range is implemented. Additional temperature sensor is also included to compensate temperature drift of the biosensor. The results indicate that the detection limit is as low as 10fM. The capability to distinguish one base-pair mismatched DNAs is also demonstrated.
{"title":"A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process","authors":"Che-Wei Huang, Yu-Jie Huang, Pei-Wen Yen, Hsiao-Ting Hsueh, Chia-Yi Lin, Min-Cheng Chen, C. Ho, Fu-Liang Yang, H. Tsai, H. Liao, Y. Juang, Chorng-Kuang Wang, Chih-Ting Lin, Shey-Shi Lu","doi":"10.1109/VLSIC.2012.6243821","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243821","url":null,"abstract":"Polysilicon nanowire (poly-Si NW) based biosensor is integrated with the wireless acquisition circuits in a standard CMOS SoC for the first time. To improve detection quality, a chopper DDA-based analog front-end with features of low noise, high CMRR, and rail-to-rail input range is implemented. Additional temperature sensor is also included to compensate temperature drift of the biosensor. The results indicate that the detection limit is as low as 10fM. The capability to distinguish one base-pair mismatched DNAs is also demonstrated.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"78 2 1","pages":"124-125"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77224441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243850
Q. Khan, A. Elshazly, Sachin Rao, Rajesh Inti, P. Hanumolu
A hysteretic buck converter employs a hybrid voltage/current mode control to regulate output voltage and switching frequency independently. Fabricated in a 130nm CMOS process, the prototype consumes only 50μA quiescent current and operates at a constant switching frequency of 1MHz over a wide range of output voltages (0.7-to-1.8V) and inductor values (1-to-5μH) with a peak efficiency of 93%. The output ripple and the settling time of the converter are less than ±2.5mV and 10μs, respectively.
{"title":"A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control","authors":"Q. Khan, A. Elshazly, Sachin Rao, Rajesh Inti, P. Hanumolu","doi":"10.1109/VLSIC.2012.6243850","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243850","url":null,"abstract":"A hysteretic buck converter employs a hybrid voltage/current mode control to regulate output voltage and switching frequency independently. Fabricated in a 130nm CMOS process, the prototype consumes only 50μA quiescent current and operates at a constant switching frequency of 1MHz over a wide range of output voltages (0.7-to-1.8V) and inductor values (1-to-5μH) with a peak efficiency of 93%. The output ripple and the settling time of the converter are less than ±2.5mV and 10μs, respectively.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"12 1","pages":"182-183"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88260077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243795
D. Yeager, W. Biederman, Nathan Narevsky, E. Alon, J. Rabaey
A wirelessly powered 0.125mm2 65nm CMOS IC for BMI applications integrates four 1.5μW amplifiers (6.5μVrms input-referred noise for a 10kHz bandwidth) with power conditioning and communication circuitry. The multi-node backscatter FDMA communication scheme frequency locks to a wireless interrogator. The full system, verified wirelessly with MATLAB generated neural data, consumes 10.5μW, and operates at 1mm range in air with 50mW transmit power.
{"title":"A fully-integrated 10.5µW miniaturized (0.125mm2) wireless neural sensor","authors":"D. Yeager, W. Biederman, Nathan Narevsky, E. Alon, J. Rabaey","doi":"10.1109/VLSIC.2012.6243795","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243795","url":null,"abstract":"A wirelessly powered 0.125mm2 65nm CMOS IC for BMI applications integrates four 1.5μW amplifiers (6.5μVrms input-referred noise for a 10kHz bandwidth) with power conditioning and communication circuitry. The multi-node backscatter FDMA communication scheme frequency locks to a wireless interrogator. The full system, verified wirelessly with MATLAB generated neural data, consumes 10.5μW, and operates at 1mm range in air with 50mW transmit power.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"59 1","pages":"72-73"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85021950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243837
S. Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, C. Su, Chen-Yi Lee
A multi-functional cardiac signal processor (CSP) with integrated sensor interfaces is designed for mobile healthcare applications, especially for heart activity diagnosis in different phases. Applying dedicated processing engines, the CSP extracts critical cardiac signal features based on compressed data with 90% storage reduction, while keeping the data network secure. Implemented in 90nm CMOS, the CSP consumes 22.6μW to 46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality.
{"title":"A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications","authors":"S. Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, C. Su, Chen-Yi Lee","doi":"10.1109/VLSIC.2012.6243837","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243837","url":null,"abstract":"A multi-functional cardiac signal processor (CSP) with integrated sensor interfaces is designed for mobile healthcare applications, especially for heart activity diagnosis in different phases. Applying dedicated processing engines, the CSP extracts critical cardiac signal features based on compressed data with 90% storage reduction, while keeping the data network secure. Implemented in 90nm CMOS, the CSP consumes 22.6μW to 46.5μW at 0.5/1.0V in different configurations. Besides, the 10.2μW biopotential and 11.4μW capacitive sensor interfaces further enhance the system functionality.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"26 1","pages":"156-157"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73502106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243824
Seung-hwan Song, K. Chun, C. Kim
A logic-compatible embedded flash memory that uses no special devices other than standard core and IO transistors is demonstrated in a low-power standard logic process having a 5nm tunnel oxide. An overstress-free high voltage switch expands the cell VTH window by >;170% while a 5T embedded flash memory cell with a selective row refresh scheme is employed for improved endurance.
{"title":"A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme","authors":"Seung-hwan Song, K. Chun, C. Kim","doi":"10.1109/VLSIC.2012.6243824","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243824","url":null,"abstract":"A logic-compatible embedded flash memory that uses no special devices other than standard core and IO transistors is demonstrated in a low-power standard logic process having a 5nm tunnel oxide. An overstress-free high voltage switch expands the cell VTH window by >;170% while a 5T embedded flash memory cell with a selective row refresh scheme is employed for improved endurance.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"16 1","pages":"130-131"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73903762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243823
A. Peizerat, J. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian
A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.
{"title":"An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversion","authors":"A. Peizerat, J. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian","doi":"10.1109/VLSIC.2012.6243823","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243823","url":null,"abstract":"A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"128-129"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82052926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243767
T. Tokairin, K. Nose, K. Takeda, K. Noguchi, T. Maeda, Kazuyoshi Kawai, M. Mizuno
A sub-μW, 1-cycle start-up CMOS relaxation oscillator has been developed with a feedforward period control scheme and a digitally-controlled boost charging technique. The oscillator is implemented in 90nm CMOS and we sucessfuly have demonstrated 100kHz clock generation with ±1%-accuracy and an extremely low power consumption of 280nW.
{"title":"A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme","authors":"T. Tokairin, K. Nose, K. Takeda, K. Noguchi, T. Maeda, Kazuyoshi Kawai, M. Mizuno","doi":"10.1109/VLSIC.2012.6243767","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243767","url":null,"abstract":"A sub-μW, 1-cycle start-up CMOS relaxation oscillator has been developed with a feedforward period control scheme and a digitally-controlled boost charging technique. The oscillator is implemented in 90nm CMOS and we sucessfuly have demonstrated 100kHz clock generation with ±1%-accuracy and an extremely low power consumption of 280nW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"510 1","pages":"16-17"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85628414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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