Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243798
Kohei Onizuka, S. Saigusa, S. Otaka
A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.
{"title":"A +30.5 dBm CMOS Doherty power amplifier with reliability enhancement technique","authors":"Kohei Onizuka, S. Saigusa, S. Otaka","doi":"10.1109/VLSIC.2012.6243798","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243798","url":null,"abstract":"A watt-level, fully integrated 1:1 Doherty power amplifier for 2.4 GHz band is demonstrated in 65 nm CMOS. Both high peak output power of +30.5 dBm and high PAE of 23% at 6 dB power back-off are achieved by the proposed compact output network. A newly introduced reliability enhancement technique for sub-PA prolongs time to failure by up to 75% as well. The PA satisfies IEEE 802.11b and 11g spectrum masks at output power levels of 25.5 and 21.5 dBm respectively, from supply voltage of 3.3 V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80423768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243810
T. Toifl, M. Ruegg, Rajesh Inti, C. Menolfi, M. Braendli, M. Kossel, P. Buchmann, P. Francese, T. Morf
This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.
{"title":"A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS","authors":"T. Toifl, M. Ruegg, Rajesh Inti, C. Menolfi, M. Braendli, M. Kossel, P. Buchmann, P. Francese, T. Morf","doi":"10.1109/VLSIC.2012.6243810","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243810","url":null,"abstract":"This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79720404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243762
Nick Ilyadis
With the emergence of cloud computing, new data center architectures are being created to address the challenges of the new computing models. The scale of these next-generation data center networks drives the demand for high-density, low-latency and low-power networking solutions. These networks are being deployed with flat topologies, virtualization and low latency. The silicon solutions that are being developed to address these new networks are redefining the data center landscape. This paper and the presentation describe the cloud data model and the evolution of the data center, and then consider the technologies that are being developed to address the new paradigms. This paper also describes the silicon solutions (the underlying engines) and the challenges they must overcome to meet these requirements.
{"title":"The evolution of next-generation data center networks for high capacity computing","authors":"Nick Ilyadis","doi":"10.1109/VLSIC.2012.6243762","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243762","url":null,"abstract":"With the emergence of cloud computing, new data center architectures are being created to address the challenges of the new computing models. The scale of these next-generation data center networks drives the demand for high-density, low-latency and low-power networking solutions. These networks are being deployed with flat topologies, virtualization and low latency. The silicon solutions that are being developed to address these new networks are redefining the data center landscape. This paper and the presentation describe the cloud data model and the evolution of the data center, and then consider the technologies that are being developed to address the new paradigms. This paper also describes the silicon solutions (the underlying engines) and the challenges they must overcome to meet these requirements.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80217806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243797
Yulin Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, Chun C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, Hyung Seok Kim, B. Carlton, Satoshi Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala
A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.
{"title":"A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS","authors":"Yulin Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, Chun C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, Hyung Seok Kim, B. Carlton, Satoshi Suzuki, M. Shafi, Y. Palaskas, H. Lakdawala","doi":"10.1109/VLSIC.2012.6243797","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243797","url":null,"abstract":"A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization the TX delivers 19.8dBm at 12.5% efficiency (PA 21.6dBm/19.7% PAE) for -25dB EVM and mask-compliant 22.8dBm/18.5%, while the RX achieves 4.8dB NF, -69dBm sensitivity, and -8dBm IIP3.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81169130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243786
C. Lai, K. Tan, L. Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu
A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC). The proposed architecture has range and azimuth resolution of 0.75 cm and 3 degree respectively. This prototype is implemented in a 0.18μm CMOS technology.
{"title":"A UWB IR timed-array radar using time-shifted direct-sampling architecture","authors":"C. Lai, K. Tan, L. Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu","doi":"10.1109/VLSIC.2012.6243786","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243786","url":null,"abstract":"A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC). The proposed architecture has range and azimuth resolution of 0.75 cm and 3 degree respectively. This prototype is implemented in a 0.18μm CMOS technology.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82634219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243774
Bibhudatta Sahoo, Behzad Razavi
A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step.
{"title":"A 10-bit 1-GHz 33-mW CMOS ADC","authors":"Bibhudatta Sahoo, Behzad Razavi","doi":"10.1109/VLSIC.2012.6243774","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243774","url":null,"abstract":"A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76164304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243841
Seung-Chul Lee, Brian Elies, Y. Chiu
A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a -1dBFS (1.1Vpp) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies 0.28mm2 in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.
{"title":"An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration","authors":"Seung-Chul Lee, Brian Elies, Y. Chiu","doi":"10.1109/VLSIC.2012.6243841","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243841","url":null,"abstract":"A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is accomplished by correlating various moments of the ADC output with a one-bit pseudorandom noise (PN). The prototype ADC employing 29dB gain amplifiers measures 85dB SFDR and 67dB SNDR for a -1dBFS (1.1Vpp) 5MHz sinusoidal input at 240MS/s. The core ADC consumes 37mW from a 1.25V supply and occupies 0.28mm2 in a 65nm CMOS low-leakage digital process, in which the transistor threshold voltages are around 0.5V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79655523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243803
Yuanching Lien
A 8-b 2-b/step asynchronous subranged SAR ADC is presented. It incorporates subranging technique to obtain fast reference settling for MSB conversion. The capacitive interpolation reduces number of NMOS switches and lowers matching requirement of a resistive DAC. The proposed timing scheme avoids the need of specific duty cycle of external clock for defining sampling period in a conventional asynchronous SAR ADC. Operating at 750 MS/s, this ADC consumes 4.5 mW from 1-V supply, achieves ENOB of 7.2 and FOM of 41 fJ/conversion-step. It is fabricated in 28-nm CMOS technology and occupies an active area of 0.004 mm2.
{"title":"A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology","authors":"Yuanching Lien","doi":"10.1109/VLSIC.2012.6243803","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243803","url":null,"abstract":"A 8-b 2-b/step asynchronous subranged SAR ADC is presented. It incorporates subranging technique to obtain fast reference settling for MSB conversion. The capacitive interpolation reduces number of NMOS switches and lowers matching requirement of a resistive DAC. The proposed timing scheme avoids the need of specific duty cycle of external clock for defining sampling period in a conventional asynchronous SAR ADC. Operating at 750 MS/s, this ADC consumes 4.5 mW from 1-V supply, achieves ENOB of 7.2 and FOM of 41 fJ/conversion-step. It is fabricated in 28-nm CMOS technology and occupies an active area of 0.004 mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75519804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243826
Hiroki Fujii, K. Miyaji, K. Johguchi, K. Higuchi, Chao Sun, K. Takeuchi
A 3D through-silicon-via (TSV) -integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drives' (SSDs') architecture is proposed for PC, server and smart phone applications. NAND-like interface (I/F) and sector-access overwrite policy are proposed for the ReRAM. Furthermore, intelligent data management algorithms are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. Both ReRAM write and read latency should be less than 3μs to obtain these improvements. The required endurance for ReRAM is 105. 3D TSV interconnects reduce the energy consumption by 68%.
{"title":"x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression","authors":"Hiroki Fujii, K. Miyaji, K. Johguchi, K. Higuchi, Chao Sun, K. Takeuchi","doi":"10.1109/VLSIC.2012.6243826","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243826","url":null,"abstract":"A 3D through-silicon-via (TSV) -integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drives' (SSDs') architecture is proposed for PC, server and smart phone applications. NAND-like interface (I/F) and sector-access overwrite policy are proposed for the ReRAM. Furthermore, intelligent data management algorithms are proposed. The proposed algorithms suppress data fragmentation and excess usage of the MLC NAND by storing hot data in the ReRAM. As a result, 11 times performance increase, 6.9 times endurance enhancement and 93% write energy reduction are achieved compared with the conventional MLC NAND SSD. Both ReRAM write and read latency should be less than 3μs to obtain these improvements. The required endurance for ReRAM is 105. 3D TSV interconnects reduce the energy consumption by 68%.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75064049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243852
Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, J. Sheu
This paper describes the design of a multi-GHz ADDLL. HDSC-based coarse-fine architecture is adopted to achieve low power and to avoid harmonic locking at large operating frequency ranges. A new resettable coarse delay line and an asynchronous binary-search design are proposed to achieve fast coarse locking and fine locking, respectively. A novel maintenance operation is also proposed to allow phase adjustments to be performed during each cycle to effectively suppress the jitter. The measurement results show that the designed 1.0-V, 55-nm ADDLL has a peak-to-peak jitter of 3 ps and a locking time of 8 cycles when operated at 2.5 GHz with a power dissipation of only 1.96 mW.
{"title":"Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment","authors":"Chun-Yuan Cheng, Jinn-Shyan Wang, Cheng-Tai Yeh, J. Sheu","doi":"10.1109/VLSIC.2012.6243852","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243852","url":null,"abstract":"This paper describes the design of a multi-GHz ADDLL. HDSC-based coarse-fine architecture is adopted to achieve low power and to avoid harmonic locking at large operating frequency ranges. A new resettable coarse delay line and an asynchronous binary-search design are proposed to achieve fast coarse locking and fine locking, respectively. A novel maintenance operation is also proposed to allow phase adjustments to be performed during each cycle to effectively suppress the jitter. The measurement results show that the designed 1.0-V, 55-nm ADDLL has a peak-to-peak jitter of 3 ps and a locking time of 8 cycles when operated at 2.5 GHz with a power dissipation of only 1.96 mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73453337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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