Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243791
Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang
Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.
{"title":"A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays","authors":"Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang","doi":"10.1109/VLSIC.2012.6243791","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243791","url":null,"abstract":"Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"71 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87699827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243781
S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu
A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.
{"title":"A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture","authors":"S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu","doi":"10.1109/VLSIC.2012.6243781","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243781","url":null,"abstract":"A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"60 1","pages":"44-45"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91346126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243814
J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver
The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.
{"title":"Isolated Preset Architecture for a 32nm SOI embedded DRAM macro","authors":"J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver","doi":"10.1109/VLSIC.2012.6243814","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243814","url":null,"abstract":"The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"21 1","pages":"110-111"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81895510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243859
Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester
A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.
{"title":"A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold","authors":"Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2012.6243859","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243859","url":null,"abstract":"A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"19 1","pages":"200-201"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89417548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243829
Taehyoun Oh, R. Harjani
A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.
{"title":"4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS","authors":"Taehyoun Oh, R. Harjani","doi":"10.1109/VLSIC.2012.6243829","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243829","url":null,"abstract":"A crosstalk cancellation and signal reutilization (XTCR) algorithm implemented with analog-IIR networks dramatically improves signal integrity across 4 closely-spaced single-ended PCB traces. The prototype XTCR design implemented in 65 nm CMOS improves the measured average horizontal and vertical-eye openings of the 4 channels by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"140-141"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81754866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243818
S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar
A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.
{"title":"A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS","authors":"S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2012.6243818","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243818","url":null,"abstract":"A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"278 1","pages":"118-119"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83428208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243778
Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya
An all 0.5V, 1Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit career-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 52-pJ/bit class-F transmitter with -21dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.
{"title":"An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS","authors":"Akira Saito, Kentaro Honda, Y. Zheng, S. Iguchi, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243778","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243778","url":null,"abstract":"An all 0.5V, 1Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit career-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 52-pJ/bit class-F transmitter with -21dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"37 1","pages":"38-39"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85807429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243857
Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu
A fully electrical startup boost converter is presented in this paper. With a three-stage stepping-up architecture, the proposed circuit is capable of performing thermoelectric energy harvesting at an input voltage as low as 50 mV. Due to the zero-current-switching (ZCS) operation of the boost converter and automatic shutdown of the low-voltage starter and the auxiliary converter, conversion efficiency up to 73% is demonstrated. The boost converter does not require bulky transformers or mechanical switches for kick-start, making it very attractive for body area sensor network applications.
{"title":"A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting","authors":"Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu","doi":"10.1109/VLSIC.2012.6243857","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243857","url":null,"abstract":"A fully electrical startup boost converter is presented in this paper. With a three-stage stepping-up architecture, the proposed circuit is capable of performing thermoelectric energy harvesting at an input voltage as low as 50 mV. Due to the zero-current-switching (ZCS) operation of the boost converter and automatic shutdown of the low-voltage starter and the auxiliary converter, conversion efficiency up to 73% is demonstrated. The boost converter does not require bulky transformers or mechanical switches for kick-start, making it very attractive for body area sensor network applications.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"18 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87173553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243768
Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks
Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.
{"title":"Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices","authors":"Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks","doi":"10.1109/VLSIC.2012.6243768","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243768","url":null,"abstract":"Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"34 1","pages":"18-19"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79075095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243763
Akira Maeda
New technologies are required in smart city applications, such as sensing, highly parallel processing, and mobile broadband communication. In this paper, it is pointed out that integration of information and control system technologies will be a key driver for smart cities, because these systems with quite different system characteristics should be integrated to realize sophisticated social infrastructure systems. Our approach will be explained with several project examples to describe the challenges and future trend of technology development.
{"title":"Technology innovations for smart cities","authors":"Akira Maeda","doi":"10.1109/VLSIC.2012.6243763","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243763","url":null,"abstract":"New technologies are required in smart city applications, such as sensing, highly parallel processing, and mobile broadband communication. In this paper, it is pointed out that integration of information and control system technologies will be a key driver for smart cities, because these systems with quite different system characteristics should be integrated to realize sophisticated social infrastructure systems. Our approach will be explained with several project examples to describe the challenges and future trend of technology development.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"40 1","pages":"6-9"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79168019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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