Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382263
E.P.Y. Chou, Yung‐Yun Wang, C. Wan
Palladium nanoparticles were synthesized simply by reducing Pd ions which were attracted to electron nitrogen atom in poly(N-vinyl-2-pyrrolidone) (PVP). This Pd/PVP aqueous system was developed as the activator for electroless copper deposition. Compared with commercial Pd/Sn colloid that was easily oxidized by dissolved oxygen and agglomerated in the solution, Pd/PVP activator was stable without any Pd aggregation for a long time. Pd/PVP activator showed high catalytic activity as Pd/Sn colloid on flat FR-4 substrate (glass fiber reinforced epoxy). From back-light test for printed-through-hole (PTH) process, we found that micro-etching process would reduce catalytic activity of Pd/PVP activator and voids in PTH occurred especially on glass fiber. Adding phosphoric acid to Pd/PVP activator could improve back-light performance, but Pd nanoparticles precipitated in a few days. In this study, we found that H3PO4 molecule was the cause of Pd agglomeration by forming hydrogen bond with PVP. Pd nanoparticles would precipitate if the concentration of H3PO4 were high in the solution. IR spectra and UV-vis spectra proved that Pd/PVP activator would react with H3PO4 molecules to form a complex by hydrogen bond, and DLS analysis also showed that Pd/PVP/H3PO4 nanoparticles formed a larger hydrolysis cluster than Pd/PVP nanoparticles. TEM images gave the information about particle size and shape of Pd nanoparticles, and more information about dispersion and distance of Pd nanoparticles and Pd clusters could be obtained by the model fitting of SAXS data. The results showed that Pd/PVP/H3PO4 nanoparticles formed a looser structure than Pd/PVP nanoparticles. Since there is higher Cu deposition on epoxy when we use Pd/PVP/H3PO4 nanoparticles as activator, in PTH process, Cu deposition on glass fiber is improved by Cu deposition on epoxy nearby. So back-light performance become acceptable for PCBs industry.
{"title":"The study of the stability of Pd/PVP nanoparticles added with phosphoric acid and the activity to electroless Cu deposition","authors":"E.P.Y. Chou, Yung‐Yun Wang, C. Wan","doi":"10.1109/IMPACT.2009.5382263","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382263","url":null,"abstract":"Palladium nanoparticles were synthesized simply by reducing Pd ions which were attracted to electron nitrogen atom in poly(N-vinyl-2-pyrrolidone) (PVP). This Pd/PVP aqueous system was developed as the activator for electroless copper deposition. Compared with commercial Pd/Sn colloid that was easily oxidized by dissolved oxygen and agglomerated in the solution, Pd/PVP activator was stable without any Pd aggregation for a long time. Pd/PVP activator showed high catalytic activity as Pd/Sn colloid on flat FR-4 substrate (glass fiber reinforced epoxy). From back-light test for printed-through-hole (PTH) process, we found that micro-etching process would reduce catalytic activity of Pd/PVP activator and voids in PTH occurred especially on glass fiber. Adding phosphoric acid to Pd/PVP activator could improve back-light performance, but Pd nanoparticles precipitated in a few days. In this study, we found that H3PO4 molecule was the cause of Pd agglomeration by forming hydrogen bond with PVP. Pd nanoparticles would precipitate if the concentration of H3PO4 were high in the solution. IR spectra and UV-vis spectra proved that Pd/PVP activator would react with H3PO4 molecules to form a complex by hydrogen bond, and DLS analysis also showed that Pd/PVP/H3PO4 nanoparticles formed a larger hydrolysis cluster than Pd/PVP nanoparticles. TEM images gave the information about particle size and shape of Pd nanoparticles, and more information about dispersion and distance of Pd nanoparticles and Pd clusters could be obtained by the model fitting of SAXS data. The results showed that Pd/PVP/H3PO4 nanoparticles formed a looser structure than Pd/PVP nanoparticles. Since there is higher Cu deposition on epoxy when we use Pd/PVP/H3PO4 nanoparticles as activator, in PTH process, Cu deposition on glass fiber is improved by Cu deposition on epoxy nearby. So back-light performance become acceptable for PCBs industry.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"625-628"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90794955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382117
R. Ahmad, O. Sidek, S. Mohd
CRC (Cyclic Redundanncy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. The Verilog code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.
为了满足Zigbee等简单、低功耗、低成本的无线通信需求，在FPGA(现场可编程门阵列)上开发了CRC(循环冗余校验)块。Zigbee主要在2.4 GHz频段运行，这使得该技术易于应用并在全球范围内可用。本文简要介绍了基于Zigbee标准的数字发射机中的CRC分组。CRC是最受欢迎的编码方法，因为它对常见的突发错误提供了非常有效的保护，并且易于实现。该研究的目的是通过Xilinx ISE 8.2i使用Verilog代码条目来使设计方法多样化。Verilog代码用于描述CRC块行为，然后在Spartan3E XC3S500E FPGA上进行模拟，合成并成功实现。本文还给出了仿真和测量结果来验证CRC块的功能。CRC块的数据速率为250kbps。
{"title":"Development of CRC block onn FPGA for Zigbee standard","authors":"R. Ahmad, O. Sidek, S. Mohd","doi":"10.1109/IMPACT.2009.5382117","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382117","url":null,"abstract":"CRC (Cyclic Redundanncy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. The Verilog code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"282-285"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88277639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382253
S. Lin, R. Huang, C. Chiu
In this paper, the thermal analysis is carried out by the combination of actual thermal measurement and numerical finite element simulation to investigate insightfully the thermal characteristics of each element in the whole assembly of the LED lighting system (LLS). Based on the thermo/fluid coupled field numerical simulation, the ANSYS¿,s finite elements are used to model the detailed assembly parts in the high-power LLS. The highpower LLS samples were assembled by soldering the LED-Ceramic package on a copper sheet, which was then attached to an aluminum alloy heat sink using thermally conductive adhesive. Four different ceramic materials: AlN, SiC, LTCC with Ag thermal via and Al2O3, were studied as ceramic thermally conductive substrates (CTCS) for the high power LED dies' packaging. The ceramic sub-mounts were produced by packing multiple LED chips with silicone resin containing phosphors coated on a CTCS. The thermal resistances of ceramic sub-mounts with the same configuration were determined to be 0.1411°C/W for AlN, 0.1778°C/W for SiC, 1.9732°C/W for LTCC with 30 volume% of silver thermal vias, and 2.0262°C/W for Al2O3. Results indicate that ceramic materials are very suitable for reducing the thermal management issues for high-power LED lighting applications.
{"title":"Investigation of thermally conductive ceramic substrates for high-power LED application","authors":"S. Lin, R. Huang, C. Chiu","doi":"10.1109/IMPACT.2009.5382253","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382253","url":null,"abstract":"In this paper, the thermal analysis is carried out by the combination of actual thermal measurement and numerical finite element simulation to investigate insightfully the thermal characteristics of each element in the whole assembly of the LED lighting system (LLS). Based on the thermo/fluid coupled field numerical simulation, the ANSYS¿,s finite elements are used to model the detailed assembly parts in the high-power LLS. The highpower LLS samples were assembled by soldering the LED-Ceramic package on a copper sheet, which was then attached to an aluminum alloy heat sink using thermally conductive adhesive. Four different ceramic materials: AlN, SiC, LTCC with Ag thermal via and Al2O3, were studied as ceramic thermally conductive substrates (CTCS) for the high power LED dies' packaging. The ceramic sub-mounts were produced by packing multiple LED chips with silicone resin containing phosphors coated on a CTCS. The thermal resistances of ceramic sub-mounts with the same configuration were determined to be 0.1411°C/W for AlN, 0.1778°C/W for SiC, 1.9732°C/W for LTCC with 30 volume% of silver thermal vias, and 2.0262°C/W for Al2O3. Results indicate that ceramic materials are very suitable for reducing the thermal management issues for high-power LED lighting applications.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"15 1","pages":"589-592"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87207944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382116
H. Kishi, T. Sasaki, N. Ueta, Ken Suzuki, H. Miura
Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced stress and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
{"title":"Multi-scale measurement of the change of the residual stress in a silicon chip during manufacturing from thin-film processing to packaging","authors":"H. Kishi, T. Sasaki, N. Ueta, Ken Suzuki, H. Miura","doi":"10.1109/IMPACT.2009.5382116","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382116","url":null,"abstract":"Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced stress and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"12 3 1","pages":"293-296"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82391378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382134
Mu-Chun Wang, Z. Hsieh, Kuo-Shu Huang, C. Tu, Shuang-Yuan Chen, Heng-Sheng Huang
In general, the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging) is able to be integrated by 7-step processes, including two masks and one set of stencil plate. After the formation of solder ball, the specified professional probe card is needed to verify whether the electric functions of this packaged IC are good. After this step, the wafer grinding, the wafer cutting, the chip choice and the final test (F/T) are gradually adopted to proceed. Finally, due to the customer's need, the shipping package type to customers is, generally, tray or tape and reel. Although the stencil printing technology can provide the mass-production capability, the mainly existing problems of this technology are the quality of manufacturing steel plate, the coating operation for solder paste, and the flatness of wafer surface. These issues usually constrain the minimization of the size of the solder ball and the pitch. Thinking to solve these issues, this package technology is still feasible in assembly competition.
{"title":"A study to stencil printing technology for solder bump assembly","authors":"Mu-Chun Wang, Z. Hsieh, Kuo-Shu Huang, C. Tu, Shuang-Yuan Chen, Heng-Sheng Huang","doi":"10.1109/IMPACT.2009.5382134","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382134","url":null,"abstract":"In general, the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging) is able to be integrated by 7-step processes, including two masks and one set of stencil plate. After the formation of solder ball, the specified professional probe card is needed to verify whether the electric functions of this packaged IC are good. After this step, the wafer grinding, the wafer cutting, the chip choice and the final test (F/T) are gradually adopted to proceed. Finally, due to the customer's need, the shipping package type to customers is, generally, tray or tape and reel. Although the stencil printing technology can provide the mass-production capability, the mainly existing problems of this technology are the quality of manufacturing steel plate, the coating operation for solder paste, and the flatness of wafer surface. These issues usually constrain the minimization of the size of the solder ball and the pitch. Thinking to solve these issues, this package technology is still feasible in assembly competition.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"54 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80351122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382237
Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee, Jenn-Ming Song, Yao-Ren Liu, M. Tsai
A strain-controllable dynamic bending method on WLCSP has been proposed in this paper. In order to identify the principle factor among the effects of stiffness attributed by different board level structures, the 0.4mm pitch WLCSP packages with Sn-4.0Ag-0.5Cu solder ball are used. This combination of WLCSP is considered to have the high stiffness in the structure. It is also shown that there are interactions between the SAC405 solder balls, the Al/Ni/Cu pad plating, the reflow profile and the flux chemistry. The experimental result shows that at the same strain rate range (∼106 µɛ/s), the fracture position occurrence happens in internal die at 11,000µɛ. This data indicates that the brittle fracture position transfers from general IMC layer to higher brittle layer in the component. The variation of the strain energy of materials and the stress concentration position which changes in different package sizes are speculated to be the cause of the fracture position transfer. Therefore, in our research; we will investigate the relationship between the IMC layer and microstructure of under bump metallization (UBM). The influence of different package dimensions will be discussed in this study, too.
{"title":"Failure mode evolution of WLCSP on board by dynamic bend method","authors":"Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee, Jenn-Ming Song, Yao-Ren Liu, M. Tsai","doi":"10.1109/IMPACT.2009.5382237","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382237","url":null,"abstract":"A strain-controllable dynamic bending method on WLCSP has been proposed in this paper. In order to identify the principle factor among the effects of stiffness attributed by different board level structures, the 0.4mm pitch WLCSP packages with Sn-4.0Ag-0.5Cu solder ball are used. This combination of WLCSP is considered to have the high stiffness in the structure. It is also shown that there are interactions between the SAC405 solder balls, the Al/Ni/Cu pad plating, the reflow profile and the flux chemistry. The experimental result shows that at the same strain rate range (∼106 µɛ/s), the fracture position occurrence happens in internal die at 11,000µɛ. This data indicates that the brittle fracture position transfers from general IMC layer to higher brittle layer in the component. The variation of the strain energy of materials and the stress concentration position which changes in different package sizes are speculated to be the cause of the fracture position transfer. Therefore, in our research; we will investigate the relationship between the IMC layer and microstructure of under bump metallization (UBM). The influence of different package dimensions will be discussed in this study, too.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"136 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86625659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382238
M. Sano, C. Chou, T. Hung, Shin-Yueh Yang, Chao-Jen Huang, K. Chiang
The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.
{"title":"Reliability and parametric study on chip scale package under board-level drop test","authors":"M. Sano, C. Chou, T. Hung, Shin-Yueh Yang, Chao-Jen Huang, K. Chiang","doi":"10.1109/IMPACT.2009.5382238","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382238","url":null,"abstract":"The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"537-540"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81366372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382132
P. Liang
In the past, high-frequency communication applications put emphasis on low loss while high speed signal transmission is required to achieve the integrity of the signal. In order to ensure the target of low loss on the CCL materials, mmost studies focus on how to reduce the polarity for resin system to achieve low Dk and low tan δ to improve the signal characteristics of high-spped transmission. The recent rapid development of IT industry demand for high-frequency communications, coupled with many researches show the composition of the CCL material, such as copper foil, glass fiber yarn and resin modification. This study intends to analyze the roughness of copper foil matte side, glass type and spreading uniformity to realize the impact on high frequency signals. Finally, we hope we can find a low cost solution for high frequency communications applications.
{"title":"The effects of CCL composition on signal loss for high frequency application","authors":"P. Liang","doi":"10.1109/IMPACT.2009.5382132","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382132","url":null,"abstract":"In the past, high-frequency communication applications put emphasis on low loss while high speed signal transmission is required to achieve the integrity of the signal. In order to ensure the target of low loss on the CCL materials, mmost studies focus on how to reduce the polarity for resin system to achieve low Dk and low tan δ to improve the signal characteristics of high-spped transmission. The recent rapid development of IT industry demand for high-frequency communications, coupled with many researches show the composition of the CCL material, such as copper foil, glass fiber yarn and resin modification. This study intends to analyze the roughness of copper foil matte side, glass type and spreading uniformity to realize the impact on high frequency signals. Finally, we hope we can find a low cost solution for high frequency communications applications.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"15 1","pages":"236-239"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82468713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382301
W. Jong, S. Peng
Due to the environmental protection issues and regulations, a lot of electronic material suppliers try to search for the replacement materials which include the lead-free solder joints and the anisotropic conductive films (ACFs). ACF is widely used in high quality, excellent signal interconnection and fine pitch products. Nevertheless, during the fast flow and curing process of the electronic material, the risk of voiding may be increased. This study focuses on the characteristics and phenomena of a new-type ACF on the outer lead bonding (OLB) for flip chip on flex substrate (FCOF) assembly. Firstly, the thermal response and curing capability of the new-type ACF is investigated by the experiment. And the numerical simulation is used by computer aided engineering (CAE) that shows the heating effect of components on the bonding process. Both the simulated and experimental results can obtain the similar thermal behaviors. For the reliability assessment of the new-type ACF, the experiment procedures are adjusted three parameters of temperature, pressure and time under the bonding process. It can be easily discovered that the delaminations or cracks is caused by a lower compliance behavior of the interfaces between bumps on the polyimide (PI) substrate and indium tin oxides (ITOs) on the glass substrate. In order to evaluate the adhesive strength of ACF through the thermal loading, the strength of FCOF assembly is measured by a 90-degree peel test and is verified by the CAE simulation. In this study, the minimum peel strength of the new-type ACF has to be greater than 400 g/cm in order to satisfy the specification. Then, a stripped meshed model is simulated to understand the fracture growth between each interface under a constant speed of 8mm/sec. It can be found that the initial creak starts from the ACF-glass substrate interface and then propagates to the ITO. Finally, the swelling phenomenon of the new-type ACF is investigated. It shows that the swelling will not affect the structure of components and the reliability assessment is good.
{"title":"A study for the new-type ACF applications of FCOF assembly","authors":"W. Jong, S. Peng","doi":"10.1109/IMPACT.2009.5382301","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382301","url":null,"abstract":"Due to the environmental protection issues and regulations, a lot of electronic material suppliers try to search for the replacement materials which include the lead-free solder joints and the anisotropic conductive films (ACFs). ACF is widely used in high quality, excellent signal interconnection and fine pitch products. Nevertheless, during the fast flow and curing process of the electronic material, the risk of voiding may be increased. This study focuses on the characteristics and phenomena of a new-type ACF on the outer lead bonding (OLB) for flip chip on flex substrate (FCOF) assembly. Firstly, the thermal response and curing capability of the new-type ACF is investigated by the experiment. And the numerical simulation is used by computer aided engineering (CAE) that shows the heating effect of components on the bonding process. Both the simulated and experimental results can obtain the similar thermal behaviors. For the reliability assessment of the new-type ACF, the experiment procedures are adjusted three parameters of temperature, pressure and time under the bonding process. It can be easily discovered that the delaminations or cracks is caused by a lower compliance behavior of the interfaces between bumps on the polyimide (PI) substrate and indium tin oxides (ITOs) on the glass substrate. In order to evaluate the adhesive strength of ACF through the thermal loading, the strength of FCOF assembly is measured by a 90-degree peel test and is verified by the CAE simulation. In this study, the minimum peel strength of the new-type ACF has to be greater than 400 g/cm in order to satisfy the specification. Then, a stripped meshed model is simulated to understand the fracture growth between each interface under a constant speed of 8mm/sec. It can be found that the initial creak starts from the ACF-glass substrate interface and then propagates to the ITO. Finally, the swelling phenomenon of the new-type ACF is investigated. It shows that the swelling will not affect the structure of components and the reliability assessment is good.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":" 23","pages":"31-34"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91413918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382122
Wei-Kai Liou, Y. Yen, Chien-Chung Jao
This study investigates aging effects on interfacial reactions between Sn-9wt%Zn-x wt% (SZ-xCu) alloys and Au substrate. The Au3Zn7/AuZn2/AuZn and Au3Zn7/AuZn phases respectively formed in the SZ/Au and SZ-1Cu/Au couples aged at 160°C for 24 hours. Only the AuSn phase was found at the SZ-4 Cu/Au interface. Extending the aging time to 800 hours, Sn became a dominant diffusion element. Binary Au-Sn phases and the metastable Au-Zn-Sn ternary phase, Au33–36 Zn35–36Sn29–31, was formed at the interface. The aging effect causing the changes of dominant diffusion element and concentration of Zn, Cu in the solder is the main reasons to change the sequence of the IMC formation in the SZ-xCu/Au systems.
{"title":"Aging effects on interfacial reactions between Cu addition into the Sn-9Zn lead-free solder and Au substrate","authors":"Wei-Kai Liou, Y. Yen, Chien-Chung Jao","doi":"10.1109/IMPACT.2009.5382122","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382122","url":null,"abstract":"This study investigates aging effects on interfacial reactions between Sn-9wt%Zn-x wt% (SZ-xCu) alloys and Au substrate. The Au<inf>3</inf>Zn<inf>7</inf>/AuZn<inf>2</inf>/AuZn and Au<inf>3</inf>Zn<inf>7</inf>/AuZn phases respectively formed in the SZ/Au and SZ-1Cu/Au couples aged at 160°C for 24 hours. Only the AuSn phase was found at the SZ-4 Cu/Au interface. Extending the aging time to 800 hours, Sn became a dominant diffusion element. Binary Au-Sn phases and the metastable Au-Zn-Sn ternary phase, Au<inf>33–36</inf> Zn<inf>35–36</inf>Sn<inf>29–31</inf>, was formed at the interface. The aging effect causing the changes of dominant diffusion element and concentration of Zn, Cu in the solder is the main reasons to change the sequence of the IMC formation in the SZ-xCu/Au systems.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"224 1","pages":"271-273"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73200893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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