Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382279
Chien-Cheng Wei, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru
Direct plated copper (DPC) metallized substrate is introduced, characterized, and demonstrated in this paper. The proposed DPC metallized substrate has the main advantages of high-frequency characteristics and excellent thermal management, due to the use of ceramic substrate and metallized copper conductor. Besides, the DPC process also provides high circuit density, fine pitch, and low cost potential compared to other technologies, like direct bonded copper (DBC), Low-Temperature Cofired Ceramics (LTCC), and High-Temperature Cofired Ceramics (HTCC) processes. Therefore, to characterize the electrical properties of DPC substrate for high-frequency applications, a simple extraction method was adopted to carry out the correlated values of dielectric constant and dielectric loss at Ku-band. However, to validate the extracted parameters, a 10-GHz parallel-coupled line band-pass filter (BPF) was demonstrated by using the presented DPC substrate. This BPF has measured insertion loss of only 0.5dB and return loss of above 10dB in the passband. It obviously proved that the DPC metallized substrate is very capable for RF module packages and microwave components, with its excellent low loss performance.
{"title":"High-frequency characterization of direct plated copper metallized substrate and its application on microwave circuit","authors":"Chien-Cheng Wei, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru","doi":"10.1109/IMPACT.2009.5382279","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382279","url":null,"abstract":"Direct plated copper (DPC) metallized substrate is introduced, characterized, and demonstrated in this paper. The proposed DPC metallized substrate has the main advantages of high-frequency characteristics and excellent thermal management, due to the use of ceramic substrate and metallized copper conductor. Besides, the DPC process also provides high circuit density, fine pitch, and low cost potential compared to other technologies, like direct bonded copper (DBC), Low-Temperature Cofired Ceramics (LTCC), and High-Temperature Cofired Ceramics (HTCC) processes. Therefore, to characterize the electrical properties of DPC substrate for high-frequency applications, a simple extraction method was adopted to carry out the correlated values of dielectric constant and dielectric loss at Ku-band. However, to validate the extracted parameters, a 10-GHz parallel-coupled line band-pass filter (BPF) was demonstrated by using the presented DPC substrate. This BPF has measured insertion loss of only 0.5dB and return loss of above 10dB in the passband. It obviously proved that the DPC metallized substrate is very capable for RF module packages and microwave components, with its excellent low loss performance.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"2 1","pages":"681-684"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88852799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382237
Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee, Jenn-Ming Song, Yao-Ren Liu, M. Tsai
A strain-controllable dynamic bending method on WLCSP has been proposed in this paper. In order to identify the principle factor among the effects of stiffness attributed by different board level structures, the 0.4mm pitch WLCSP packages with Sn-4.0Ag-0.5Cu solder ball are used. This combination of WLCSP is considered to have the high stiffness in the structure. It is also shown that there are interactions between the SAC405 solder balls, the Al/Ni/Cu pad plating, the reflow profile and the flux chemistry. The experimental result shows that at the same strain rate range (∼106 µɛ/s), the fracture position occurrence happens in internal die at 11,000µɛ. This data indicates that the brittle fracture position transfers from general IMC layer to higher brittle layer in the component. The variation of the strain energy of materials and the stress concentration position which changes in different package sizes are speculated to be the cause of the fracture position transfer. Therefore, in our research; we will investigate the relationship between the IMC layer and microstructure of under bump metallization (UBM). The influence of different package dimensions will be discussed in this study, too.
{"title":"Failure mode evolution of WLCSP on board by dynamic bend method","authors":"Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee, Jenn-Ming Song, Yao-Ren Liu, M. Tsai","doi":"10.1109/IMPACT.2009.5382237","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382237","url":null,"abstract":"A strain-controllable dynamic bending method on WLCSP has been proposed in this paper. In order to identify the principle factor among the effects of stiffness attributed by different board level structures, the 0.4mm pitch WLCSP packages with Sn-4.0Ag-0.5Cu solder ball are used. This combination of WLCSP is considered to have the high stiffness in the structure. It is also shown that there are interactions between the SAC405 solder balls, the Al/Ni/Cu pad plating, the reflow profile and the flux chemistry. The experimental result shows that at the same strain rate range (∼106 µɛ/s), the fracture position occurrence happens in internal die at 11,000µɛ. This data indicates that the brittle fracture position transfers from general IMC layer to higher brittle layer in the component. The variation of the strain energy of materials and the stress concentration position which changes in different package sizes are speculated to be the cause of the fracture position transfer. Therefore, in our research; we will investigate the relationship between the IMC layer and microstructure of under bump metallization (UBM). The influence of different package dimensions will be discussed in this study, too.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"136 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86625659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382163
ChungJen Fu, D. Chang, C. Chen
In this paper, the effects of solder mask are studied and two types of solder mask are used in this study, include liquid type and dry film type. Ether liquid type or dry film type solder mask has its own advantage and disadvantage. For liquid type, it is a mature process and can be operated without vacuum environment. However, for dry film type, it needs to be operated in vacuum environment for preventing contamination and void, but dry film type could get better solder mask thickness uniformity and smaller roughness. The test vehicle of this study is 42.5mm*42.5mm Flip Chip Ball Grid Array (FCBGA) with 150um bump pitch composed with different solder mask material. Two kinds of substrate are evaluated in this study: liquid type solder mask (S/M1), dry film type solder mask (S/M2). Substrate roughness, adhesion test, PKG level coplanarity, PKG warpage and reliability test are conducted to evaluate the effect of dry film type and liquid type solder mask on substrate and PKG. The results shows that dry film type solder mask has lower roughness than liquid type. For the part of adhesion test between underfill and solder mask, dry film type solder mask shows similar adhesion strength to liquid type. Shadow moiré is employed to measure warpage and the results shows substrate with dry film solder mask has lower warpage. For the reliability life test, two packages are subjected to pre-condition of JEDEC MSL Level 3, TCT1000, HTSL1000 and HAST168, and both two packages passes reliability test.
本文研究了阻焊剂的作用，采用了两种类型的阻焊剂，包括液体型和干膜型。醚液型或干膜型阻焊膜各有优缺点。对于液体型，它是一个成熟的工艺，可以在没有真空的环境下操作。而对于干膜型，为了防止污染和空隙，需要在真空环境下操作，而干膜型可以获得更好的阻焊厚度均匀性和更小的粗糙度。本研究的试验载体为42.5mm*42.5mm凸距150um的倒装芯片球栅阵列(FCBGA)，由不同阻焊材料组成。本研究评估了两种衬底:液体型阻焊膜(S/M1)和干膜型阻焊膜(S/M2)。通过衬底粗糙度、附着力、PKG水平共面性、PKG挠曲度和可靠性试验，评价了干膜型和液体型阻焊剂对衬底和PKG的影响，结果表明，干膜型阻焊剂的粗糙度低于液体型阻焊剂。干膜型阻焊剂与液体型阻焊剂的附着强度相近。采用影模法测量翘曲量，结果表明采用干膜阻焊的基片翘曲量较低。在可靠性寿命测试中，两个封装分别经过JEDEC MSL Level 3、TCT1000、HTSL1000和HAST168的前置条件，两个封装均通过了可靠性测试。
{"title":"Film type solder mask evaluation for flip chip BGA","authors":"ChungJen Fu, D. Chang, C. Chen","doi":"10.1109/IMPACT.2009.5382163","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382163","url":null,"abstract":"In this paper, the effects of solder mask are studied and two types of solder mask are used in this study, include liquid type and dry film type. Ether liquid type or dry film type solder mask has its own advantage and disadvantage. For liquid type, it is a mature process and can be operated without vacuum environment. However, for dry film type, it needs to be operated in vacuum environment for preventing contamination and void, but dry film type could get better solder mask thickness uniformity and smaller roughness. The test vehicle of this study is 42.5mm*42.5mm Flip Chip Ball Grid Array (FCBGA) with 150um bump pitch composed with different solder mask material. Two kinds of substrate are evaluated in this study: liquid type solder mask (S/M1), dry film type solder mask (S/M2). Substrate roughness, adhesion test, PKG level coplanarity, PKG warpage and reliability test are conducted to evaluate the effect of dry film type and liquid type solder mask on substrate and PKG. The results shows that dry film type solder mask has lower roughness than liquid type. For the part of adhesion test between underfill and solder mask, dry film type solder mask shows similar adhesion strength to liquid type. Shadow moiré is employed to measure warpage and the results shows substrate with dry film solder mask has lower warpage. For the reliability life test, two packages are subjected to pre-condition of JEDEC MSL Level 3, TCT1000, HTSL1000 and HAST168, and both two packages passes reliability test.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"37 1","pages":"121-123"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89564170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382261
Shoukai Zhang, R. Mohanty, Xiaodong Jiang, R. Mao, J. Lee, Chuan Xia, K. Sweatman, D. Teoh
The widely recognized industry standard IPC-7525 has been used as the starting point for an experimental program that explores the effect of varying the keep out distance for 0201 and 0402 chip components, CSP and SOP with pitches down to 0.4mm, and larger components represented by CCGA. Other variables that were included in the experimental program to determine if they had an effect on the sensitivity of paste transfer to keep-out distance included stencil type, step height and solder type. In the first stage of the project the printing to each pad was measured with automated 3D SPI systems and optimum combinations of parameters identified by statistical analysis. In this paper the authors will explain the methodology chosen to achieve the project objectives and indicate the direction of likely future work. Early results indicate that a key objective of the project, to provide evidence to support the case for a reduction in the keep out
{"title":"iNEMI solder paste deposition project - First stage review optimizing solder paste printing for large and small components","authors":"Shoukai Zhang, R. Mohanty, Xiaodong Jiang, R. Mao, J. Lee, Chuan Xia, K. Sweatman, D. Teoh","doi":"10.1109/IMPACT.2009.5382261","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382261","url":null,"abstract":"The widely recognized industry standard IPC-7525 has been used as the starting point for an experimental program that explores the effect of varying the keep out distance for 0201 and 0402 chip components, CSP and SOP with pitches down to 0.4mm, and larger components represented by CCGA. Other variables that were included in the experimental program to determine if they had an effect on the sensitivity of paste transfer to keep-out distance included stencil type, step height and solder type. In the first stage of the project the printing to each pad was measured with automated 3D SPI systems and optimum combinations of parameters identified by statistical analysis. In this paper the authors will explain the methodology chosen to achieve the project objectives and indicate the direction of likely future work. Early results indicate that a key objective of the project, to provide evidence to support the case for a reduction in the keep out","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"6 1","pages":"620-623"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85254686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382238
M. Sano, C. Chou, T. Hung, Shin-Yueh Yang, Chao-Jen Huang, K. Chiang
The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.
{"title":"Reliability and parametric study on chip scale package under board-level drop test","authors":"M. Sano, C. Chou, T. Hung, Shin-Yueh Yang, Chao-Jen Huang, K. Chiang","doi":"10.1109/IMPACT.2009.5382238","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382238","url":null,"abstract":"The board level drop test is intended to evaluate and compare the drop performance of surface mount electronic components. The JEDEC standardize for board level drop test address test board construction, design, material, component locations and test conditions etc. However, in actual drop test conditions, continued drops usually loosen up the mounting screw consequently. This situation may cause the poor repeatability of the experiment. The uncertainty condition of the screw may consequently influence the dynamic behavior of the printed circuit board (PCB) assembly. The objective of this research is to study the uncertainty of the screw condition in relation to the dynamic response on the board level drop test by LS-DYNA3D. Both drop test experiments and dynamic simulation are executed. The modified input-G method, which considered the residuals of screw, was proposed to discuss the uncertainty of screw condition. Residual stress is applied in the tight screw condition. The result shows that a loose screw condition has higher first vibration amplitude of displacement, and the vibration frequency is lower than in a tight screw condition. It is also found that the chip scale package under the loose screw condition has worse reliability in the of drop test due to higher vibration magnitude. Several parametric studies including discussions on the chip thickness, chip size, dielectric layer thickness and hardness, and the solder ball distribution were performed to improve reliability.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"537-540"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81366372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382263
E.P.Y. Chou, Yung‐Yun Wang, C. Wan
Palladium nanoparticles were synthesized simply by reducing Pd ions which were attracted to electron nitrogen atom in poly(N-vinyl-2-pyrrolidone) (PVP). This Pd/PVP aqueous system was developed as the activator for electroless copper deposition. Compared with commercial Pd/Sn colloid that was easily oxidized by dissolved oxygen and agglomerated in the solution, Pd/PVP activator was stable without any Pd aggregation for a long time. Pd/PVP activator showed high catalytic activity as Pd/Sn colloid on flat FR-4 substrate (glass fiber reinforced epoxy). From back-light test for printed-through-hole (PTH) process, we found that micro-etching process would reduce catalytic activity of Pd/PVP activator and voids in PTH occurred especially on glass fiber. Adding phosphoric acid to Pd/PVP activator could improve back-light performance, but Pd nanoparticles precipitated in a few days. In this study, we found that H3PO4 molecule was the cause of Pd agglomeration by forming hydrogen bond with PVP. Pd nanoparticles would precipitate if the concentration of H3PO4 were high in the solution. IR spectra and UV-vis spectra proved that Pd/PVP activator would react with H3PO4 molecules to form a complex by hydrogen bond, and DLS analysis also showed that Pd/PVP/H3PO4 nanoparticles formed a larger hydrolysis cluster than Pd/PVP nanoparticles. TEM images gave the information about particle size and shape of Pd nanoparticles, and more information about dispersion and distance of Pd nanoparticles and Pd clusters could be obtained by the model fitting of SAXS data. The results showed that Pd/PVP/H3PO4 nanoparticles formed a looser structure than Pd/PVP nanoparticles. Since there is higher Cu deposition on epoxy when we use Pd/PVP/H3PO4 nanoparticles as activator, in PTH process, Cu deposition on glass fiber is improved by Cu deposition on epoxy nearby. So back-light performance become acceptable for PCBs industry.
{"title":"The study of the stability of Pd/PVP nanoparticles added with phosphoric acid and the activity to electroless Cu deposition","authors":"E.P.Y. Chou, Yung‐Yun Wang, C. Wan","doi":"10.1109/IMPACT.2009.5382263","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382263","url":null,"abstract":"Palladium nanoparticles were synthesized simply by reducing Pd ions which were attracted to electron nitrogen atom in poly(N-vinyl-2-pyrrolidone) (PVP). This Pd/PVP aqueous system was developed as the activator for electroless copper deposition. Compared with commercial Pd/Sn colloid that was easily oxidized by dissolved oxygen and agglomerated in the solution, Pd/PVP activator was stable without any Pd aggregation for a long time. Pd/PVP activator showed high catalytic activity as Pd/Sn colloid on flat FR-4 substrate (glass fiber reinforced epoxy). From back-light test for printed-through-hole (PTH) process, we found that micro-etching process would reduce catalytic activity of Pd/PVP activator and voids in PTH occurred especially on glass fiber. Adding phosphoric acid to Pd/PVP activator could improve back-light performance, but Pd nanoparticles precipitated in a few days. In this study, we found that H3PO4 molecule was the cause of Pd agglomeration by forming hydrogen bond with PVP. Pd nanoparticles would precipitate if the concentration of H3PO4 were high in the solution. IR spectra and UV-vis spectra proved that Pd/PVP activator would react with H3PO4 molecules to form a complex by hydrogen bond, and DLS analysis also showed that Pd/PVP/H3PO4 nanoparticles formed a larger hydrolysis cluster than Pd/PVP nanoparticles. TEM images gave the information about particle size and shape of Pd nanoparticles, and more information about dispersion and distance of Pd nanoparticles and Pd clusters could be obtained by the model fitting of SAXS data. The results showed that Pd/PVP/H3PO4 nanoparticles formed a looser structure than Pd/PVP nanoparticles. Since there is higher Cu deposition on epoxy when we use Pd/PVP/H3PO4 nanoparticles as activator, in PTH process, Cu deposition on glass fiber is improved by Cu deposition on epoxy nearby. So back-light performance become acceptable for PCBs industry.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"625-628"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90794955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382116
H. Kishi, T. Sasaki, N. Ueta, Ken Suzuki, H. Miura
Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced stress and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
{"title":"Multi-scale measurement of the change of the residual stress in a silicon chip during manufacturing from thin-film processing to packaging","authors":"H. Kishi, T. Sasaki, N. Ueta, Ken Suzuki, H. Miura","doi":"10.1109/IMPACT.2009.5382116","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382116","url":null,"abstract":"Both thermal and intrinsic stresses that occur during thin-film processing and packaging dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method. The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-MPa to about 15%/100-MPa by decreasing the gate length of the transistors from 400 nm to 150 nm. So, it showed miniaturization of transistors increased the stress sensitivity of the performance. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM). The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. Next, the change of the residual stress caused by the interference of the stress concentration field between gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making one slit by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. In addition, the change of residual stress was increased with the more decreased width of slits. It was confirmed, therefore, that both the thin film process-induced stress and the packaging-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"12 3 1","pages":"293-296"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82391378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382132
P. Liang
In the past, high-frequency communication applications put emphasis on low loss while high speed signal transmission is required to achieve the integrity of the signal. In order to ensure the target of low loss on the CCL materials, mmost studies focus on how to reduce the polarity for resin system to achieve low Dk and low tan δ to improve the signal characteristics of high-spped transmission. The recent rapid development of IT industry demand for high-frequency communications, coupled with many researches show the composition of the CCL material, such as copper foil, glass fiber yarn and resin modification. This study intends to analyze the roughness of copper foil matte side, glass type and spreading uniformity to realize the impact on high frequency signals. Finally, we hope we can find a low cost solution for high frequency communications applications.
{"title":"The effects of CCL composition on signal loss for high frequency application","authors":"P. Liang","doi":"10.1109/IMPACT.2009.5382132","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382132","url":null,"abstract":"In the past, high-frequency communication applications put emphasis on low loss while high speed signal transmission is required to achieve the integrity of the signal. In order to ensure the target of low loss on the CCL materials, mmost studies focus on how to reduce the polarity for resin system to achieve low Dk and low tan δ to improve the signal characteristics of high-spped transmission. The recent rapid development of IT industry demand for high-frequency communications, coupled with many researches show the composition of the CCL material, such as copper foil, glass fiber yarn and resin modification. This study intends to analyze the roughness of copper foil matte side, glass type and spreading uniformity to realize the impact on high frequency signals. Finally, we hope we can find a low cost solution for high frequency communications applications.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"15 1","pages":"236-239"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82468713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382253
S. Lin, R. Huang, C. Chiu
In this paper, the thermal analysis is carried out by the combination of actual thermal measurement and numerical finite element simulation to investigate insightfully the thermal characteristics of each element in the whole assembly of the LED lighting system (LLS). Based on the thermo/fluid coupled field numerical simulation, the ANSYS¿,s finite elements are used to model the detailed assembly parts in the high-power LLS. The highpower LLS samples were assembled by soldering the LED-Ceramic package on a copper sheet, which was then attached to an aluminum alloy heat sink using thermally conductive adhesive. Four different ceramic materials: AlN, SiC, LTCC with Ag thermal via and Al2O3, were studied as ceramic thermally conductive substrates (CTCS) for the high power LED dies' packaging. The ceramic sub-mounts were produced by packing multiple LED chips with silicone resin containing phosphors coated on a CTCS. The thermal resistances of ceramic sub-mounts with the same configuration were determined to be 0.1411°C/W for AlN, 0.1778°C/W for SiC, 1.9732°C/W for LTCC with 30 volume% of silver thermal vias, and 2.0262°C/W for Al2O3. Results indicate that ceramic materials are very suitable for reducing the thermal management issues for high-power LED lighting applications.
{"title":"Investigation of thermally conductive ceramic substrates for high-power LED application","authors":"S. Lin, R. Huang, C. Chiu","doi":"10.1109/IMPACT.2009.5382253","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382253","url":null,"abstract":"In this paper, the thermal analysis is carried out by the combination of actual thermal measurement and numerical finite element simulation to investigate insightfully the thermal characteristics of each element in the whole assembly of the LED lighting system (LLS). Based on the thermo/fluid coupled field numerical simulation, the ANSYS¿,s finite elements are used to model the detailed assembly parts in the high-power LLS. The highpower LLS samples were assembled by soldering the LED-Ceramic package on a copper sheet, which was then attached to an aluminum alloy heat sink using thermally conductive adhesive. Four different ceramic materials: AlN, SiC, LTCC with Ag thermal via and Al2O3, were studied as ceramic thermally conductive substrates (CTCS) for the high power LED dies' packaging. The ceramic sub-mounts were produced by packing multiple LED chips with silicone resin containing phosphors coated on a CTCS. The thermal resistances of ceramic sub-mounts with the same configuration were determined to be 0.1411°C/W for AlN, 0.1778°C/W for SiC, 1.9732°C/W for LTCC with 30 volume% of silver thermal vias, and 2.0262°C/W for Al2O3. Results indicate that ceramic materials are very suitable for reducing the thermal management issues for high-power LED lighting applications.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"15 1","pages":"589-592"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87207944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382122
Wei-Kai Liou, Y. Yen, Chien-Chung Jao
This study investigates aging effects on interfacial reactions between Sn-9wt%Zn-x wt% (SZ-xCu) alloys and Au substrate. The Au3Zn7/AuZn2/AuZn and Au3Zn7/AuZn phases respectively formed in the SZ/Au and SZ-1Cu/Au couples aged at 160°C for 24 hours. Only the AuSn phase was found at the SZ-4 Cu/Au interface. Extending the aging time to 800 hours, Sn became a dominant diffusion element. Binary Au-Sn phases and the metastable Au-Zn-Sn ternary phase, Au33–36 Zn35–36Sn29–31, was formed at the interface. The aging effect causing the changes of dominant diffusion element and concentration of Zn, Cu in the solder is the main reasons to change the sequence of the IMC formation in the SZ-xCu/Au systems.
{"title":"Aging effects on interfacial reactions between Cu addition into the Sn-9Zn lead-free solder and Au substrate","authors":"Wei-Kai Liou, Y. Yen, Chien-Chung Jao","doi":"10.1109/IMPACT.2009.5382122","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382122","url":null,"abstract":"This study investigates aging effects on interfacial reactions between Sn-9wt%Zn-x wt% (SZ-xCu) alloys and Au substrate. The Au<inf>3</inf>Zn<inf>7</inf>/AuZn<inf>2</inf>/AuZn and Au<inf>3</inf>Zn<inf>7</inf>/AuZn phases respectively formed in the SZ/Au and SZ-1Cu/Au couples aged at 160°C for 24 hours. Only the AuSn phase was found at the SZ-4 Cu/Au interface. Extending the aging time to 800 hours, Sn became a dominant diffusion element. Binary Au-Sn phases and the metastable Au-Zn-Sn ternary phase, Au<inf>33–36</inf> Zn<inf>35–36</inf>Sn<inf>29–31</inf>, was formed at the interface. The aging effect causing the changes of dominant diffusion element and concentration of Zn, Cu in the solder is the main reasons to change the sequence of the IMC formation in the SZ-xCu/Au systems.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"224 1","pages":"271-273"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73200893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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