Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382202
Bor-Tsuen Wang, Fu-Xiang Hsu, Xiu-Wei Liang, Chen-Hsiung Hung, Y. Lai, Chang-Lin Yeh, Ying-Chih Lee
The printed circuit board (PCB) subject to vibration and thermal couple loading is of great interest. This work presents both theoretical analysis and experimental verification for the PCB in heating condition subject to random vibration. The designed heating pad is used as the heating source attached to the package on PCB by providing constant temperature inputs. The calibrated finite element model of PCB in fixture condition is employed to perform thermal analysis for the PCB subjected to the fixed high temperature at the package surface. The thermal response of the PCB can be determined, and thus the spectrum response analysis of the PCB including the thermal effect for random excitation according to JEDEC specification is carried out. The temperature distribution over the PCB in heating condition is monitored by the digital infrared thermography and compared with that of finite element analysis (FEA). The acceleration spectral responses on the PCB during random vibration test with thermal effect are also recorded. Results show that the predicted temperature distribution for the heated PCB and acceleration response due to thermal and random vibration compound loadings agree reasonably between the FEA and experiments. The stress fields on the PCB subject to the thermal input and random vibration excitation can then be obtained and evaluated for its possible fatigue failures due to the compound loading effects. This work presents the analytical solutions via the commercial FE code for the PCB subject to compound loadings for thermal input and random vibration excitation. The predicted results are well validated by comparing with experiments. The developed methodology will be beneficial for further study of PCB and its package reliability in considering both thermal and vibration inputs simultaneously.
{"title":"Response prediction and verification for PCB with package due to thermal and random vibration coupling effects","authors":"Bor-Tsuen Wang, Fu-Xiang Hsu, Xiu-Wei Liang, Chen-Hsiung Hung, Y. Lai, Chang-Lin Yeh, Ying-Chih Lee","doi":"10.1109/IMPACT.2009.5382202","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382202","url":null,"abstract":"The printed circuit board (PCB) subject to vibration and thermal couple loading is of great interest. This work presents both theoretical analysis and experimental verification for the PCB in heating condition subject to random vibration. The designed heating pad is used as the heating source attached to the package on PCB by providing constant temperature inputs. The calibrated finite element model of PCB in fixture condition is employed to perform thermal analysis for the PCB subjected to the fixed high temperature at the package surface. The thermal response of the PCB can be determined, and thus the spectrum response analysis of the PCB including the thermal effect for random excitation according to JEDEC specification is carried out. The temperature distribution over the PCB in heating condition is monitored by the digital infrared thermography and compared with that of finite element analysis (FEA). The acceleration spectral responses on the PCB during random vibration test with thermal effect are also recorded. Results show that the predicted temperature distribution for the heated PCB and acceleration response due to thermal and random vibration compound loadings agree reasonably between the FEA and experiments. The stress fields on the PCB subject to the thermal input and random vibration excitation can then be obtained and evaluated for its possible fatigue failures due to the compound loading effects. This work presents the analytical solutions via the commercial FE code for the PCB subject to compound loadings for thermal input and random vibration excitation. The predicted results are well validated by comparing with experiments. The developed methodology will be beneficial for further study of PCB and its package reliability in considering both thermal and vibration inputs simultaneously.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"401-404"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89454934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382215
S. Kim, Kyudae Hwang, Jong-Chul Moon, S. Karng
Thermal management for two array types of a serial circulation and a two-way parallel circulation using six mini liquid-cooled cold plates were experimentally measured in this study. In order to reduce weight of the cooling devices for humanoid robot cooling, the cold plates were covered with non-metallic material (polycarbonate, PC). Six cold plates attached on 10 x 10 mm2 copper base: 0.5 x 0.5 mm2 pin-finned surfaces of 1.5 mm high with 0.5 mm array spacing, was mounted on six copper heating blocks with isothermal conditions of 50~90°C, respectively. In order to compare thermal characteristics according to two circulation types, the surface temperatures of heating blocks and the cooling water temperatures at inlets and outlets of cold plates were measured. From the results, it was found that a two-way parallel circulation was better performance than a serial circulation in terms of total thermal resistance, total heat transfer rate, and surface temperature rises from first heating block to last one for six multiple cold plates.
{"title":"Thermal management of liquid-cooled cold plates for multiple heat sources in a humanoid robot","authors":"S. Kim, Kyudae Hwang, Jong-Chul Moon, S. Karng","doi":"10.1109/IMPACT.2009.5382215","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382215","url":null,"abstract":"Thermal management for two array types of a serial circulation and a two-way parallel circulation using six mini liquid-cooled cold plates were experimentally measured in this study. In order to reduce weight of the cooling devices for humanoid robot cooling, the cold plates were covered with non-metallic material (polycarbonate, PC). Six cold plates attached on 10 x 10 mm2 copper base: 0.5 x 0.5 mm2 pin-finned surfaces of 1.5 mm high with 0.5 mm array spacing, was mounted on six copper heating blocks with isothermal conditions of 50~90°C, respectively. In order to compare thermal characteristics according to two circulation types, the surface temperatures of heating blocks and the cooling water temperatures at inlets and outlets of cold plates were measured. From the results, it was found that a two-way parallel circulation was better performance than a serial circulation in terms of total thermal resistance, total heat transfer rate, and surface temperature rises from first heating block to last one for six multiple cold plates.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"96 1","pages":"453-456"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74750823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382159
R. Sung, K. Chiang, J. Lai, Yu-Po Wang
Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause Simultaneous Switching Noises (SSN). In this paper, some analysis on this design was evaluated.
{"title":"Guarding trace and ground via-hole analysis for DDR interface designed in high-speed packages","authors":"R. Sung, K. Chiang, J. Lai, Yu-Po Wang","doi":"10.1109/IMPACT.2009.5382159","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382159","url":null,"abstract":"Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause Simultaneous Switching Noises (SSN). In this paper, some analysis on this design was evaluated.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"14 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80020131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382239
F. Tai, J. Duh
The high impact speeds (200, 1000 mm/s) in the pendulum test were conducted on the SAC305/ENIG joints aged at 150°C for 500 and 1000 h, respectively. The preliminary results exhibit that the peak force, pre-peak energy and total impact energy except post-energy of as-reflowed are larger than those of as-aged samples regardless of aging time. For the as-reflowed SAC305/ENIG joint (0.3 mm at diameter), the peak force is 2.592 N at the speed of the 1000 mm/s; the
{"title":"Interfacial toughness evaluation of SAC305 solder bump with pendulum impact test","authors":"F. Tai, J. Duh","doi":"10.1109/IMPACT.2009.5382239","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382239","url":null,"abstract":"The high impact speeds (200, 1000 mm/s) in the pendulum test were conducted on the SAC305/ENIG joints aged at 150°C for 500 and 1000 h, respectively. The preliminary results exhibit that the peak force, pre-peak energy and total impact energy except post-energy of as-reflowed are larger than those of as-aged samples regardless of aging time. For the as-reflowed SAC305/ENIG joint (0.3 mm at diameter), the peak force is 2.592 N at the speed of the 1000 mm/s; the","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"66 1","pages":"541-544"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83918541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382287
Hsien-Chie Cheng, Kun-Yu Hsieh
This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.
{"title":"Design optimization and analysis of a novel nanocomposite-film typed flip chip technology","authors":"Hsien-Chie Cheng, Kun-Yu Hsieh","doi":"10.1109/IMPACT.2009.5382287","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382287","url":null,"abstract":"This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"18 1","pages":"713-717"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84441132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382261
Shoukai Zhang, R. Mohanty, Xiaodong Jiang, R. Mao, J. Lee, Chuan Xia, K. Sweatman, D. Teoh
The widely recognized industry standard IPC-7525 has been used as the starting point for an experimental program that explores the effect of varying the keep out distance for 0201 and 0402 chip components, CSP and SOP with pitches down to 0.4mm, and larger components represented by CCGA. Other variables that were included in the experimental program to determine if they had an effect on the sensitivity of paste transfer to keep-out distance included stencil type, step height and solder type. In the first stage of the project the printing to each pad was measured with automated 3D SPI systems and optimum combinations of parameters identified by statistical analysis. In this paper the authors will explain the methodology chosen to achieve the project objectives and indicate the direction of likely future work. Early results indicate that a key objective of the project, to provide evidence to support the case for a reduction in the keep out
{"title":"iNEMI solder paste deposition project - First stage review optimizing solder paste printing for large and small components","authors":"Shoukai Zhang, R. Mohanty, Xiaodong Jiang, R. Mao, J. Lee, Chuan Xia, K. Sweatman, D. Teoh","doi":"10.1109/IMPACT.2009.5382261","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382261","url":null,"abstract":"The widely recognized industry standard IPC-7525 has been used as the starting point for an experimental program that explores the effect of varying the keep out distance for 0201 and 0402 chip components, CSP and SOP with pitches down to 0.4mm, and larger components represented by CCGA. Other variables that were included in the experimental program to determine if they had an effect on the sensitivity of paste transfer to keep-out distance included stencil type, step height and solder type. In the first stage of the project the printing to each pad was measured with automated 3D SPI systems and optimum combinations of parameters identified by statistical analysis. In this paper the authors will explain the methodology chosen to achieve the project objectives and indicate the direction of likely future work. Early results indicate that a key objective of the project, to provide evidence to support the case for a reduction in the keep out","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"6 1","pages":"620-623"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85254686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382279
Chien-Cheng Wei, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru
Direct plated copper (DPC) metallized substrate is introduced, characterized, and demonstrated in this paper. The proposed DPC metallized substrate has the main advantages of high-frequency characteristics and excellent thermal management, due to the use of ceramic substrate and metallized copper conductor. Besides, the DPC process also provides high circuit density, fine pitch, and low cost potential compared to other technologies, like direct bonded copper (DBC), Low-Temperature Cofired Ceramics (LTCC), and High-Temperature Cofired Ceramics (HTCC) processes. Therefore, to characterize the electrical properties of DPC substrate for high-frequency applications, a simple extraction method was adopted to carry out the correlated values of dielectric constant and dielectric loss at Ku-band. However, to validate the extracted parameters, a 10-GHz parallel-coupled line band-pass filter (BPF) was demonstrated by using the presented DPC substrate. This BPF has measured insertion loss of only 0.5dB and return loss of above 10dB in the passband. It obviously proved that the DPC metallized substrate is very capable for RF module packages and microwave components, with its excellent low loss performance.
{"title":"High-frequency characterization of direct plated copper metallized substrate and its application on microwave circuit","authors":"Chien-Cheng Wei, Chin-Ta Fan, Ta-Hsiang Chiang, Ming-Kuen Chiu, S. Ru","doi":"10.1109/IMPACT.2009.5382279","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382279","url":null,"abstract":"Direct plated copper (DPC) metallized substrate is introduced, characterized, and demonstrated in this paper. The proposed DPC metallized substrate has the main advantages of high-frequency characteristics and excellent thermal management, due to the use of ceramic substrate and metallized copper conductor. Besides, the DPC process also provides high circuit density, fine pitch, and low cost potential compared to other technologies, like direct bonded copper (DBC), Low-Temperature Cofired Ceramics (LTCC), and High-Temperature Cofired Ceramics (HTCC) processes. Therefore, to characterize the electrical properties of DPC substrate for high-frequency applications, a simple extraction method was adopted to carry out the correlated values of dielectric constant and dielectric loss at Ku-band. However, to validate the extracted parameters, a 10-GHz parallel-coupled line band-pass filter (BPF) was demonstrated by using the presented DPC substrate. This BPF has measured insertion loss of only 0.5dB and return loss of above 10dB in the passband. It obviously proved that the DPC metallized substrate is very capable for RF module packages and microwave components, with its excellent low loss performance.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"2 1","pages":"681-684"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88852799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382222
A. Zee, R. Massey, H. Reischer
In multi-layer printed circuit board (PCB) manufacturing, adhesion promoters are applied between the inner layer copper surface and prepreg resin to ensure superior bonding reliability. Traditional adhesion promoters used over the last decade include processes such as black oxide and oxide replacement processes. Both inner layer bonding enhancement processes apply a coating or chemically etch the copper surface to create certain amount of roughness and provide mechanical bonding. Most oxide replacement processes also cover the roughened surface with organic coatings that further improves the inner layer adhesion through chemical bonding as well.
{"title":"Impact of surface treatment on high frequency signal loss characteristics","authors":"A. Zee, R. Massey, H. Reischer","doi":"10.1109/IMPACT.2009.5382222","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382222","url":null,"abstract":"In multi-layer printed circuit board (PCB) manufacturing, adhesion promoters are applied between the inner layer copper surface and prepreg resin to ensure superior bonding reliability. Traditional adhesion promoters used over the last decade include processes such as black oxide and oxide replacement processes. Both inner layer bonding enhancement processes apply a coating or chemically etch the copper surface to create certain amount of roughness and provide mechanical bonding. Most oxide replacement processes also cover the roughened surface with organic coatings that further improves the inner layer adhesion through chemical bonding as well.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"23 1","pages":"474-477"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89673084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382160
W. Y. Huang, E. Chen, D. Jiang, Yu Po Wang, J. Chiang, F. Tsai, R. Huang, E. Lee, I. Chang
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.
{"title":"Stress evaluations in micro bump structures of FCBGA","authors":"W. Y. Huang, E. Chen, D. Jiang, Yu Po Wang, J. Chiang, F. Tsai, R. Huang, E. Lee, I. Chang","doi":"10.1109/IMPACT.2009.5382160","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382160","url":null,"abstract":"System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"140-143"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89253494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382163
ChungJen Fu, D. Chang, C. Chen
In this paper, the effects of solder mask are studied and two types of solder mask are used in this study, include liquid type and dry film type. Ether liquid type or dry film type solder mask has its own advantage and disadvantage. For liquid type, it is a mature process and can be operated without vacuum environment. However, for dry film type, it needs to be operated in vacuum environment for preventing contamination and void, but dry film type could get better solder mask thickness uniformity and smaller roughness. The test vehicle of this study is 42.5mm*42.5mm Flip Chip Ball Grid Array (FCBGA) with 150um bump pitch composed with different solder mask material. Two kinds of substrate are evaluated in this study: liquid type solder mask (S/M1), dry film type solder mask (S/M2). Substrate roughness, adhesion test, PKG level coplanarity, PKG warpage and reliability test are conducted to evaluate the effect of dry film type and liquid type solder mask on substrate and PKG. The results shows that dry film type solder mask has lower roughness than liquid type. For the part of adhesion test between underfill and solder mask, dry film type solder mask shows similar adhesion strength to liquid type. Shadow moiré is employed to measure warpage and the results shows substrate with dry film solder mask has lower warpage. For the reliability life test, two packages are subjected to pre-condition of JEDEC MSL Level 3, TCT1000, HTSL1000 and HAST168, and both two packages passes reliability test.
本文研究了阻焊剂的作用，采用了两种类型的阻焊剂，包括液体型和干膜型。醚液型或干膜型阻焊膜各有优缺点。对于液体型，它是一个成熟的工艺，可以在没有真空的环境下操作。而对于干膜型，为了防止污染和空隙，需要在真空环境下操作，而干膜型可以获得更好的阻焊厚度均匀性和更小的粗糙度。本研究的试验载体为42.5mm*42.5mm凸距150um的倒装芯片球栅阵列(FCBGA)，由不同阻焊材料组成。本研究评估了两种衬底:液体型阻焊膜(S/M1)和干膜型阻焊膜(S/M2)。通过衬底粗糙度、附着力、PKG水平共面性、PKG挠曲度和可靠性试验，评价了干膜型和液体型阻焊剂对衬底和PKG的影响，结果表明，干膜型阻焊剂的粗糙度低于液体型阻焊剂。干膜型阻焊剂与液体型阻焊剂的附着强度相近。采用影模法测量翘曲量，结果表明采用干膜阻焊的基片翘曲量较低。在可靠性寿命测试中，两个封装分别经过JEDEC MSL Level 3、TCT1000、HTSL1000和HAST168的前置条件，两个封装均通过了可靠性测试。
{"title":"Film type solder mask evaluation for flip chip BGA","authors":"ChungJen Fu, D. Chang, C. Chen","doi":"10.1109/IMPACT.2009.5382163","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382163","url":null,"abstract":"In this paper, the effects of solder mask are studied and two types of solder mask are used in this study, include liquid type and dry film type. Ether liquid type or dry film type solder mask has its own advantage and disadvantage. For liquid type, it is a mature process and can be operated without vacuum environment. However, for dry film type, it needs to be operated in vacuum environment for preventing contamination and void, but dry film type could get better solder mask thickness uniformity and smaller roughness. The test vehicle of this study is 42.5mm*42.5mm Flip Chip Ball Grid Array (FCBGA) with 150um bump pitch composed with different solder mask material. Two kinds of substrate are evaluated in this study: liquid type solder mask (S/M1), dry film type solder mask (S/M2). Substrate roughness, adhesion test, PKG level coplanarity, PKG warpage and reliability test are conducted to evaluate the effect of dry film type and liquid type solder mask on substrate and PKG. The results shows that dry film type solder mask has lower roughness than liquid type. For the part of adhesion test between underfill and solder mask, dry film type solder mask shows similar adhesion strength to liquid type. Shadow moiré is employed to measure warpage and the results shows substrate with dry film solder mask has lower warpage. For the reliability life test, two packages are subjected to pre-condition of JEDEC MSL Level 3, TCT1000, HTSL1000 and HAST168, and both two packages passes reliability test.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"37 1","pages":"121-123"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89564170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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