Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382225
Toru Takahashi
Ever increasing need for smaller and functionally more integrated electronics devices such as smart phone, IC package substrate is forcing changes in materials for PWB imaging. This paper will provide insights how new materials developments are offering improved capabilities to produce such a high-end, fine-line PWBs along with imaging process considerations. The fabrication processes involved in the production of fine-line printed wiring boards will be also reviewed in some detail, between subtractive processes (which will not meet future needs) and semi-additive processes as well as emerging damascene-type of structure. This paper will highlight an overview of the importance that material and process selection has on the capability of PWB fabricators to meet the challenges in the future and provide insights into future direction based on evolving market needs
{"title":"Image transfer solutions for future demand","authors":"Toru Takahashi","doi":"10.1109/IMPACT.2009.5382225","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382225","url":null,"abstract":"Ever increasing need for smaller and functionally more integrated electronics devices such as smart phone, IC package substrate is forcing changes in materials for PWB imaging. This paper will provide insights how new materials developments are offering improved capabilities to produce such a high-end, fine-line PWBs along with imaging process considerations. The fabrication processes involved in the production of fine-line printed wiring boards will be also reviewed in some detail, between subtractive processes (which will not meet future needs) and semi-additive processes as well as emerging damascene-type of structure. This paper will highlight an overview of the importance that material and process selection has on the capability of PWB fabricators to meet the challenges in the future and provide insights into future direction based on evolving market needs","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"36 1","pages":"490-492"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73307650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382215
S. Kim, Kyudae Hwang, Jong-Chul Moon, S. Karng
Thermal management for two array types of a serial circulation and a two-way parallel circulation using six mini liquid-cooled cold plates were experimentally measured in this study. In order to reduce weight of the cooling devices for humanoid robot cooling, the cold plates were covered with non-metallic material (polycarbonate, PC). Six cold plates attached on 10 x 10 mm2 copper base: 0.5 x 0.5 mm2 pin-finned surfaces of 1.5 mm high with 0.5 mm array spacing, was mounted on six copper heating blocks with isothermal conditions of 50~90°C, respectively. In order to compare thermal characteristics according to two circulation types, the surface temperatures of heating blocks and the cooling water temperatures at inlets and outlets of cold plates were measured. From the results, it was found that a two-way parallel circulation was better performance than a serial circulation in terms of total thermal resistance, total heat transfer rate, and surface temperature rises from first heating block to last one for six multiple cold plates.
{"title":"Thermal management of liquid-cooled cold plates for multiple heat sources in a humanoid robot","authors":"S. Kim, Kyudae Hwang, Jong-Chul Moon, S. Karng","doi":"10.1109/IMPACT.2009.5382215","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382215","url":null,"abstract":"Thermal management for two array types of a serial circulation and a two-way parallel circulation using six mini liquid-cooled cold plates were experimentally measured in this study. In order to reduce weight of the cooling devices for humanoid robot cooling, the cold plates were covered with non-metallic material (polycarbonate, PC). Six cold plates attached on 10 x 10 mm2 copper base: 0.5 x 0.5 mm2 pin-finned surfaces of 1.5 mm high with 0.5 mm array spacing, was mounted on six copper heating blocks with isothermal conditions of 50~90°C, respectively. In order to compare thermal characteristics according to two circulation types, the surface temperatures of heating blocks and the cooling water temperatures at inlets and outlets of cold plates were measured. From the results, it was found that a two-way parallel circulation was better performance than a serial circulation in terms of total thermal resistance, total heat transfer rate, and surface temperature rises from first heating block to last one for six multiple cold plates.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"96 1","pages":"453-456"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74750823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382134
Mu-Chun Wang, Z. Hsieh, Kuo-Shu Huang, C. Tu, Shuang-Yuan Chen, Heng-Sheng Huang
In general, the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging) is able to be integrated by 7-step processes, including two masks and one set of stencil plate. After the formation of solder ball, the specified professional probe card is needed to verify whether the electric functions of this packaged IC are good. After this step, the wafer grinding, the wafer cutting, the chip choice and the final test (F/T) are gradually adopted to proceed. Finally, due to the customer's need, the shipping package type to customers is, generally, tray or tape and reel. Although the stencil printing technology can provide the mass-production capability, the mainly existing problems of this technology are the quality of manufacturing steel plate, the coating operation for solder paste, and the flatness of wafer surface. These issues usually constrain the minimization of the size of the solder ball and the pitch. Thinking to solve these issues, this package technology is still feasible in assembly competition.
{"title":"A study to stencil printing technology for solder bump assembly","authors":"Mu-Chun Wang, Z. Hsieh, Kuo-Shu Huang, C. Tu, Shuang-Yuan Chen, Heng-Sheng Huang","doi":"10.1109/IMPACT.2009.5382134","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382134","url":null,"abstract":"In general, the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging) is able to be integrated by 7-step processes, including two masks and one set of stencil plate. After the formation of solder ball, the specified professional probe card is needed to verify whether the electric functions of this packaged IC are good. After this step, the wafer grinding, the wafer cutting, the chip choice and the final test (F/T) are gradually adopted to proceed. Finally, due to the customer's need, the shipping package type to customers is, generally, tray or tape and reel. Although the stencil printing technology can provide the mass-production capability, the mainly existing problems of this technology are the quality of manufacturing steel plate, the coating operation for solder paste, and the flatness of wafer surface. These issues usually constrain the minimization of the size of the solder ball and the pitch. Thinking to solve these issues, this package technology is still feasible in assembly competition.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"54 1","pages":"231-234"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80351122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382159
R. Sung, K. Chiang, J. Lai, Yu-Po Wang
Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause Simultaneous Switching Noises (SSN). In this paper, some analysis on this design was evaluated.
{"title":"Guarding trace and ground via-hole analysis for DDR interface designed in high-speed packages","authors":"R. Sung, K. Chiang, J. Lai, Yu-Po Wang","doi":"10.1109/IMPACT.2009.5382159","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382159","url":null,"abstract":"Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause Simultaneous Switching Noises (SSN). In this paper, some analysis on this design was evaluated.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"14 1","pages":"136-139"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80020131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382287
Hsien-Chie Cheng, Kun-Yu Hsieh
This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.
{"title":"Design optimization and analysis of a novel nanocomposite-film typed flip chip technology","authors":"Hsien-Chie Cheng, Kun-Yu Hsieh","doi":"10.1109/IMPACT.2009.5382287","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382287","url":null,"abstract":"This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"18 1","pages":"713-717"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84441132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382239
F. Tai, J. Duh
The high impact speeds (200, 1000 mm/s) in the pendulum test were conducted on the SAC305/ENIG joints aged at 150°C for 500 and 1000 h, respectively. The preliminary results exhibit that the peak force, pre-peak energy and total impact energy except post-energy of as-reflowed are larger than those of as-aged samples regardless of aging time. For the as-reflowed SAC305/ENIG joint (0.3 mm at diameter), the peak force is 2.592 N at the speed of the 1000 mm/s; the
{"title":"Interfacial toughness evaluation of SAC305 solder bump with pendulum impact test","authors":"F. Tai, J. Duh","doi":"10.1109/IMPACT.2009.5382239","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382239","url":null,"abstract":"The high impact speeds (200, 1000 mm/s) in the pendulum test were conducted on the SAC305/ENIG joints aged at 150°C for 500 and 1000 h, respectively. The preliminary results exhibit that the peak force, pre-peak energy and total impact energy except post-energy of as-reflowed are larger than those of as-aged samples regardless of aging time. For the as-reflowed SAC305/ENIG joint (0.3 mm at diameter), the peak force is 2.592 N at the speed of the 1000 mm/s; the","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"66 1","pages":"541-544"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83918541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382160
W. Y. Huang, E. Chen, D. Jiang, Yu Po Wang, J. Chiang, F. Tsai, R. Huang, E. Lee, I. Chang
System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.
{"title":"Stress evaluations in micro bump structures of FCBGA","authors":"W. Y. Huang, E. Chen, D. Jiang, Yu Po Wang, J. Chiang, F. Tsai, R. Huang, E. Lee, I. Chang","doi":"10.1109/IMPACT.2009.5382160","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382160","url":null,"abstract":"System in Package(SiP) includes technologies of Multi-chip Module(MCM), Multi-chip Package(MCP), stacked die, Package on Package(PoP), Package in Package(PiP) and Embedded substrate. While Au wire bonding technology is commonly used as current SIP interconnection solution, take Staked Die structure for example, with increasing stack die number the upper die needs longer wire bonding length for signal interconnection and results in lower electrical performance for whole system. In addition, wire bonding technology as Stacked die solution requires spacer die insertion between functional chips for bonding space and thus increases total package thickness. In order to achieve better electrical performance and reduce form factor, a new fine pitch bump technology of “Micro Bump” structure is developed with metal bump for both top and bottom chips. Micro bump structure is one of the key technologies of Trough Silicon Vias (TSV) and is used in chip to chip interconnection with the dimension of Micro bump smaller than typical flip chip bump.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"1 1","pages":"140-143"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89253494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382222
A. Zee, R. Massey, H. Reischer
In multi-layer printed circuit board (PCB) manufacturing, adhesion promoters are applied between the inner layer copper surface and prepreg resin to ensure superior bonding reliability. Traditional adhesion promoters used over the last decade include processes such as black oxide and oxide replacement processes. Both inner layer bonding enhancement processes apply a coating or chemically etch the copper surface to create certain amount of roughness and provide mechanical bonding. Most oxide replacement processes also cover the roughened surface with organic coatings that further improves the inner layer adhesion through chemical bonding as well.
{"title":"Impact of surface treatment on high frequency signal loss characteristics","authors":"A. Zee, R. Massey, H. Reischer","doi":"10.1109/IMPACT.2009.5382222","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382222","url":null,"abstract":"In multi-layer printed circuit board (PCB) manufacturing, adhesion promoters are applied between the inner layer copper surface and prepreg resin to ensure superior bonding reliability. Traditional adhesion promoters used over the last decade include processes such as black oxide and oxide replacement processes. Both inner layer bonding enhancement processes apply a coating or chemically etch the copper surface to create certain amount of roughness and provide mechanical bonding. Most oxide replacement processes also cover the roughened surface with organic coatings that further improves the inner layer adhesion through chemical bonding as well.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"23 1","pages":"474-477"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89673084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382301
W. Jong, S. Peng
Due to the environmental protection issues and regulations, a lot of electronic material suppliers try to search for the replacement materials which include the lead-free solder joints and the anisotropic conductive films (ACFs). ACF is widely used in high quality, excellent signal interconnection and fine pitch products. Nevertheless, during the fast flow and curing process of the electronic material, the risk of voiding may be increased. This study focuses on the characteristics and phenomena of a new-type ACF on the outer lead bonding (OLB) for flip chip on flex substrate (FCOF) assembly. Firstly, the thermal response and curing capability of the new-type ACF is investigated by the experiment. And the numerical simulation is used by computer aided engineering (CAE) that shows the heating effect of components on the bonding process. Both the simulated and experimental results can obtain the similar thermal behaviors. For the reliability assessment of the new-type ACF, the experiment procedures are adjusted three parameters of temperature, pressure and time under the bonding process. It can be easily discovered that the delaminations or cracks is caused by a lower compliance behavior of the interfaces between bumps on the polyimide (PI) substrate and indium tin oxides (ITOs) on the glass substrate. In order to evaluate the adhesive strength of ACF through the thermal loading, the strength of FCOF assembly is measured by a 90-degree peel test and is verified by the CAE simulation. In this study, the minimum peel strength of the new-type ACF has to be greater than 400 g/cm in order to satisfy the specification. Then, a stripped meshed model is simulated to understand the fracture growth between each interface under a constant speed of 8mm/sec. It can be found that the initial creak starts from the ACF-glass substrate interface and then propagates to the ITO. Finally, the swelling phenomenon of the new-type ACF is investigated. It shows that the swelling will not affect the structure of components and the reliability assessment is good.
{"title":"A study for the new-type ACF applications of FCOF assembly","authors":"W. Jong, S. Peng","doi":"10.1109/IMPACT.2009.5382301","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382301","url":null,"abstract":"Due to the environmental protection issues and regulations, a lot of electronic material suppliers try to search for the replacement materials which include the lead-free solder joints and the anisotropic conductive films (ACFs). ACF is widely used in high quality, excellent signal interconnection and fine pitch products. Nevertheless, during the fast flow and curing process of the electronic material, the risk of voiding may be increased. This study focuses on the characteristics and phenomena of a new-type ACF on the outer lead bonding (OLB) for flip chip on flex substrate (FCOF) assembly. Firstly, the thermal response and curing capability of the new-type ACF is investigated by the experiment. And the numerical simulation is used by computer aided engineering (CAE) that shows the heating effect of components on the bonding process. Both the simulated and experimental results can obtain the similar thermal behaviors. For the reliability assessment of the new-type ACF, the experiment procedures are adjusted three parameters of temperature, pressure and time under the bonding process. It can be easily discovered that the delaminations or cracks is caused by a lower compliance behavior of the interfaces between bumps on the polyimide (PI) substrate and indium tin oxides (ITOs) on the glass substrate. In order to evaluate the adhesive strength of ACF through the thermal loading, the strength of FCOF assembly is measured by a 90-degree peel test and is verified by the CAE simulation. In this study, the minimum peel strength of the new-type ACF has to be greater than 400 g/cm in order to satisfy the specification. Then, a stripped meshed model is simulated to understand the fracture growth between each interface under a constant speed of 8mm/sec. It can be found that the initial creak starts from the ACF-glass substrate interface and then propagates to the ITO. Finally, the swelling phenomenon of the new-type ACF is investigated. It shows that the swelling will not affect the structure of components and the reliability assessment is good.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":" 23","pages":"31-34"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91413918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382117
R. Ahmad, O. Sidek, S. Mohd
CRC (Cyclic Redundanncy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. The Verilog code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.
为了满足Zigbee等简单、低功耗、低成本的无线通信需求，在FPGA(现场可编程门阵列)上开发了CRC(循环冗余校验)块。Zigbee主要在2.4 GHz频段运行，这使得该技术易于应用并在全球范围内可用。本文简要介绍了基于Zigbee标准的数字发射机中的CRC分组。CRC是最受欢迎的编码方法，因为它对常见的突发错误提供了非常有效的保护，并且易于实现。该研究的目的是通过Xilinx ISE 8.2i使用Verilog代码条目来使设计方法多样化。Verilog代码用于描述CRC块行为，然后在Spartan3E XC3S500E FPGA上进行模拟，合成并成功实现。本文还给出了仿真和测量结果来验证CRC块的功能。CRC块的数据速率为250kbps。
{"title":"Development of CRC block onn FPGA for Zigbee standard","authors":"R. Ahmad, O. Sidek, S. Mohd","doi":"10.1109/IMPACT.2009.5382117","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382117","url":null,"abstract":"CRC (Cyclic Redundanncy Check) block was developed on FPGA (Field Programmable Gate Array) in order to meet the needs for simple, low-power and low-cost wireless communication such as Zigbee. Zigbee operates primarily in the 2.4 GHz band, which makes the technology easily applicable and worldwide available. This paper gives a short overview of CRC block in the digital transmitter based on Zigbee Standard. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. The purpose of the research is to diversify the design methods by using the Verilog code entry through Xilinx ISE 8.2i. The Verilog code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Spartan3E XC3S500E FPGA. Here, the simulation and measurement results are also presented to verify the functionality of the CRC block. The data rate of CRC block is 250 kbps.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"4 1","pages":"282-285"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88277639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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