Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382152
Y. Chan
Thanks for paying your attention on International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2009), and I cordially welcome your participation of the conference.
感谢您关注国际微系统、封装、组装与电路技术会议(IMPACT 2009)，我诚挚地欢迎您的参与。
{"title":"Welcome message from Yi-Jen Chan, conference general chair","authors":"Y. Chan","doi":"10.1109/IMPACT.2009.5382152","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382152","url":null,"abstract":"Thanks for paying your attention on International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2009), and I cordially welcome your participation of the conference.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"69 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75371110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382314
Yu-Chung Chen, Hung-Kun Lee
With the best tolerance and thermal stability among the commercially available embeddable resistor products, thin film resistors having copper foil as carrier have been expected to be one of the most potential candidates for meeting the future HDI development trend of PCB manufacturing process. However, before the potential can be realized, the problem of too small sheet resistivity - 250Ω/□ max limited by the native low resistivity of alloy resistive materials to cover the major usage range 10000 Ω/□ needs to be solved beforehand. In this study, a new composite thin film material comprising both the dispersed palladium metal conductor phase made from metal-organic deposition (MOD) of palladium acetate precursor, and the continuous semiconductor phase made of copper oxide got from 3 different processes - SILAR (Successive Ionic Layer Absorption and Reaction), MOD of copper acetate precursor and direct oxidation of copper foil has been developed and verified successfully with performance of broad sheet resistivity coverage from 1000 to 10000 Ω/□ and low temperature coefficient of resistance TCR ≪ ±200 ppm/°C. Due to different conductive mechanisms of the two different phase materials, the electric properties of the newly developed thin film resistive material can be easily adjusted. Increasing the metal conductor phase content - Pd with nature of low resistivity and positive TCR will make the resistance smaller and shift TCR positively and vice versa. In addition, for the copper oxide semiconductor phase materials with nature of high resistivity and negative TCR, cupric oxide CuO is superior to cuprous oxide Cu2O for its better compatibility with existing alkaline etching process.
{"title":"A new embeddable copper oxide based thin film resistor material","authors":"Yu-Chung Chen, Hung-Kun Lee","doi":"10.1109/IMPACT.2009.5382314","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382314","url":null,"abstract":"With the best tolerance and thermal stability among the commercially available embeddable resistor products, thin film resistors having copper foil as carrier have been expected to be one of the most potential candidates for meeting the future HDI development trend of PCB manufacturing process. However, before the potential can be realized, the problem of too small sheet resistivity - 250Ω/□ max limited by the native low resistivity of alloy resistive materials to cover the major usage range 10000 Ω/□ needs to be solved beforehand. In this study, a new composite thin film material comprising both the dispersed palladium metal conductor phase made from metal-organic deposition (MOD) of palladium acetate precursor, and the continuous semiconductor phase made of copper oxide got from 3 different processes - SILAR (Successive Ionic Layer Absorption and Reaction), MOD of copper acetate precursor and direct oxidation of copper foil has been developed and verified successfully with performance of broad sheet resistivity coverage from 1000 to 10000 Ω/□ and low temperature coefficient of resistance TCR ≪ ±200 ppm/°C. Due to different conductive mechanisms of the two different phase materials, the electric properties of the newly developed thin film resistive material can be easily adjusted. Increasing the metal conductor phase content - Pd with nature of low resistivity and positive TCR will make the resistance smaller and shift TCR positively and vice versa. In addition, for the copper oxide semiconductor phase materials with nature of high resistivity and negative TCR, cupric oxide CuO is superior to cuprous oxide Cu2O for its better compatibility with existing alkaline etching process.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"274 1","pages":"81-84"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73279073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382210
S. Chung, E. Kuo, M. Tseng
Copper pillars have been adopted and implemented in high volume manufacturing environment as early as 2006 as a replacement for high lead bumps. It is not only lead-free, but also offers the added advantage of higher stand-off, finer pitch capability and better electromigration resistance compared to tin-lead solder bumps. Owing to its significant superior thermal and electrical properties, higher stand-off, simpler UBM structure, and lower overall cost, it is not surprising that copper pillar bump has become and will continue to be a key interconnect technology in future semiconductor packages. As the full implementation of RoHS in 2010 approaches, various chemicals have been tested for this application by IDMs and OSATs. In order to simplify the chemical management in plant and shorten learning period, most of the efforts have been made on using RDL copper plating chemistry for Cu pillar applications.
{"title":"Bump shape control on high speed copper pillar plating process in lead-free wafer level packaging","authors":"S. Chung, E. Kuo, M. Tseng","doi":"10.1109/IMPACT.2009.5382210","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382210","url":null,"abstract":"Copper pillars have been adopted and implemented in high volume manufacturing environment as early as 2006 as a replacement for high lead bumps. It is not only lead-free, but also offers the added advantage of higher stand-off, finer pitch capability and better electromigration resistance compared to tin-lead solder bumps. Owing to its significant superior thermal and electrical properties, higher stand-off, simpler UBM structure, and lower overall cost, it is not surprising that copper pillar bump has become and will continue to be a key interconnect technology in future semiconductor packages. As the full implementation of RoHS in 2010 approaches, various chemicals have been tested for this application by IDMs and OSATs. In order to simplify the chemical management in plant and shorten learning period, most of the efforts have been made on using RDL copper plating chemistry for Cu pillar applications.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"16 1","pages":"432-435"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81659664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382219
A. Wu
Thank you for participating in IMPACT Conference 2009 and International 3D IC Conference. Due to the trend of 3D IC technology and development are discussed popularly in the world; SIPO especially holds this joint conference with IMPACT to introduce more about 3D IC technology in this conference.
{"title":"Welcome message from An-Yeu Wu, conference co-chair","authors":"A. Wu","doi":"10.1109/IMPACT.2009.5382219","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382219","url":null,"abstract":"Thank you for participating in IMPACT Conference 2009 and International 3D IC Conference. Due to the trend of 3D IC technology and development are discussed popularly in the world; SIPO especially holds this joint conference with IMPACT to introduce more about 3D IC technology in this conference.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"43 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85081714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382153
You-Chun Liang, Chih Chen
In this study, the temperature map distribution in the Sn3.0Ag0.5Cu solder bump with Cu column under current stressing is directly examined using infrared microscopy. It is the radiance changes between the different materials of the surface that cause the unreasonable temperature map distribution. By coating a thin layer of black optical paint which is in order to eliminate the radiance changes, we got the corrected temperature map distribution. Under a current stress of 1.15 × 104 A/cm2 at 100 °, the hot-spot temperature is 132.2°C which surpasses the average Cu column temperature of 129.7°C and the average solder bump temperature of 127.4¼. It is interesting that there are two modes of temperature distribution in the Cu column and in the solder bump, respectively.
本研究利用红外显微镜直接研究了电流应力作用下Sn3.0Ag0.5Cu带Cu柱钎料凸点的温度分布图。表面不同材质间的亮度变化是造成温度分布不合理的主要原因。为了消除辐射变化，我们在表面涂上一层薄薄的黑色光学涂料，得到了校正后的温度分布图。在电流应力为1.15 × 104 a /cm2，温度为100℃时，热点温度为132.2℃，超过了铜柱平均温度129.7℃和凸点平均温度127.4¼。有趣的是，在铜柱和凸点中分别存在两种温度分布模式。
{"title":"Direct measurement of hot-spot temperature in flip-chip solder joints with Cu columns under current stressing using infrared microscopy","authors":"You-Chun Liang, Chih Chen","doi":"10.1109/IMPACT.2009.5382153","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382153","url":null,"abstract":"In this study, the temperature map distribution in the Sn3.0Ag0.5Cu solder bump with Cu column under current stressing is directly examined using infrared microscopy. It is the radiance changes between the different materials of the surface that cause the unreasonable temperature map distribution. By coating a thin layer of black optical paint which is in order to eliminate the radiance changes, we got the corrected temperature map distribution. Under a current stress of 1.15 × 104 A/cm2 at 100 °, the hot-spot temperature is 132.2°C which surpasses the average Cu column temperature of 129.7°C and the average solder bump temperature of 127.4¼. It is interesting that there are two modes of temperature distribution in the Cu column and in the solder bump, respectively.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"13 1","pages":"158-161"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88903822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382211
Naokazu Murata, K. Tamakawa, K. Suzuki, H. Miura
Both the static and fatigue strengths of electroplated copper thin films were measured under uni-axial stress. The mechanical properties such as the yield stress, fracture elongation and Young's modulus of each film were quite different from those of bulk copper depending on their micro structure. The fracture surfaces were observed by SEM after the fatigue test. It was found that there were two fracture modes under the fatigue test. One was a typical ductile fracture, and another was brittle one even under the fatigue load higher than its yield stress. Since the initial micro texture was found to change significantly even after the annealing at temperatures lower than 300°C, the effect of the thermal history of them after electroplating on both their micro texture and fatigue strength was investigated quantitatively. In addition to the mechanical properties, the electrical properties of the films varied significantly depending on their micro texture. The resistivity of the films was much higher than that of bulk material, and the increase ratio varied from a few to a hundred depending on the conditions of electroplating. This increase can be also attributed to the variation of their micro texture. The fracture mode of the films under electromigration tests also varied from the local fusion cutting caused by the localized Joule heating to the conventional electromigration caused by the diffusion of copper atoms. This change can be explained by the characterization of grain boundaries of the films. When the grain boundaries were rather porous, copper atoms could not cross the adjoining grains. Since the resistivity of the porous grain boundaries is very high, fusion cutting may occur due to the highly localized Joule heating. This fusion cutting occurs unexpectedly without clear increase of the resistance of interconnections.
{"title":"Effect of micro-texture of electroplated copper thin-films on their mechanical and electrical reliability","authors":"Naokazu Murata, K. Tamakawa, K. Suzuki, H. Miura","doi":"10.1109/IMPACT.2009.5382211","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382211","url":null,"abstract":"Both the static and fatigue strengths of electroplated copper thin films were measured under uni-axial stress. The mechanical properties such as the yield stress, fracture elongation and Young's modulus of each film were quite different from those of bulk copper depending on their micro structure. The fracture surfaces were observed by SEM after the fatigue test. It was found that there were two fracture modes under the fatigue test. One was a typical ductile fracture, and another was brittle one even under the fatigue load higher than its yield stress. Since the initial micro texture was found to change significantly even after the annealing at temperatures lower than 300°C, the effect of the thermal history of them after electroplating on both their micro texture and fatigue strength was investigated quantitatively. In addition to the mechanical properties, the electrical properties of the films varied significantly depending on their micro texture. The resistivity of the films was much higher than that of bulk material, and the increase ratio varied from a few to a hundred depending on the conditions of electroplating. This increase can be also attributed to the variation of their micro texture. The fracture mode of the films under electromigration tests also varied from the local fusion cutting caused by the localized Joule heating to the conventional electromigration caused by the diffusion of copper atoms. This change can be explained by the characterization of grain boundaries of the films. When the grain boundaries were rather porous, copper atoms could not cross the adjoining grains. Since the resistivity of the porous grain boundaries is very high, fusion cutting may occur due to the highly localized Joule heating. This fusion cutting occurs unexpectedly without clear increase of the resistance of interconnections.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"26 46","pages":"436-439"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91418398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382264
K. W. Dennis, S. L. Yee, Leung Martin Bayes
Microelectronic wire bonding is a widely used and cost effective manufacturing process used to electrically connect integrated circuits (IC) with printed circuit boards (PCBs) or other substrates. The first bond is formed on the chip side and the second bond at the circuit board side. The choice of wire bondable surface finishes used on the circuit board can have a great impact on the reliability of the device. Electroless nickel electroless palladium immersion gold (ENEPIG) is one of the available wirebondable finishes and has been applied in these applications for some time. Although the rate of adoption of ENEPIG has been limited, it is attracting more interest due to increased gold prices, as a replacement for electrolytic nickel gold. This paper will present experimental data that demonstrates the capability of ENEPIG as a versatile surface finish providing reliable gold wire bonding performance. It also confirms that ENEPIG is a viable alternative to electrolytic nickel/gold.
{"title":"Effect of electroless palladium immersion gold deposit properties on gold wire bonding","authors":"K. W. Dennis, S. L. Yee, Leung Martin Bayes","doi":"10.1109/IMPACT.2009.5382264","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382264","url":null,"abstract":"Microelectronic wire bonding is a widely used and cost effective manufacturing process used to electrically connect integrated circuits (IC) with printed circuit boards (PCBs) or other substrates. The first bond is formed on the chip side and the second bond at the circuit board side. The choice of wire bondable surface finishes used on the circuit board can have a great impact on the reliability of the device. Electroless nickel electroless palladium immersion gold (ENEPIG) is one of the available wirebondable finishes and has been applied in these applications for some time. Although the rate of adoption of ENEPIG has been limited, it is attracting more interest due to increased gold prices, as a replacement for electrolytic nickel gold. This paper will present experimental data that demonstrates the capability of ENEPIG as a versatile surface finish providing reliable gold wire bonding performance. It also confirms that ENEPIG is a viable alternative to electrolytic nickel/gold.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"11 1","pages":"629-632"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91395717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382218
T. Wang, Hsuan-Yu Chen, Chang-Chi Lee, Y. Lai
HFCBGA is a thermally enhanced FCBGA with its heat spreader extending heat conduction area by connecting itself to the rear side of the silicon die. A thermal interface material plays an important role as a heat conduction path. The thermal performance should be checked not only at time zero, several types of reliability tests have to be examined to cover the field condition faced by end user. Temperature cycling test, highly-accelerated temperature and humidity stress test and multiple reflows are chosen for investigating thermal resistance of junction to case of a selected thermal gel.
{"title":"High-power-used thermal gel degradation Evaluation on board-level HFCBGA subjected to reliability tests","authors":"T. Wang, Hsuan-Yu Chen, Chang-Chi Lee, Y. Lai","doi":"10.1109/IMPACT.2009.5382218","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382218","url":null,"abstract":"HFCBGA is a thermally enhanced FCBGA with its heat spreader extending heat conduction area by connecting itself to the rear side of the silicon die. A thermal interface material plays an important role as a heat conduction path. The thermal performance should be checked not only at time zero, several types of reliability tests have to be examined to cover the field condition faced by end user. Temperature cycling test, highly-accelerated temperature and humidity stress test and multiple reflows are chosen for investigating thermal resistance of junction to case of a selected thermal gel.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"62 1","pages":"465-468"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78548311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382275
Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee
In this paper, we are interested in the Halogen-free (HF) impact on the reliability performance of portable electronic devices. Due to the trend of environment protection, the Halogen-free materials of solder paste, molding compounds, PCB and etc. have been widely discussed. When the material changes happen, the transition of failure modes in the board level can be expected, and the challenges are how to identify the influences of various factors. The strategies of improving HF materials are how to decrease the coefficient of thermal expansion (CTE) and increase the glass transition temperature (Tg) to avoid the warpage issue in the lead-free assembly process. However, these strategies will cause higher stiffness in the integral structure of the board level. According to the preliminary study, the high elastic modulus of materials is the main factor which attributes to the brittle fracture mode in the high strain-rate test; therefore, our research will investigate the impact of Halogen-free materials on the performance through the high strain-rate bend test. In this study, various factors, i.e., package sizes, solder ball materials, HF PCB stiffness and its outer-later structure, are taken into different combinations to valuation the performance. The experiment is divided into three parts. Each part will only have one variation. In the first part, the variation is the package size. The solder ball material (SAC105) remains unchanged. The result shows that the smaller package has better performance than the larger one at the same strain. In the second part, HF PCB stiffness is the variation. The result shows that the HF PCB of higher flexure modulus has worse performance than HF PCB of lower flexure modulus at the same strain. The fracture position transfers from the intermetallic compound (IMC) crack of the component side to the IMC crack of the board side and PCB pad delamination with increase the strain range. In the last part, some package suppliers migrate their sphere alloys from higher Ag alloys (SAC405 or SAC305) to alloys with lower Ag contents. There are numerous perceived benefits to this transformation in terms of intrinsic characteristic and performance. In this paper, we will choose several low Ag alloys to compensate HF PCB stiffness to resist the brittle fracture. We find one of the phenomena is that the performance will be better at a high strain rate test if the solder has applicable yield strength and higher elongation properties
{"title":"The impact investigation of CSP IC packaging on Halogen-free board level performance","authors":"Chi-Ko Yu, G. Chang, T. Shao, C. Chen, J. Lee","doi":"10.1109/IMPACT.2009.5382275","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382275","url":null,"abstract":"In this paper, we are interested in the Halogen-free (HF) impact on the reliability performance of portable electronic devices. Due to the trend of environment protection, the Halogen-free materials of solder paste, molding compounds, PCB and etc. have been widely discussed. When the material changes happen, the transition of failure modes in the board level can be expected, and the challenges are how to identify the influences of various factors. The strategies of improving HF materials are how to decrease the coefficient of thermal expansion (CTE) and increase the glass transition temperature (Tg) to avoid the warpage issue in the lead-free assembly process. However, these strategies will cause higher stiffness in the integral structure of the board level. According to the preliminary study, the high elastic modulus of materials is the main factor which attributes to the brittle fracture mode in the high strain-rate test; therefore, our research will investigate the impact of Halogen-free materials on the performance through the high strain-rate bend test. In this study, various factors, i.e., package sizes, solder ball materials, HF PCB stiffness and its outer-later structure, are taken into different combinations to valuation the performance. The experiment is divided into three parts. Each part will only have one variation. In the first part, the variation is the package size. The solder ball material (SAC105) remains unchanged. The result shows that the smaller package has better performance than the larger one at the same strain. In the second part, HF PCB stiffness is the variation. The result shows that the HF PCB of higher flexure modulus has worse performance than HF PCB of lower flexure modulus at the same strain. The fracture position transfers from the intermetallic compound (IMC) crack of the component side to the IMC crack of the board side and PCB pad delamination with increase the strain range. In the last part, some package suppliers migrate their sphere alloys from higher Ag alloys (SAC405 or SAC305) to alloys with lower Ag contents. There are numerous perceived benefits to this transformation in terms of intrinsic characteristic and performance. In this paper, we will choose several low Ag alloys to compensate HF PCB stiffness to resist the brittle fracture. We find one of the phenomena is that the performance will be better at a high strain rate test if the solder has applicable yield strength and higher elongation properties","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"25 1","pages":"666-669"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82502999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382130
A. Huang, Kuo Liang Su, P. Liang, J. Lin
A majority of OEMs have announced their plans to use non-halogenated circuit boards in 2008, and this decision has helped to accelerate the development schedule of halogen-free substrate cores.
{"title":"The development trend of halogen-free substrate cores","authors":"A. Huang, Kuo Liang Su, P. Liang, J. Lin","doi":"10.1109/IMPACT.2009.5382130","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382130","url":null,"abstract":"A majority of OEMs have announced their plans to use non-halogenated circuit boards in 2008, and this decision has helped to accelerate the development schedule of halogen-free substrate cores.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"44 1","pages":"244-246"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74993118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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