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2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference最新文献

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Nanotechnology for lead-free PWB final finishes with the Organic Metal 纳米技术无铅压水板最终饰面与有机金属
B. Wessling, J. Kenny
For the first time, a thin layer of only a few nano-meters has been deposited onto copper pads of printed circuit boards which provides effective protection against oxidation and preserves its solderability. The Nano layer has a thickness of nominally only 50 nm, and contains the Organic Metal (conductive polymer) and a small amount of silver. With ≪ 90% (by volume), the Organic Metal is the major component of the deposited layer, Ag is present equivalent to a thickness of 4 nm. This Organic Metal - Ag complex final finish outperforms any established surface finishes.
首次在印刷电路板的铜衬垫上沉积了一层只有几纳米的薄层,可以有效地防止氧化并保持其可焊性。纳米层的厚度名义上只有50纳米,包含有机金属(导电聚合物)和少量银。有机金属是沉积层的主要成分,其厚度相当于4纳米,占比达90%(按体积计)。这种有机金属-银复合物的最终处理优于任何既定的表面处理。
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引用次数: 0
Optical analysis and measurements of high-power COP LED packages 大功率COP LED封装的光学分析与测量
C. Y. Tang, C. Chen, M. Tsai
The purpose of this study is to investigate the optical behaviors and thus maximize luminous efficiency (focusing on light extraction efficiency here) of high-power chip-on-plate (COP) LED packages with the low-cost feature. First of all, to validate the luminous flux and candela distribution measurements and TracePro (one of commercial optical software) simulation, a Lumiled K1 LED package (one of commercially-available packages) is analyzed numerically and experimentally and compared with given data sheet. After the validation, both measurements and TracePro are applied to studying the candela distribution and light extraction efficiency of the COP LED packages. Furthermore, parametric studies of lens cavity height-radius ratio (h/r) and cup angle of COP LED packages using TracePro are implemented to find out the key factors to the light extraction efficiency. The results show that the candela distribution of COP LED packages from TracePro simulation is consistent with that from experiments. In optical parametric study, the effect of lens cavity height-radius ratio (h/r) of the COP LED packages on light extraction is found to be negligible, except for h/r=0. Moreover, with given lens cavity, the effect of air gap between silicone encapsulant and lens on light extraction is apparent by a way that air gap decreases with increasing light extraction. Also, it is found that the cup angle below 60° does not apparently affect light extraction, but beyond 60°, light extraction increases with the cup angle.
本研究的目的是研究具有低成本特性的高功率片上芯片(COP) LED封装的光学行为,从而最大限度地提高发光效率(这里主要关注光提取效率)。首先,为了验证光通量和坎德拉分布测量和TracePro(商用光学软件之一)模拟,对Lumiled K1 LED封装(商用封装之一)进行了数值和实验分析,并与给定数据表进行了比较。验证后,应用测量和TracePro研究了COP LED封装的坎德拉分布和光提取效率。此外,利用TracePro对COP LED封装的透镜腔高半径比(h/r)和杯角进行了参数化研究,找出影响光提取效率的关键因素。结果表明,TracePro模拟的COP LED封装的坎德拉分布与实验结果一致。在光学参数研究中,除了h/r=0外,COP LED封装的透镜腔高半径比(h/r)对光提取的影响可以忽略不计。此外,在给定透镜腔的情况下,硅酮密封剂与透镜之间的气隙对出光的影响是明显的,气隙随着出光量的增加而减小。在60°以下的杯角对光提取没有明显影响,而在60°以上,光提取随杯角的增大而增大。
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引用次数: 1
Thermal design strategy of server and storage products for 1U and 2U system 1U和2U系统服务器和存储产品的散热设计策略
B. Chang, C. Hsiao, Ping-Chi Hung, C. T. Wang
There are four topics have been discussed in this paper via numerical simulation which include on board placement, stand-off, redundancy design and outlet condition. The simulation is performed for 1U with 200W and 2U system with 700W, respectively. This paper also provides the some solutions for each topic and reveals the thermal phenomena in these two systems. The proper placement can reduce the loading of thermal design, and it will make the design easier. The effect of stand-off is important in 1U system and will limited to the thermal performance of CPU cooler. For redundancy design, the flow field may be complex due to re-flow. The outlet condition will also affect the thermal performance, the other possible solutions have been mentioned in this paper.
本文通过数值模拟的方法讨论了舰载布置、隔离、冗余设计和出口条件四个方面的问题。对1U和2U系统分别进行了200W和700W的仿真。本文还针对每个问题给出了一些解决方案,并揭示了这两个系统中的热现象。适当的放置可以减少热设计的负荷,使设计更容易。在1U系统中,隔离的影响是重要的,它将限制CPU冷却器的热性能。对于冗余设计,由于再流动,流场可能会很复杂。出口条件也会影响热工性能,文中还提出了其他可能的解决方案。
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引用次数: 0
Transmission electron microscopy characterization of the porous structure induced by high current density in the flip-chip solder joints 高电流密度诱导倒装焊点多孔结构的透射电镜表征
M. Tsai, Yen-liang Lin, C. Kao
There are several identified failure mechanisms such as void formation and propagation, the local melting mechanism and the underbump metallization (UBM) dissolution in flip chip solder joints. In our previous studies Ni(V) UBM consumption was also found to cause the failure. The flip chip solder joint used in this study was with Al/Ni(V)/Cu UBM on the chip side and an Au/Ni surface finish on the substrate side. The solder was used by eutectic PbSn. The aging temperature was constant 150°C and a 0.32A current stressing was applied to make a nominal current density of 5 x 103A/cm2. Owing to the combined effects of current crowding and local Joule heating, the microstructure of the Ni(V) UBM near the entrance of the electrons into the joints was transformed to a porous structure after 550 hours. Afterwards the porous structure propagated all over the UBM to make the solder joints fail since the porous structure was non-conductive. The microstructure was firstly observed by field emission scanning electron microscopy (FE-SEM) and subsequently focused ion beam (FIB) was used to fabricate specimens for transmission electron microscopy (TEM) observation. The porous structure was composed of many voids near the interface of Ni(V)/(Cu,Ni)6Sn5 and a void-free area near the interface of Ni(V)/Al. Energy dispersion X-ray (EDX) analysis on TEM was performed for composition analyses. In the porous structure almost no Ni signal was detected except for the region near the interface of Ni(V)/Al. Pb-rich dark patches observed in the porous structure revealed that a severe diffusion behavior was occurred during electromigration. Selected area diffraction patterns (SADPs) were derived to identify phases. The results showed that the matrix of the porous structure was amorphous. Fine grains of Cu6Sn5 and V2Sn3 were randomly distributed in the matrix of the porous structure and a thin layer of Ni3Sn4 was located at the interface of Ni(V)/Al.
倒装焊点的失效机制包括空洞的形成和扩展、局部熔化机制和凹凸下金属化(UBM)的溶解。在我们之前的研究中,Ni(V) UBM的消耗也发现了导致失败的原因。本研究中使用的倒装芯片焊点在芯片一侧使用Al/Ni(V)/Cu UBM,在衬底一侧使用Au/Ni表面抛光。焊料采用共晶PbSn。老化温度为150°C,施加0.32A电流应力,使标称电流密度为5 × 103A/cm2。由于电流拥挤和局部焦耳加热的共同作用,550小时后,电子进入接头入口附近的Ni(V) UBM微观结构转变为多孔结构。由于多孔结构不导电,导致焊点失效。首先用场发射扫描电镜(FE-SEM)观察其微观结构,然后用聚焦离子束(FIB)制作样品进行透射电镜(TEM)观察。在Ni(V)/(Cu,Ni)6Sn5界面附近有许多孔洞,在Ni(V)/Al界面附近有一个无孔洞区。在TEM上进行了能量色散x射线(EDX)分析。在多孔结构中,除Ni(V)/Al界面附近外,几乎没有检测到Ni信号。在多孔结构中观察到富铅暗斑,表明电迁移过程中发生了严重的扩散行为。导出了选择区域衍射图(SADPs)来识别相。结果表明,多孔结构的基体为非晶态。细小的Cu6Sn5和V2Sn3晶粒随机分布在多孔结构的基体中,Ni(V)/Al界面处有一层薄薄的Ni3Sn4。
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引用次数: 1
An in-depth study on the fabrication of 1055–1064 nm multi-quantum-well and super-lattice laser diodes 对1055 ~ 1064 nm多量子阱和超晶格激光二极管的制备进行了深入研究
A. Wu, H. Tseng, C. Wan, Yan-Kuin Su, Chenming Hu, S. Tsau
The InGaAs/GaAs multi-quantum-well as well as the AlGaAs/GaAs and the GaAsP/GaAs super-lattice laser diodes were successfully fabricated by low-pressure MOCVD system, and a number of novel structures were explored in this systematic investigation. The strain-relief effect and the composition of cladding layers were analyzed in detail. Via a series of growth experiments, we concluded that better lasing efficiency and the minimum threshold current could be obtained from the sample made up of the AlGaAs/GaAs structure combined with the 60% Aluminum content of the AlGaAs cladding layer.
利用低压MOCVD系统成功制备了InGaAs/GaAs多量子阱、AlGaAs/GaAs和GaAsP/GaAs超晶格激光二极管,并探索了一些新的结构。详细分析了熔覆层的应变缓解效果和熔覆层的组成。通过一系列的生长实验,我们得出AlGaAs/GaAs结构与60%铝含量的AlGaAs包层结合可以获得更好的激光效率和最小阈值电流。
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引用次数: 0
Performance tests on a novel vapor chamber 新型蒸汽室的性能测试
K. Hsieh, S. Wong
The performance of a novel vapor chamber is tested in this study. In this vapor chamber, parallel grooves are made on the inner surface of the top plate, with inter-groove openings, to replace the conventional porous wick. To the inner surface of the bottom plate is sintered a layer of porous wick as the evaporator. The peaks of the groove walls directly contact with the wick so that the grooves function as vapor path, condenser and structural supporters simultaneously. The corrugated groove walls provide not only an enlarged condensation area, but also a direct shortcut for a portion of the liquid condensed on the groove surface to be absorbed back to the wick. Thus, smaller liquid-flow resistance and hence high anti-dryout capability are achieved. The test module includes a copper plate-fin heat sink in combination with a top fan. In this study, the evaporator wick was made of sintered multi-layer copper screens and the footprint of the vapor chamber was 10 cm × 8.9 cm. With a 2.1 cm × 2.1 cm or a 1.1 cm × 1.1 cm heating area, the vapor chamber resistances were measured for heat load increasing from 80 W to beyond 300 W. Good performances with low vapor chamber resistance and large heat load limit were obtained under different orientations.
本文对一种新型蒸汽室进行了性能测试。在该蒸汽室中,在顶板的内表面上制作平行凹槽,凹槽间有开口,以取代传统的多孔灯芯。在底板的内表面烧结一层多孔灯芯作为蒸发器。槽壁的峰值与芯直接接触,使槽同时起蒸汽通道、冷凝器和结构支撑的作用。波纹槽壁不仅提供了一个扩大的冷凝面积,而且还提供了一个直接的捷径,使在槽表面冷凝的一部分液体被吸收回芯。因此,液体流动阻力较小,因此具有较高的抗干性。测试模块包括一个铜板翅散热器和一个顶部风扇。在本研究中,蒸发器芯芯由烧结多层铜网制成,蒸汽室占地面积为10 cm × 8.9 cm。在2.1 cm × 2.1 cm或1.1 cm × 1.1 cm的加热区域,测量了热负荷从80w增加到300w以上时的蒸汽室阻力。在不同取向下均获得了较低的气室阻力和较大的热负荷极限。
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引用次数: 62
Flux study for ultra fine pitch flip chip packages 超细间距倒装芯片封装的通量研究
W. Lee, G. Lin, D. Chang, J. Jiang, Carl Chen
Flux used in 25um ultra fine pitch flip chip attachment process has been found to play an important role in the bump joint and performance. It is commonly used in cleaning the surfaces of solder balls and the surfaces to be soldered to ensure a good wetting of the solder bumps on the substrate pads. Here we use Cu pillar bump with solder cap and substrate pad surface finish is plating tin, and furthermore the standard reflow process was used to perform the evaluation. Due to higher bonding temperature requirement, a Pbfree compatible no clean flux is needed. This kind of flux is formulated to work well with small bump diameter and pitch which have low residual after reflow profile and low weight loss during the whole process. Of course they are achieving compatibility with the underfill. For this new generation flip chip products, how to select a suitable flux is the most challenge. This paper gives a detailed description of the challenges encountered during assembly, such as the flux selection process, flux height study. The characteristics of flux can be determined by using TGA, wet-ability test, and thermal resistance. For ultra fine pitch flip chip application, no clean and low residue flux is the basic demand. Besides, jetting type flux will be the best choice because the flux height is hard to control and the flux amount might not be enough to provide the solder joint ability. Finally, we conclude that the most rigid bonding method, and parameter for fine pitch Cu pillar bump flip chip package.
在25um超细间距倒装芯片的贴装工艺中,焊剂的使用对凹凸接头的性能起着重要的作用。它通常用于清洗焊锡球表面和待焊表面,以确保衬底上的焊锡凸起得到良好润湿。本文采用铜柱凸焊带焊锡帽,衬底垫表面抛光镀锡,并采用标准回流工艺进行评价。由于焊接温度要求较高,因此需要无铅兼容的无清洁焊剂。该助焊剂具有小凸点直径和节距,回流后残余量小,全程重量损失小的特点。当然,他们正在实现与下填料的兼容性。对于这种新一代倒装芯片产品,如何选择合适的磁通是最大的挑战。本文详细介绍了在装配过程中遇到的难题,如焊剂的选择过程、焊剂高度的研究等。通过热重热分析、润湿性测试和热阻测试可以确定助焊剂的特性。对于超细间距倒装芯片应用,无清洁和低残留焊剂是基本要求。此外,喷射型助焊剂的助焊剂高度难以控制,且助焊剂量可能不足以提供焊点的性能,因此是最佳选择。最后,我们得出了最严格的键合方法和参数,用于小间距铜柱碰撞倒装芯片封装。
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引用次数: 9
Influence of intermetallic compound on the stress distribution and fatigue life of halogen-free printed circuit board assembly 金属间化合物对无卤印刷电路板组件应力分布和疲劳寿命的影响
Tao-Chih Chang, H. Chang, C. Zhan, Jing-Yao Chang, Jiali Fan, J. Chou
A complete halogen-free test vehicle was achieved by assembling five ball grid array (BGA) components with daisy-chain on an 8-layer high density interconnection (HDI) printed circuit board with a low-halide Sn1.0Ag0.5Cu (SAC105) Pb-free solder pastes for reducing the formation of Ag3Sn. Afterward a board-level cyclic bending test was enforced on the as-reflowed assemblies according to the JESD22-B113 standard to evaluate the reliability of HF PCBA under a low-level load condition. The Weibull analyses showed that the characteristic lives of the assemblies were 99,098 and 130,290 cycles on Cu pad and electroless Ni pad, respectively, and the failure mode was the fracture of Cu trace within the micro-via induced by the crack of resin coated copper (RCC) layer. At the interfaces of solder joints, the intermetallic compound (IMC) formed on both Cu and electroless Ni was (Cu, Ni)6Sn5 with various Ni contents of 3.9 and 20.1 at%, respectively, and different thicknesses of 5.6 and 1.1 um. The simulation results pointed out that the factors of composition and thickness of IMC significantly influenced the stress distribution and characteristic life of the HF test vehicle. The stiff (Cu, Ni)6Sn5 constrained the deformation of solder joint interconnection, but increased the stress concentrated on soldering pad and RCC layer. Although the (Cu, Ni)6Sn5 on the electroless Ni was stiffer than that on the Cu pad, the thicker (Cu, Ni)6Sn5 instead increased the stress on the Cu pad due to size effect, and results in a lower characteristic life.
采用低卤化物Sn1.0Ag0.5Cu (SAC105)无铅焊膏减少Ag3Sn的形成,在8层高密度互连(HDI)印刷电路板上以菊花链方式组装5个球栅阵列(BGA)元件,实现了完整的无卤化测试车。随后,根据JESD22-B113标准对回流组件进行板级循环弯曲试验,以评估高频PCBA在低负荷条件下的可靠性。Weibull分析结果表明,在Cu焊盘和化学镀镍焊盘上,组件的特征寿命分别为99,098次和130,290次,失效模式为树脂包覆铜(RCC)层裂纹引起的微孔内Cu微量断裂。在焊点界面处,Cu和化学镀Ni均形成金属间化合物(IMC)为(Cu, Ni)6Sn5, Ni含量分别为3.9和20.1 At %,厚度分别为5.6和1.1 um。仿真结果表明,内嵌件的组成和厚度等因素对高频试验车的应力分布和特性寿命有显著影响。刚性的(Cu, Ni)6Sn5抑制了焊点互连的变形,但增加了集中在焊垫和RCC层上的应力。虽然化学镀Ni表面的(Cu, Ni)6Sn5比Cu焊盘表面的(Cu, Ni)6Sn5更硬,但更厚的(Cu, Ni)6Sn5由于尺寸效应反而增加了Cu焊盘上的应力,导致特性寿命降低。
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引用次数: 1
Mechanism of pore formation in solid 固体孔隙形成机制
P. Wei, S. Hsiao
The shapes of a growing or decaying bubble entrapped by a solidification front are predicted in this work. The bubble results from supersaturation of a dissolved gas in the liquid ahead of the solidification front. Pore formation and its shape in solid are one of the most serious issues affecting properties, microstructure, and stresses in materials. In this study, the bubble and pore shapes entrapped in solid are realistically predicted by utilizing perturbation solutions of Young-Laplace equation governing the tiny bubble shape in the literature. The growth and entrapment of a microbubble in solid can be predicted and found to agree with experimental data.
在此工作中,预测了被凝固锋包围的生长或衰减气泡的形状。气泡是由于凝固前液体中溶解气体的过饱和造成的。孔隙的形成及其在固体中的形状是影响材料性能、微观结构和应力的最严重问题之一。在本研究中,利用文献中控制微小气泡形状的Young-Laplace方程的摄动解,真实地预测了固体中的气泡和孔隙形状。可以预测微泡在固体中的生长和包裹,并与实验数据相吻合。
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引用次数: 0
Reliability of 20µm pitch NCF type COF package with compliant-bump 20µm间距NCF型COF封装的可靠性
Yu-Min Lin, Su-Tsai Lu, Tai-Hong Chen
In this study, three kinds of NCF adhesives named as NCF I, NCF II and NCF III, were applied to COF package with compliant-bump. Firstly, to investigate bonding temperature effects, the curing rate of the NCFs and strength of interconnection under different bonding temperatures (150 °C ∼ 230 °C) were evaluated using differential scanning calorimeter (DSC) test and a 90 degree peeling test, respectively. Then, the electrical performances of NCF joints bonded at different bonding temperatures were monitored by measuring daisy chain and insulated resistance. After that, the reliability tests of 85 °C / 85 % RH thermal humidity storage test (THST), and 55 °C ∼ 125 °C thermal cycling test (TCT) were performed. Finally, the cross-section images of failure samples from SEM were observed to find the failure mode.
本研究将三种NCF胶粘剂NCF I、NCF II和NCF III应用于凹凸凹凸的COF包装。首先,为了研究键合温度的影响,分别使用差示扫描量热计(DSC)测试和90度剥离测试评估了不同键合温度(150°C ~ 230°C)下nfc的固化速率和互连强度。然后,通过测量雏菊链和绝缘电阻,监测不同连接温度下NCF接头的电性能。之后,进行85°C / 85% RH热湿储存试验(THST)和55°C ~ 125°C热循环试验(TCT)的可靠性试验。最后,通过扫描电镜观察破坏试样的截面图,找出破坏模式。
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引用次数: 5
期刊
2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference
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