In recent years, high power white LED devices (LEDs) have been developed and widely used in display, display backlight module and general lightings. UV LED pumped RGB phosphors is one of the methods to generate white light. It shows some advantages, such as: excellent color rendering index (CRI), tolerant to LED variation, etc. However, the high energy of UV or near UV based LED lighting source leads to encapsulated transparent epoxy resin chain scission and forms some chromatic sites. The discolored epoxy materials decreases the light output and accumulates heat inside to speed up material degradation. Moreover, LED display and LED lighting devices also suffer UV irradiation from sunlight in the outdoor applications. In order to avoid the UV-degraded problem of LED encapsulating materials, we developed UV resistant material technology. Our developing strategies included evaluating UV stabilizer, synthesis of silicone modified epoxy or curing agent to enhance the bonding energy of encapsulating material.
{"title":"Development of UV stable LED encapsulants","authors":"Chih-Hau Lin, H. Li, Shu-Chen Huang, Chia-Wen Hsu, Kai-Chi Chen, Wen-Bin Chen","doi":"10.1109/IMPACT.2009.5382245","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382245","url":null,"abstract":"In recent years, high power white LED devices (LEDs) have been developed and widely used in display, display backlight module and general lightings. UV LED pumped RGB phosphors is one of the methods to generate white light. It shows some advantages, such as: excellent color rendering index (CRI), tolerant to LED variation, etc. However, the high energy of UV or near UV based LED lighting source leads to encapsulated transparent epoxy resin chain scission and forms some chromatic sites. The discolored epoxy materials decreases the light output and accumulates heat inside to speed up material degradation. Moreover, LED display and LED lighting devices also suffer UV irradiation from sunlight in the outdoor applications. In order to avoid the UV-degraded problem of LED encapsulating materials, we developed UV resistant material technology. Our developing strategies included evaluating UV stabilizer, synthesis of silicone modified epoxy or curing agent to enhance the bonding energy of encapsulating material.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"310 1","pages":"565-567"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79953174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382255
S. Tisdale, R. Pfahl, H. Fu
The electronics industry is aggressively pursuing the removal of potentially toxic compounds from their products, including the halogenated flame retardants (HFRs) that were once widely used in electronics housings and cases and are still used extensively in printed circuit boards. Several leading electronics companies have publicly stated their intent to remove brominated and/or halogenated flame retardants from some or all of their products. The International Electronics Manufacturing Initiative (iNEMI), an industry-led consortium, is working with a number of its OEM and supply chain members to assess the feasibility of a broad conversion to HFR-free PCB materials. While IPC and JEDEC are developing halogen-free standard specifications and numerous companies have compliant materials, significant questions remain regarding overall readiness to make a transition to these materials. This paper will discuss results & conclusions from the completed iNEMI HFR-free PCB Materials Project, as well as outline current projects, which include the HFR-free High-Reliability PCB project, the HFR-free Signal Integrity
{"title":"iNEMI HFR-free leadership program","authors":"S. Tisdale, R. Pfahl, H. Fu","doi":"10.1109/IMPACT.2009.5382255","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382255","url":null,"abstract":"The electronics industry is aggressively pursuing the removal of potentially toxic compounds from their products, including the halogenated flame retardants (HFRs) that were once widely used in electronics housings and cases and are still used extensively in printed circuit boards. Several leading electronics companies have publicly stated their intent to remove brominated and/or halogenated flame retardants from some or all of their products. The International Electronics Manufacturing Initiative (iNEMI), an industry-led consortium, is working with a number of its OEM and supply chain members to assess the feasibility of a broad conversion to HFR-free PCB materials. While IPC and JEDEC are developing halogen-free standard specifications and numerous companies have compliant materials, significant questions remain regarding overall readiness to make a transition to these materials. This paper will discuss results & conclusions from the completed iNEMI HFR-free PCB Materials Project, as well as outline current projects, which include the HFR-free High-Reliability PCB project, the HFR-free Signal Integrity","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"107 1","pages":"594-597"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86058439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382141
Kai-Shing Yang, Yu-Lieh Wu, I. Chen, Chi-Chuan Wang
A detailed numerical simulation of the performance of thermal module having “thermal via” is made in this study. The results indicate the temperature distributions from the numerical simulation are significantly affected by spreading resistance. The filled thermal via can considerably improve the performance of thermal module. For further explanation of the significant drop of junction and thermal resistance at sub-mount with thermal via, the detailed thermal resistances distribution in the thermal module are further examined. It is found that the significant drop of thermal resistance is mainly from package level with the help of thermal via filled in submount. However, the effect of PCB on the thermal resistance is quite different for the simulated geometries, a “maximum” ratio of thermal resistance of PCB had occurred. The thermal resistance of heat sink remains the same for all simulated case. With further adding the thermal via, the effect of heat sink on the overall resistance will become more and more pronounced.
{"title":"An investigation of thermal spreading device with thermal via in high power LEDs","authors":"Kai-Shing Yang, Yu-Lieh Wu, I. Chen, Chi-Chuan Wang","doi":"10.1109/IMPACT.2009.5382141","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382141","url":null,"abstract":"A detailed numerical simulation of the performance of thermal module having “thermal via” is made in this study. The results indicate the temperature distributions from the numerical simulation are significantly affected by spreading resistance. The filled thermal via can considerably improve the performance of thermal module. For further explanation of the significant drop of junction and thermal resistance at sub-mount with thermal via, the detailed thermal resistances distribution in the thermal module are further examined. It is found that the significant drop of thermal resistance is mainly from package level with the help of thermal via filled in submount. However, the effect of PCB on the thermal resistance is quite different for the simulated geometries, a “maximum” ratio of thermal resistance of PCB had occurred. The thermal resistance of heat sink remains the same for all simulated case. With further adding the thermal via, the effect of heat sink on the overall resistance will become more and more pronounced.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"2 1","pages":"195-198"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81249548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382310
Y. W. Wang, C. Kao
It is of importance for the reliability of lead-free and lead-bearing solder joints to have better understanding and control of the solder/metallization interactions during soldering. In the reactions between solders and Cu substrate, the formation of micro voids within the Cu3Sn layer had been report by many research groups. Because the Cu3Sn growth had been linked to the formation of micro voids, which in turn increased the potential for a brittle interfacial fracture, thinner Cu3Sn layers might translate into better solder joint strength. Main thrust of retarding Cu3Sn is the minor alloy additions. One of the more note-worthy alloying elements is Ni. In order to investigate the effects of Ni on Cu3Sn, the solders used for this study are 10Sn90Pb and 5Sn95Pb doped with 0, 0.06, and 0.2 wt.% Ni. These solders were prepared from 99.999 % purity elements. For the investigation of microstructure evolution of the solder joint, Cu plates with 99.99 % purity were used. Reaction conditions included one reflow at 350 °C for 2 min and solid-state aging at 160 °C for up to 2000 h. In reflow study, Cu3Sn was the only reaction product observed for all the different solders used. In solid state aging study, both Cu3Sn and Cu6Sn5 formed in 10Sn90Pb-xNi solders, but only Cu3Sn formed in 5Sn95Pb-xNi solders. These phenomena can clearly know by using the ternary SnPbCu phase diagrams. The objective of this study is to investigate the influences of Ni on Cu3Sn growth and micro voids in different kinds of solders. Emphasis is placed on a systematic comparison study on the effects of Ni addition. The effect of Ni on the Cu3Sn and micro voids were discussed in detail based on the experimental results. The results of this study can be summarized as below: (1) Minor Ni addition to high-lead solder can't retard Cu3Sn thickness. However, the Ni addition to lead-free solder can retard Cu3Sn. (2) The Sn flux from the solder towards the Cu substrate would be reduced by thick Cu6Sn5. The shrinkage of Cu3Sn attribute to the decrease of Sn flux. (3) Ni retards the Cu3Sn growth through Cu6Sn5. (4) Micro voids formed after aging at 160 oC for more than 500 h in 10Sn90Pb-xNi and 5Sn95Pb-xNi solders.
{"title":"Effects of Ni addition to high-lead solders on the growth of Cu3Sn and micro voids","authors":"Y. W. Wang, C. Kao","doi":"10.1109/IMPACT.2009.5382310","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382310","url":null,"abstract":"It is of importance for the reliability of lead-free and lead-bearing solder joints to have better understanding and control of the solder/metallization interactions during soldering. In the reactions between solders and Cu substrate, the formation of micro voids within the Cu3Sn layer had been report by many research groups. Because the Cu3Sn growth had been linked to the formation of micro voids, which in turn increased the potential for a brittle interfacial fracture, thinner Cu3Sn layers might translate into better solder joint strength. Main thrust of retarding Cu3Sn is the minor alloy additions. One of the more note-worthy alloying elements is Ni. In order to investigate the effects of Ni on Cu3Sn, the solders used for this study are 10Sn90Pb and 5Sn95Pb doped with 0, 0.06, and 0.2 wt.% Ni. These solders were prepared from 99.999 % purity elements. For the investigation of microstructure evolution of the solder joint, Cu plates with 99.99 % purity were used. Reaction conditions included one reflow at 350 °C for 2 min and solid-state aging at 160 °C for up to 2000 h. In reflow study, Cu3Sn was the only reaction product observed for all the different solders used. In solid state aging study, both Cu3Sn and Cu6Sn5 formed in 10Sn90Pb-xNi solders, but only Cu3Sn formed in 5Sn95Pb-xNi solders. These phenomena can clearly know by using the ternary SnPbCu phase diagrams. The objective of this study is to investigate the influences of Ni on Cu3Sn growth and micro voids in different kinds of solders. Emphasis is placed on a systematic comparison study on the effects of Ni addition. The effect of Ni on the Cu3Sn and micro voids were discussed in detail based on the experimental results. The results of this study can be summarized as below: (1) Minor Ni addition to high-lead solder can't retard Cu3Sn thickness. However, the Ni addition to lead-free solder can retard Cu3Sn. (2) The Sn flux from the solder towards the Cu substrate would be reduced by thick Cu6Sn5. The shrinkage of Cu3Sn attribute to the decrease of Sn flux. (3) Ni retards the Cu3Sn growth through Cu6Sn5. (4) Micro voids formed after aging at 160 oC for more than 500 h in 10Sn90Pb-xNi and 5Sn95Pb-xNi solders.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"10 1","pages":"64-67"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87780828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382121
Tzu Yu Chen, S. Liang, Chih Chen
This study investigates the effect of passivation opening design on electromigration reliability issue in flip-chip solder joints by using statistical analysis. Eutectic SnAg solder joints were used in this study with two different filling condition of polyimide (PI), ie with or without contact opening. The bump height is 50 µm. The four point probe method was used to monitor the bump resistance of a specific solder joint with downward election flow, under 0.8 A at 155°C. The failure criteria are defined as the resistances rose to 1.2 times and 2 times of their initial values. In addition, three-dimensional finite element analysis (3D-FEA) was employed to show the distribution of current density, and the different failure modes were also discussed. The solder joints without PI performed longer failure time from the statistical analysis results. In other words, the set without PI shows better reliability than that with PI.
{"title":"Effect of passivation opening design on electromigration reliability issue in flip-chip solder joints","authors":"Tzu Yu Chen, S. Liang, Chih Chen","doi":"10.1109/IMPACT.2009.5382121","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382121","url":null,"abstract":"This study investigates the effect of passivation opening design on electromigration reliability issue in flip-chip solder joints by using statistical analysis. Eutectic SnAg solder joints were used in this study with two different filling condition of polyimide (PI), ie with or without contact opening. The bump height is 50 µm. The four point probe method was used to monitor the bump resistance of a specific solder joint with downward election flow, under 0.8 A at 155°C. The failure criteria are defined as the resistances rose to 1.2 times and 2 times of their initial values. In addition, three-dimensional finite element analysis (3D-FEA) was employed to show the distribution of current density, and the different failure modes were also discussed. The solder joints without PI performed longer failure time from the statistical analysis results. In other words, the set without PI shows better reliability than that with PI.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"45 1","pages":"267-270"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88081478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382178
Ching-Chang Chen, Chien-in Li, Tai-Feng Wu
In this study, a new piezomotor is presented, and an optical anti-shake image system using this piezomotor is also developed. Comparing with other linear piezomotors, this motor is simpler, compacter, and more powerful. The dimension of the motor is 16mm(L)×8mm(W)×1.5mm(H), and the resonate frequency is 220kHz. Moreover, the push force at operating voltage 10Vpp is 15g, and the power consumption is 0.23W. Because of the long travel range:±2mm and high maximum velocity:26mm/s, it could satisfy the compensative displacement of the CMOS sensor caused by the hand tremor in a anti-shake image system. In this paper, a dynamic behavior of the piezomotor is investigated by COMSOL software, and the control algorithm in the optical anti-shake image system, including tremor sensing, motor position sensing, is also described.
{"title":"An optical anti-shake system with a tremor sensing module and compact linear piezomotors","authors":"Ching-Chang Chen, Chien-in Li, Tai-Feng Wu","doi":"10.1109/IMPACT.2009.5382178","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382178","url":null,"abstract":"In this study, a new piezomotor is presented, and an optical anti-shake image system using this piezomotor is also developed. Comparing with other linear piezomotors, this motor is simpler, compacter, and more powerful. The dimension of the motor is 16mm(L)×8mm(W)×1.5mm(H), and the resonate frequency is 220kHz. Moreover, the push force at operating voltage 10Vpp is 15g, and the power consumption is 0.23W. Because of the long travel range:±2mm and high maximum velocity:26mm/s, it could satisfy the compensative displacement of the CMOS sensor caused by the hand tremor in a anti-shake image system. In this paper, a dynamic behavior of the piezomotor is investigated by COMSOL software, and the control algorithm in the optical anti-shake image system, including tremor sensing, motor position sensing, is also described.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"8 1","pages":"308-311"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85693433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382233
P.S. Huang, M. Tsai
For determining die strength, there are a couple of tests available in the literature, such as three-point and four-point bending, ball breaker, ball-on-the-ring, ring-on-the-ring, and recently proposed ball-on-elastic- pad (BoEP) and ball-on-the-hole (BoH) tests. It's well known that the test data reduction with theoretical formulations is more convenient and useful than that with numerical simulation results. However, those theoretical formulations have to be validated either by numerical simulation or experiments, before their applications. The objective of this study is to reevaluate and thus improve the existing BoEP and BoH tests for die strength using Hertzian contact theory, plate theories and finite element method (FEM). In this paper, the FEM analysis with “contact element” successfully has been verified with Hertzian contact theory and further proved that Hertzian contact theory can be employed to estimate the contact area for calculating die strength in both methods. The results indicate that the consistency between the theoretical formulation and FEM simulation for both tests exist only at the relatively large radius of ball and high applied loading, because the feasibility of the theoretical formulations requires large contact radius(> 0.06 mm) or area. For the BoEP test, the elastic moduli of elastic pad and ball have no obvious effect on the difference of maximum die stress between theoretical and FEM results. The theoretical solutions associated with contact radius determined by Hertzian contact theory are successfully proved for improving BoEP and BoH tests for die strength determination, and for better accuracy of die strength the ball with radius ranging from 2 mm to 4 mm is suggested.
{"title":"Improved ball-on-elastic-pad and ball-on-hole tests for silicon die strength","authors":"P.S. Huang, M. Tsai","doi":"10.1109/IMPACT.2009.5382233","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382233","url":null,"abstract":"For determining die strength, there are a couple of tests available in the literature, such as three-point and four-point bending, ball breaker, ball-on-the-ring, ring-on-the-ring, and recently proposed ball-on-elastic- pad (BoEP) and ball-on-the-hole (BoH) tests. It's well known that the test data reduction with theoretical formulations is more convenient and useful than that with numerical simulation results. However, those theoretical formulations have to be validated either by numerical simulation or experiments, before their applications. The objective of this study is to reevaluate and thus improve the existing BoEP and BoH tests for die strength using Hertzian contact theory, plate theories and finite element method (FEM). In this paper, the FEM analysis with “contact element” successfully has been verified with Hertzian contact theory and further proved that Hertzian contact theory can be employed to estimate the contact area for calculating die strength in both methods. The results indicate that the consistency between the theoretical formulation and FEM simulation for both tests exist only at the relatively large radius of ball and high applied loading, because the feasibility of the theoretical formulations requires large contact radius(> 0.06 mm) or area. For the BoEP test, the elastic moduli of elastic pad and ball have no obvious effect on the difference of maximum die stress between theoretical and FEM results. The theoretical solutions associated with contact radius determined by Hertzian contact theory are successfully proved for improving BoEP and BoH tests for die strength determination, and for better accuracy of die strength the ball with radius ranging from 2 mm to 4 mm is suggested.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"319 2","pages":"518-521"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91429775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382295
N. Miyazaki, H. Ogino, Y. Kitamura, T. Mabuchi, T. Nawata
We developed an analysis system for simulating birefringence of an annealed ingot of CaF2 single crystal caused by the residual stress after annealing process. In the residual stress calculation, we can select either the elastic thermal stress analysis using a stress-free temperature or more exact stress analysis considering creep deformation. When we use the residual stress calculated from the creep deformation analysis of a CaF2 ingot, we can obtain reasonable results in comparison with the experimental results.
{"title":"Birefringence simulations of annealed ingot of calcium fluoride single crystal by considering creep behavior of ingot during annealing process","authors":"N. Miyazaki, H. Ogino, Y. Kitamura, T. Mabuchi, T. Nawata","doi":"10.1109/IMPACT.2009.5382295","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382295","url":null,"abstract":"We developed an analysis system for simulating birefringence of an annealed ingot of CaF2 single crystal caused by the residual stress after annealing process. In the residual stress calculation, we can select either the elastic thermal stress analysis using a stress-free temperature or more exact stress analysis considering creep deformation. When we use the residual stress calculated from the creep deformation analysis of a CaF2 ingot, we can obtain reasonable results in comparison with the experimental results.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"65 1","pages":"2-5"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78601926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382198
Y.S. Chen, Yu-chun Huang
Shock test is one of the significant reliability tests for electronics products. JEDEC test standards regulate only the first controlled-pulse by defining a variety of conditions such as the pulse peak acceleration, pulse duration and velocity change during the drop impact processes. In reality, a practical test showed that not only was one pulse produced, but also a series of two or more aftershocks are encountered. Hence, it is doubtful on whether and how the aftershocks influence results of components' reliability. The purpose of this study is to investigate the aftershocks' effect on the test products and to predict the time interval of its occurrence as well as the relating acceleration responses. The investigations include experimental, theoretical and finite element analysis methods. The severity of aftershock and the time instant it happens were first tested and modeled precisely. This model was then used as input both for theoretical and numerical calculations to solve system's response. Good consistencies among results of all three methods are observed, it is then possible to use the theoretical and FEA methods for the shock design of electronic systems prior to the manufacturing of the prototypes. Most importantly, the corresponding outcomes have taken the aftershock into consideration instead of only the primary pulse. It is believed to be more accurate in the reliability analysis of electronic products.
{"title":"Aftershock effects on the reliability of electronic components under shock test","authors":"Y.S. Chen, Yu-chun Huang","doi":"10.1109/IMPACT.2009.5382198","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382198","url":null,"abstract":"Shock test is one of the significant reliability tests for electronics products. JEDEC test standards regulate only the first controlled-pulse by defining a variety of conditions such as the pulse peak acceleration, pulse duration and velocity change during the drop impact processes. In reality, a practical test showed that not only was one pulse produced, but also a series of two or more aftershocks are encountered. Hence, it is doubtful on whether and how the aftershocks influence results of components' reliability. The purpose of this study is to investigate the aftershocks' effect on the test products and to predict the time interval of its occurrence as well as the relating acceleration responses. The investigations include experimental, theoretical and finite element analysis methods. The severity of aftershock and the time instant it happens were first tested and modeled precisely. This model was then used as input both for theoretical and numerical calculations to solve system's response. Good consistencies among results of all three methods are observed, it is then possible to use the theoretical and FEA methods for the shock design of electronic systems prior to the manufacturing of the prototypes. Most importantly, the corresponding outcomes have taken the aftershock into consideration instead of only the primary pulse. It is believed to be more accurate in the reliability analysis of electronic products.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"142 1","pages":"385-388"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77794869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-01DOI: 10.1109/IMPACT.2009.5382266
Y. Ho, J. Luo, Keven Hsu, Arthur Chen
In this study, lead free (Sn-4Ag-0.5Cu (SAC)) and lead (62Sn-36Pb-2Ag (SP)) solder joint on various surface finished of ball grid array (BGA) pad, such as Immersion Tin (ImSn), Organic solderability preservatives (OSPs), Ni-P/Pd/Au (ENEPIG), and Ni-P/Au (ENIG) was investigated by its interface morphology and its physical properties. To evaluate the mechanical and physical properties of BGA pad with lead and lead free solder joint, it was tested by bonding strength measuring, shear force test and interfacial microstructure. The IMC (Inter metallic compound) of SAC and SP solder with these finishes were also studied by using Focused Ion Beam (FIB) microscope to observe the crystal grain, morphology and size. It was found that the IMC crystal lattice is dependent on solder material and the solder joint reliability is dependent on both the solder material as well as the surface finish. Moreover, the shear test results show that the shear strength of solder joints could not be significantly influenced by the thickness and morphology of the interfacial IMC.
{"title":"Reliability test and IMC investigation of lead and lead free solder joints on different surface finish processes","authors":"Y. Ho, J. Luo, Keven Hsu, Arthur Chen","doi":"10.1109/IMPACT.2009.5382266","DOIUrl":"https://doi.org/10.1109/IMPACT.2009.5382266","url":null,"abstract":"In this study, lead free (Sn-4Ag-0.5Cu (SAC)) and lead (62Sn-36Pb-2Ag (SP)) solder joint on various surface finished of ball grid array (BGA) pad, such as Immersion Tin (ImSn), Organic solderability preservatives (OSPs), Ni-P/Pd/Au (ENEPIG), and Ni-P/Au (ENIG) was investigated by its interface morphology and its physical properties. To evaluate the mechanical and physical properties of BGA pad with lead and lead free solder joint, it was tested by bonding strength measuring, shear force test and interfacial microstructure. The IMC (Inter metallic compound) of SAC and SP solder with these finishes were also studied by using Focused Ion Beam (FIB) microscope to observe the crystal grain, morphology and size. It was found that the IMC crystal lattice is dependent on solder material and the solder joint reliability is dependent on both the solder material as well as the surface finish. Moreover, the shear test results show that the shear strength of solder joints could not be significantly influenced by the thickness and morphology of the interfacial IMC.","PeriodicalId":6410,"journal":{"name":"2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference","volume":"79 1","pages":"637-640"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83784238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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