Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001591
X. Tao, K. Reis, B. Haby, M. Karnett, N. White, C. Watts, M. Delgado, K. Gardner, K. R. Harris
Electrical microprobe and Passive Voltage Contrast (PVC) techniques were used to investigate incompletely filled contacts and vias on our 0.20 um FEOL (Front-End-Of-Line) characterization and process qualification vehicles. The failure mechanism of unfilled tungsten plugs was attributed to electrochemical corrosion during the post-metal etch solvent strip. This tungsten plug corrosion led to high contact and via failure rates, failure of the yield impact prediction model, electromigration test failure, and 3% to 6% yield loss at final test. Several detailed experiments were performed towards identifying and resolving this corrosion plug failure mechanism. It was found that modification of the Tungsten CMP buff significantly reduced the failure rate and led to increased probe yield with improved manufacturability.
电微探头和无源电压对比(PVC)技术用于研究我们的0.20 um FEOL(前端线)表征和工艺鉴定车辆上未完全填充的触点和过孔。未填充钨塞的失效机理是金属后蚀刻溶剂带过程中的电化学腐蚀。这种钨塞腐蚀导致高接触和通孔失败率、屈服影响预测模型失效、电迁移测试失败，以及最终测试中3%至6%的屈服损失。为了确定和解决腐蚀塞的失效机制，进行了一些详细的实验。结果表明，对钨基CMP buff进行改性可以显著降低探针的故障率，提高探针的成品率，提高探针的可制造性。
{"title":"Failure rate and yield-limiting tungsten plug corrosion diagnosis using characterization test vehicles","authors":"X. Tao, K. Reis, B. Haby, M. Karnett, N. White, C. Watts, M. Delgado, K. Gardner, K. R. Harris","doi":"10.1109/ASMC.2002.1001591","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001591","url":null,"abstract":"Electrical microprobe and Passive Voltage Contrast (PVC) techniques were used to investigate incompletely filled contacts and vias on our 0.20 um FEOL (Front-End-Of-Line) characterization and process qualification vehicles. The failure mechanism of unfilled tungsten plugs was attributed to electrochemical corrosion during the post-metal etch solvent strip. This tungsten plug corrosion led to high contact and via failure rates, failure of the yield impact prediction model, electromigration test failure, and 3% to 6% yield loss at final test. Several detailed experiments were performed towards identifying and resolving this corrosion plug failure mechanism. It was found that modification of the Tungsten CMP buff significantly reduced the failure rate and led to increased probe yield with improved manufacturability.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81578239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001598
G. Nicolussi, E. Beck
Assembly & Packaging processes of semiconductor devices such as die attach, wire bonding, and molding can greatly benefit from Plasma Cleaning. The removal of surface contaminants prior to these process steps results in more reliable connections between the bonding surfaces. In this paper we present a new plasma process for die and chip carrier cleaning. Highly reactive radicals are generated in a hollow cathode discharge using different gas mixture; i.e. argon/hydrogen, argon/oxygen, and argon/ nitrogen. The radicals react with surface contaminants to form volatile compounds which subsequently degas from the substrate surface. The employment of a hollow cathode plasma source ensures a high degree of ionization and molecular fragmentation of the working gas. At the same time, the plasma potential was kept below 30 V. As a result, the cleaning process is purely chemical and not associated with surface erosion due to physical sputtering caused by energetic ions. Visual inspection, wire pull test, and contact angle measurements were used to confirm the cleaning efficiency.
{"title":"Plasma chemical cleaning of chip carrier in a downstream hollow cathode discharge","authors":"G. Nicolussi, E. Beck","doi":"10.1109/ASMC.2002.1001598","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001598","url":null,"abstract":"Assembly & Packaging processes of semiconductor devices such as die attach, wire bonding, and molding can greatly benefit from Plasma Cleaning. The removal of surface contaminants prior to these process steps results in more reliable connections between the bonding surfaces. In this paper we present a new plasma process for die and chip carrier cleaning. Highly reactive radicals are generated in a hollow cathode discharge using different gas mixture; i.e. argon/hydrogen, argon/oxygen, and argon/ nitrogen. The radicals react with surface contaminants to form volatile compounds which subsequently degas from the substrate surface. The employment of a hollow cathode plasma source ensures a high degree of ionization and molecular fragmentation of the working gas. At the same time, the plasma potential was kept below 30 V. As a result, the cleaning process is purely chemical and not associated with surface erosion due to physical sputtering caused by energetic ions. Visual inspection, wire pull test, and contact angle measurements were used to confirm the cleaning efficiency.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89481709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001611
Hung-Nan Chen, R. Dabbas
In this paper we demonstrate the use of an analytical queuing model and a simulation model for calculating the minimum staffing level in a semiconductor manufacturing environment. The analytical model analyzes the number of operators required to process wafers and perform operator-level equipment service and maintenance. Machine interference is modeled as an M/M/c queue with finite calling population. When compared to a simulation model, the analytical model yields close results in various factory loading and equipment maintenance plans. The analytical model is then implemented as an Intranet on line tool for staffing analysis in a Motorola factory. The implemented system allows fast and accurate analysis on different equipment groupings (assignments of equipment to bays), PM schedule, product mix, and operator loading assumptions.
{"title":"Modeling staffing requirements within a semiconductor manufacturing environment","authors":"Hung-Nan Chen, R. Dabbas","doi":"10.1109/ASMC.2002.1001611","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001611","url":null,"abstract":"In this paper we demonstrate the use of an analytical queuing model and a simulation model for calculating the minimum staffing level in a semiconductor manufacturing environment. The analytical model analyzes the number of operators required to process wafers and perform operator-level equipment service and maintenance. Machine interference is modeled as an M/M/c queue with finite calling population. When compared to a simulation model, the analytical model yields close results in various factory loading and equipment maintenance plans. The analytical model is then implemented as an Intranet on line tool for staffing analysis in a Motorola factory. The implemented system allows fast and accurate analysis on different equipment groupings (assignments of equipment to bays), PM schedule, product mix, and operator loading assumptions.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89484244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001623
Hong Lin, A. Busnaina, I. Suni
High aspect ratio submicron trench cleaning is of seriously concern in semiconductor manufacturing. Megasonic cleaning is known as one of the most effective techniques in blanket wafer cleaning. The authors have studied megasonic rinsing and cleaning processes for blanket wafers and provided both experimental and modeling results. Although megasonic cleaning is currently used in patterned wafer cleaning, the mechanism of the process is not well understood. In our previous research , simulation of pulsating flow passing a series of rectangular cavities was verified and showed excellent agreement with the numerical and experimental results of Perkins. Pulsating flow rinse shows a significant advantage in patterned wafer cleaning because the vortex oscillating mechanism enhances the mixing. In this paper, the removal of contaminants from high aspect-ratio submicron trenches using high frequency pulsating flow (megasonic rinse) is studied using physical modeling.
{"title":"Cleaning of high aspect ratio submicron trenches","authors":"Hong Lin, A. Busnaina, I. Suni","doi":"10.1109/ASMC.2002.1001623","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001623","url":null,"abstract":"High aspect ratio submicron trench cleaning is of seriously concern in semiconductor manufacturing. Megasonic cleaning is known as one of the most effective techniques in blanket wafer cleaning. The authors have studied megasonic rinsing and cleaning processes for blanket wafers and provided both experimental and modeling results. Although megasonic cleaning is currently used in patterned wafer cleaning, the mechanism of the process is not well understood. In our previous research , simulation of pulsating flow passing a series of rectangular cavities was verified and showed excellent agreement with the numerical and experimental results of Perkins. Pulsating flow rinse shows a significant advantage in patterned wafer cleaning because the vortex oscillating mechanism enhances the mixing. In this paper, the removal of contaminants from high aspect-ratio submicron trenches using high frequency pulsating flow (megasonic rinse) is studied using physical modeling.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89766133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001566
I. Grodnensky, S. Enayati, J. Manka, S. Mizutani, S. Slonaker
We present a new technique for accurate and fast evaluation of lithographic imaging performance at critical dimensions (CDs) of 100 nm and below. Its advantages over traditional methods that use either SEM or electrical CD metrologies are based on two key factors. First, it exploits a specially designed mark corresponding to a particular CD. Second, instead of mark dimensions the mark image irradiance is measured with a CCD TV camera. In combination, these provide an easy-to-implement and inexpensive technique for controlling exposure tool imaging performance. In actual application, best focus determination shows a repeatability (3/spl sigma/) of less than 5 nm.
{"title":"Controlling lithographic imaging performance at sub-100 nm CD with optical measurements","authors":"I. Grodnensky, S. Enayati, J. Manka, S. Mizutani, S. Slonaker","doi":"10.1109/ASMC.2002.1001566","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001566","url":null,"abstract":"We present a new technique for accurate and fast evaluation of lithographic imaging performance at critical dimensions (CDs) of 100 nm and below. Its advantages over traditional methods that use either SEM or electrical CD metrologies are based on two key factors. First, it exploits a specially designed mark corresponding to a particular CD. Second, instead of mark dimensions the mark image irradiance is measured with a CCD TV camera. In combination, these provide an easy-to-implement and inexpensive technique for controlling exposure tool imaging performance. In actual application, best focus determination shows a repeatability (3/spl sigma/) of less than 5 nm.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87957017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001622
B. Vermeire, K. Delbridge, V. Pandit, H. Parks, S. Raghavan, K. Ramkumar, S. Geha, J. Jeon
Hf and Zr contamination during immersion in process solutions is most likely to occur in neutral or caustic solutions. Both Hf and Zr contamination are introduced onto the wafer surface if they are present in an APM solution (which is caustic), but such contamination is easily removed using existing cleans. If contamination remains on a wafer, an effect on gate oxide integrity using ramped voltage testing is only observed at very high concentrations of Hf. Time dependent dielectric breakdown results are affected at lower levels of contamination. This is true particularly if the contamination is introduced using an APM solution. Wafer-to-wafer cross contamination can also occur in a thermal reactor during high temperature anneals of high-k dielectric layers.
{"title":"The effect of hafnium or zirconium contamination on MOS processes","authors":"B. Vermeire, K. Delbridge, V. Pandit, H. Parks, S. Raghavan, K. Ramkumar, S. Geha, J. Jeon","doi":"10.1109/ASMC.2002.1001622","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001622","url":null,"abstract":"Hf and Zr contamination during immersion in process solutions is most likely to occur in neutral or caustic solutions. Both Hf and Zr contamination are introduced onto the wafer surface if they are present in an APM solution (which is caustic), but such contamination is easily removed using existing cleans. If contamination remains on a wafer, an effect on gate oxide integrity using ramped voltage testing is only observed at very high concentrations of Hf. Time dependent dielectric breakdown results are affected at lower levels of contamination. This is true particularly if the contamination is introduced using an APM solution. Wafer-to-wafer cross contamination can also occur in a thermal reactor during high temperature anneals of high-k dielectric layers.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82467284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001603
B. Gurcan, T. Thibeault, Heather Maines, K. Swan, L. Moores
With the advent of shallow source/drains in advanced CMOS, PMOS transistors can become susceptible to source to well leakage. Products which use shallow trench isolation (STI) are susceptible to thin trench oxide which can lead to leaky transistors as the cobalt silicide gets formed around the edges of the active region, creating a current path when trench oxide is thin. PMOS transistors are more susceptible to this leakage current mechanism as the PMOS source drain implants are shallower than the NMOS. Implementation of feed forward of post CMP trench oxide thickness to trench recess etch time can compensate for incoming variation from STI CMP. This results in a more consistent field oxide thickness, and a more consistent field oxide to active area step height. This is accomplished by adjusting the trench recess HF time based on the incoming oxide thickness. P+ contact leakage on test lots decreased significantly as a result of the STI trench recess feed forward process between the TEST and CONTROL legs of the experiment.
{"title":"STI trench recess feed forward control for self-aligned contact processes to reduce PMOS contact leakage","authors":"B. Gurcan, T. Thibeault, Heather Maines, K. Swan, L. Moores","doi":"10.1109/ASMC.2002.1001603","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001603","url":null,"abstract":"With the advent of shallow source/drains in advanced CMOS, PMOS transistors can become susceptible to source to well leakage. Products which use shallow trench isolation (STI) are susceptible to thin trench oxide which can lead to leaky transistors as the cobalt silicide gets formed around the edges of the active region, creating a current path when trench oxide is thin. PMOS transistors are more susceptible to this leakage current mechanism as the PMOS source drain implants are shallower than the NMOS. Implementation of feed forward of post CMP trench oxide thickness to trench recess etch time can compensate for incoming variation from STI CMP. This results in a more consistent field oxide thickness, and a more consistent field oxide to active area step height. This is accomplished by adjusting the trench recess HF time based on the incoming oxide thickness. P+ contact leakage on test lots decreased significantly as a result of the STI trench recess feed forward process between the TEST and CONTROL legs of the experiment.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86560742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001592
B. Wu
The conventionally designed 300 mm IC fabricator in an automated environment has many drawbacks such as: high capital outlay and high cost of ownership, long fab construction time, low flexibility for multiproduct and multi-process operation, long process cycle time and high work in process. These drawbacks have an enormous impact on the economics of a 300 mm fab. This paper proposes a new fab architecture and operational philosophy to improve the economics of 300 mm/450 mm fabs. The new fab architecture and design will reduce capital outlay and fab construction time by 50%, increase equipment utilization by 100%, reduce COO by 30%, and reduce both process cycle time and work in process by at least 30%, and cut annual operating expense by 30%. Integral to this new approach is the cooperative alignment of IC makers and equipment suppliers throughout the equipment and fab life cycle. By closely working together, both will reap the economic rewards.
{"title":"Innovations for economical 300/450 mm IC fabricators","authors":"B. Wu","doi":"10.1109/ASMC.2002.1001592","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001592","url":null,"abstract":"The conventionally designed 300 mm IC fabricator in an automated environment has many drawbacks such as: high capital outlay and high cost of ownership, long fab construction time, low flexibility for multiproduct and multi-process operation, long process cycle time and high work in process. These drawbacks have an enormous impact on the economics of a 300 mm fab. This paper proposes a new fab architecture and operational philosophy to improve the economics of 300 mm/450 mm fabs. The new fab architecture and design will reduce capital outlay and fab construction time by 50%, increase equipment utilization by 100%, reduce COO by 30%, and reduce both process cycle time and work in process by at least 30%, and cut annual operating expense by 30%. Integral to this new approach is the cooperative alignment of IC makers and equipment suppliers throughout the equipment and fab life cycle. By closely working together, both will reap the economic rewards.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88291231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001624
Sheng‐Bai Zhu
A comprehensive study of airborne molecular contamination (AMC) in minienvironments is presented in this paper. The impact of AMC on semiconductor manufacturing processes is reviewed. Models that describe contamination mechanisms are developed. The technologies and performance of minienvironments in contamination control are discussed based on theoretical models and experimental data.
{"title":"Study of airborne molecular contamination in minienvironments","authors":"Sheng‐Bai Zhu","doi":"10.1109/ASMC.2002.1001624","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001624","url":null,"abstract":"A comprehensive study of airborne molecular contamination (AMC) in minienvironments is presented in this paper. The impact of AMC on semiconductor manufacturing processes is reviewed. Models that describe contamination mechanisms are developed. The technologies and performance of minienvironments in contamination control are discussed based on theoretical models and experimental data.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88117372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001634
B. Lin, C.S. Chen, W. Yeh, S. Peng
The device features increasingly smaller and complex circuitry in the process 0.15 /spl mu/m technology and beyond 0.15 /spl mu/m. The layers of interconnect are increase. year to year and the number of transistors are increased dramatically. It means Chemical Mechanical Polish (CMP) is important day to day. Slurry and polish pad are the key parameters in Chemical Mechanical Polish (CMP) due to small Lithograph window and vertical topography tolerance. Since there are many brand of slurry applicant widely in Oxide polishing, Tungsten polishing and Copper polishing. Hence, the behavior of surfactant in slurry is very important for us decide which surfactant and slurry is suit for us. One surfactant and two different types of slurry are evaluated in. this experiment. The planarity (dishing, step height remove...) is very good in this study. Defect is an important index for the technology beyond 0.15 /spl mu/m, the micro-scratch was studied in this experiment. Of course, we need evaluate the ability in mass production. The result is very satisfactory.
{"title":"Surfactant behavior and study in slurry","authors":"B. Lin, C.S. Chen, W. Yeh, S. Peng","doi":"10.1109/ASMC.2002.1001634","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001634","url":null,"abstract":"The device features increasingly smaller and complex circuitry in the process 0.15 /spl mu/m technology and beyond 0.15 /spl mu/m. The layers of interconnect are increase. year to year and the number of transistors are increased dramatically. It means Chemical Mechanical Polish (CMP) is important day to day. Slurry and polish pad are the key parameters in Chemical Mechanical Polish (CMP) due to small Lithograph window and vertical topography tolerance. Since there are many brand of slurry applicant widely in Oxide polishing, Tungsten polishing and Copper polishing. Hence, the behavior of surfactant in slurry is very important for us decide which surfactant and slurry is suit for us. One surfactant and two different types of slurry are evaluated in. this experiment. The planarity (dishing, step height remove...) is very good in this study. Defect is an important index for the technology beyond 0.15 /spl mu/m, the micro-scratch was studied in this experiment. Of course, we need evaluate the ability in mass production. The result is very satisfactory.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78477448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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