Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001582
C. Gould
High volume, cost effective, manufacturing of state of the art lithography processes requires in depth understanding of Process and Process-Tool interaction to achieve Advanced Process Control (APC). The APC systems being deployed at Infineon Technologies, Richmond has shown and is expected to continue demonstrating continuous improvement for the following primary metrics: /spl middot/ OL and CD Cpk /spl middot/ Rework Reduction /spl middot/ Reduction of MTTD /spl middot/ Lot Cycle Time improvement.
{"title":"Advanced Process Control: benefits for photolithography process control","authors":"C. Gould","doi":"10.1109/ASMC.2002.1001582","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001582","url":null,"abstract":"High volume, cost effective, manufacturing of state of the art lithography processes requires in depth understanding of Process and Process-Tool interaction to achieve Advanced Process Control (APC). The APC systems being deployed at Infineon Technologies, Richmond has shown and is expected to continue demonstrating continuous improvement for the following primary metrics: /spl middot/ OL and CD Cpk /spl middot/ Rework Reduction /spl middot/ Reduction of MTTD /spl middot/ Lot Cycle Time improvement.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76861998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001629
S. Miraglia, C. Blouin, G. Boldman, S. Judd, T. Richardson, D. Yao
At IBM in Essex Junction, Vermont, an enhanced ABC model is being used not only to assign costs to wafers, but in several new ways that have enabled analysis across multiple dimensions. The model is being used to aid cost reduction activities by providing wafer cost breakdown by process type (e.g., expose, deposition, etch, cleans, measurement), by element (e.g., depreciation, chemicals, staffing, occupancy), by level (e.g., poly gate, metal, via), and by equipment state (e.g., productive or idle). These new cost breakdowns allow a more complete understanding of the cost contribution of different factors and therefore enable proper focus with regard to cost reduction activities and productivity studies. For example, wafer costs broken down by masking layer show that critical levels (i.e., critical in terms of printing requirements) are the most expensive to manufacture. This approach changes classical activity-based-costing (ABC) from a financial tool to a managerial tool for assessing factory dynamics.
{"title":"ABC modeling: advanced features [semiconductor manufacturing]","authors":"S. Miraglia, C. Blouin, G. Boldman, S. Judd, T. Richardson, D. Yao","doi":"10.1109/ASMC.2002.1001629","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001629","url":null,"abstract":"At IBM in Essex Junction, Vermont, an enhanced ABC model is being used not only to assign costs to wafers, but in several new ways that have enabled analysis across multiple dimensions. The model is being used to aid cost reduction activities by providing wafer cost breakdown by process type (e.g., expose, deposition, etch, cleans, measurement), by element (e.g., depreciation, chemicals, staffing, occupancy), by level (e.g., poly gate, metal, via), and by equipment state (e.g., productive or idle). These new cost breakdowns allow a more complete understanding of the cost contribution of different factors and therefore enable proper focus with regard to cost reduction activities and productivity studies. For example, wafer costs broken down by masking layer show that critical levels (i.e., critical in terms of printing requirements) are the most expensive to manufacture. This approach changes classical activity-based-costing (ABC) from a financial tool to a managerial tool for assessing factory dynamics.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80043545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001583
M. Sarfaty, A. Shanmugasundram, A. Schwarm, J. Paik, Jimin Zhang, R. Pan, M. Seamons, H. Li, R. Hung, S. Parikh
Traditional semiconductor manufacturing relies on a fixed process-recipe combined with a classical statistical process control that is used to monitor the production process. Leading-edge manufacturing processes require higher levels of precision and accuracy, which necessitate the use of tighter process control. Advanced Process Control (APC) is becoming a critical component to improve performance, yield, throughput, and flexibility of the manufacturing process using run-to-run, wafer-to-wafer, within wafer and real-time process control. The complexity of device manufacturing process as well as the strong coupling effect of several input parameters on the final process outputs prohibit the use of a classical single variable feedback control method. Therefore, multivariate, model-based APC system is developed in conjunction with feed-forward and feedback mechanisms to automatically determine the optimal recipe for each wafer based on both incoming wafer and tool state properties. The APC system uses wafer metrology, process models and sophisticated control algorithms to provide dynamic fine-tuning of intermediate process targets that enhance final device targets. The design of the APC system enables scalable control solutions across a single chamber, a process tool, multi-tools, a process module and multi-process modules using similar building blocks, concepts and algorithms.
{"title":"Advance Process Control solutions for semiconductor manufacturing","authors":"M. Sarfaty, A. Shanmugasundram, A. Schwarm, J. Paik, Jimin Zhang, R. Pan, M. Seamons, H. Li, R. Hung, S. Parikh","doi":"10.1109/ASMC.2002.1001583","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001583","url":null,"abstract":"Traditional semiconductor manufacturing relies on a fixed process-recipe combined with a classical statistical process control that is used to monitor the production process. Leading-edge manufacturing processes require higher levels of precision and accuracy, which necessitate the use of tighter process control. Advanced Process Control (APC) is becoming a critical component to improve performance, yield, throughput, and flexibility of the manufacturing process using run-to-run, wafer-to-wafer, within wafer and real-time process control. The complexity of device manufacturing process as well as the strong coupling effect of several input parameters on the final process outputs prohibit the use of a classical single variable feedback control method. Therefore, multivariate, model-based APC system is developed in conjunction with feed-forward and feedback mechanisms to automatically determine the optimal recipe for each wafer based on both incoming wafer and tool state properties. The APC system uses wafer metrology, process models and sophisticated control algorithms to provide dynamic fine-tuning of intermediate process targets that enhance final device targets. The design of the APC system enables scalable control solutions across a single chamber, a process tool, multi-tools, a process module and multi-process modules using similar building blocks, concepts and algorithms.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90541016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001630
G. Klusewitz, J. M. C. Viegh
Semiconductor fabricators use immense amounts of water, a large portion of which is used to produce Ultra Pure Water (UPW) also referred to as DI (Deionized) water. Approximately 1500 gallons of city water are required to produce 1000 gallons of UPW. The cost for generating UPW is approximately $12 per 1000 gallons. Producing the UPW also involves UV lamps, filters, pumps, and recirculating systems that require energy to operate. Approximately 46 kWH can be saved for every 1000 gallons of UPW conserved. This paper describes the methodology and results of a cross-functional team to reduce UPW usage in the Fairchild Mountaintop six inch facility. The team comprised process technicians, process engineers, facility engineers, and equipment vendors. Reduction efforts included rinse sink, process, and supply modifications. The goal was to reduce the DI usage by 2 million gallons within one year. The annual savings as a result of this team's efforts are projected to approach 18 million gallons of DI water or about $214,000.
{"title":"Water usage reduction in a semiconductor fabricator","authors":"G. Klusewitz, J. M. C. Viegh","doi":"10.1109/ASMC.2002.1001630","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001630","url":null,"abstract":"Semiconductor fabricators use immense amounts of water, a large portion of which is used to produce Ultra Pure Water (UPW) also referred to as DI (Deionized) water. Approximately 1500 gallons of city water are required to produce 1000 gallons of UPW. The cost for generating UPW is approximately $12 per 1000 gallons. Producing the UPW also involves UV lamps, filters, pumps, and recirculating systems that require energy to operate. Approximately 46 kWH can be saved for every 1000 gallons of UPW conserved. This paper describes the methodology and results of a cross-functional team to reduce UPW usage in the Fairchild Mountaintop six inch facility. The team comprised process technicians, process engineers, facility engineers, and equipment vendors. Reduction efforts included rinse sink, process, and supply modifications. The goal was to reduce the DI usage by 2 million gallons within one year. The annual savings as a result of this team's efforts are projected to approach 18 million gallons of DI water or about $214,000.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91118679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001569
K. Saito, S. Arima
This paper proposes a new dynamic priority dispatching algorithm for the product-mix of work-in-progress (WIP) at a processing station with multiple machines. The algorithm is used to evaluate dispatching priority when each quantum starts. The priority is defined considering both the number of WIP and the decreasing rate of WIP in the incoming buffer. When the priority is high, a single sort of WIP is assigned to a machine for a given period, or quantum. This algorithm, named Pseudo Periodical Priority Dispatching (P3D), P3D was examined through Monte Carlo simulation. In a product-mix, a machine must be adjusted when the WIP is changed. The adjustment frequency and the degradation of the machine utilization due to the adjustment are discussed. The algorithm is able to achieve fair dispatching both at a bottlenecked processing step and a non-bottlenecked processing step.
{"title":"A simulation study on periodical priority dispatching of WIP for product-mix fabrication","authors":"K. Saito, S. Arima","doi":"10.1109/ASMC.2002.1001569","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001569","url":null,"abstract":"This paper proposes a new dynamic priority dispatching algorithm for the product-mix of work-in-progress (WIP) at a processing station with multiple machines. The algorithm is used to evaluate dispatching priority when each quantum starts. The priority is defined considering both the number of WIP and the decreasing rate of WIP in the incoming buffer. When the priority is high, a single sort of WIP is assigned to a machine for a given period, or quantum. This algorithm, named Pseudo Periodical Priority Dispatching (P3D), P3D was examined through Monte Carlo simulation. In a product-mix, a machine must be adjusted when the WIP is changed. The adjustment frequency and the degradation of the machine utilization due to the adjustment are discussed. The algorithm is able to achieve fair dispatching both at a bottlenecked processing step and a non-bottlenecked processing step.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87723984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001584
P. Jowett, V. Morozov
A project was launched to improve Shallow Trench Isolation (STI) etch depth control on magnetically enhanced reactive ion etch (MERIE) chambers. The aim was to reduce the wafer-to-wafer depth variation. The cause of the wafer-to-wafer depth variation was found to be due to a number of factors, including: (a) Multiple chamber/platform of film deposition tools, (b) Multiple Film Thickness Metrology tools, (c) Multiple etch chamber/platform tools and (d) Multiple STI Depth metrology equipment. To account for these variations, a feedback Run-to-Run control loop has been developed. The algorithm utilizes pre-etch film thickness and post-etch STI depth metrology data to output a new etch time for a particular chamber in order to re-center the process. The challenges that where overcome with the Run-to-Run (R2R) algorithm included: (1) Filtering incoming data from possible "flyers," (2) Accounting for uncertainties associated with different metrology tools and (3) Improving the robustness of the control algorithm. After implementation, in-silicon depth standard deviation was reduced to /spl sim/1/3 of its original value. SPC (statistical process control) parameters were also significantly improved.
{"title":"Shallow trench isolation run-to-run control project at Infineon Technologies Richmond","authors":"P. Jowett, V. Morozov","doi":"10.1109/ASMC.2002.1001584","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001584","url":null,"abstract":"A project was launched to improve Shallow Trench Isolation (STI) etch depth control on magnetically enhanced reactive ion etch (MERIE) chambers. The aim was to reduce the wafer-to-wafer depth variation. The cause of the wafer-to-wafer depth variation was found to be due to a number of factors, including: (a) Multiple chamber/platform of film deposition tools, (b) Multiple Film Thickness Metrology tools, (c) Multiple etch chamber/platform tools and (d) Multiple STI Depth metrology equipment. To account for these variations, a feedback Run-to-Run control loop has been developed. The algorithm utilizes pre-etch film thickness and post-etch STI depth metrology data to output a new etch time for a particular chamber in order to re-center the process. The challenges that where overcome with the Run-to-Run (R2R) algorithm included: (1) Filtering incoming data from possible \"flyers,\" (2) Accounting for uncertainties associated with different metrology tools and (3) Improving the robustness of the control algorithm. After implementation, in-silicon depth standard deviation was reduced to /spl sim/1/3 of its original value. SPC (statistical process control) parameters were also significantly improved.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76596731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001638
C. Putnam, H. Magoon, M. Alam, S. Beaumont, C. Fruga, F. Leung, E. Morita, R. Pierce, N. Roberts
The rapid pace in scanner technology has produced a situation where many process layers will have to be manufactured with a minimum depth of focus (DOF) of approximately 0.3 um with very stringent critical dimension (CD) control. This paper explores the application of Optical Critical Dimension (formerly called OCD, now MX-SMP) technology to measure and evaluate focus in addition to the CD response across the wafer.
{"title":"Scanner focus and CD response characterization metrology for sub 180 nm lithography","authors":"C. Putnam, H. Magoon, M. Alam, S. Beaumont, C. Fruga, F. Leung, E. Morita, R. Pierce, N. Roberts","doi":"10.1109/ASMC.2002.1001638","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001638","url":null,"abstract":"The rapid pace in scanner technology has produced a situation where many process layers will have to be manufactured with a minimum depth of focus (DOF) of approximately 0.3 um with very stringent critical dimension (CD) control. This paper explores the application of Optical Critical Dimension (formerly called OCD, now MX-SMP) technology to measure and evaluate focus in addition to the CD response across the wafer.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87844930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001581
P. Stöckl, B. Saville, J. Kavanagh, T. Dellwig
The introduction of yield sensitive, advanced interconnect technology coupled with the requirement for accelerating yield ramp in today's state-of-the-art semiconductor manufacturing facilities, are driving tool monitoring requirements for fast and accurate defect excursion control. In the Copper CMP module the challenge is accentuated by the relative immaturity of this process, the dominance of single wafer excursions and a high count of nuisance defect types relative to the critical yield-limiting defect types. A manufacturing-worthy Copper CMP tool monitor methodology is described here that improves excursion control through detection and tracking of critical, yield-limiting defect types, independent of non-yield-critical nuisance defect types. High-resolution automatic defect review and classification, a critical component of the methodology, is limited to wafers with high critical-defect counts, reducing monitoring cost and time-to-results. A new trigger sampling feature and intelligent image sampling reduces monitoring cost and time-to-results through minimizing defect review overhead. Integration of such a solution into the manufacturing environment is presented in detail and contrasted next to existing traditional defect excursion control model. Ease-of-use considerations are highlighted with use case examples. The paper will approximate the cost savings to manufacturing such as reducing existing levels of false excursion due to nuisance defects and improving the cycle time in the Cu CMP module. Benefits are achieved by integrating functionality into existing inspection hardware. No additional capital equipment was required.
{"title":"Advanced Cu CMP defect excursion control for leading edge micro-processor manufacturing","authors":"P. Stöckl, B. Saville, J. Kavanagh, T. Dellwig","doi":"10.1109/ASMC.2002.1001581","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001581","url":null,"abstract":"The introduction of yield sensitive, advanced interconnect technology coupled with the requirement for accelerating yield ramp in today's state-of-the-art semiconductor manufacturing facilities, are driving tool monitoring requirements for fast and accurate defect excursion control. In the Copper CMP module the challenge is accentuated by the relative immaturity of this process, the dominance of single wafer excursions and a high count of nuisance defect types relative to the critical yield-limiting defect types. A manufacturing-worthy Copper CMP tool monitor methodology is described here that improves excursion control through detection and tracking of critical, yield-limiting defect types, independent of non-yield-critical nuisance defect types. High-resolution automatic defect review and classification, a critical component of the methodology, is limited to wafers with high critical-defect counts, reducing monitoring cost and time-to-results. A new trigger sampling feature and intelligent image sampling reduces monitoring cost and time-to-results through minimizing defect review overhead. Integration of such a solution into the manufacturing environment is presented in detail and contrasted next to existing traditional defect excursion control model. Ease-of-use considerations are highlighted with use case examples. The paper will approximate the cost savings to manufacturing such as reducing existing levels of false excursion due to nuisance defects and improving the cycle time in the Cu CMP module. Benefits are achieved by integrating functionality into existing inspection hardware. No additional capital equipment was required.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74071988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001633
H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien
Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed "Hammer"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.
{"title":"Manufacturing implementation of low-k dielectrics for copper damascene technology","authors":"H. Ruelke, C. Streck, J. Hohage, S. Weiher-Telford, O. Chretrien","doi":"10.1109/ASMC.2002.1001633","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001633","url":null,"abstract":"Advanced logic devices are setting new demands for backend integration. New high-end processor families like the AMD Athlon/sup TM/ and AMD's eighth generation processor (codenamed \"Hammer\"), require the introduction of low-k interlayer dielectric (ILD) materials with copper to enable improvements in chip speed and reduction of overall power consumption. This is a challenging process for both tool suppliers and integrated circuit manufacturers. The semiconductor industry is looking for a low-k solution that delivers easy-to-integrate, high-performance dielectric films combined with high throughput and low cost of ownership. Based on key technical and manufacturing requirements, Advanced Micro Devices, Inc. has chosen the Applied Materials Producer system for low-k dielectric process applications. Implementation of Black Diamond/sup TM/ (BD) and BLOk/sup TM/ into the process flow enables an integrated k value of <3.0, which represents a 20 percent reduction compared to fluorinated silicate glass (F-TEOS) and silicon nitride (SiN). At Fab 30, AMD's advanced copper manufacturing line, the Producer has demonstrated reliable and stable performance in high volume production for the deposition of conventional dielectric films. This paper focuses on bringing a low-k dielectric solution beyond F-TEOS to full manufacturing readiness for copper interconnect technology.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76728793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001642
R. Ridley, C. Strate, J. Cumbo, T. Grebs, C. Gasser
In this investigation the implementation of AFM as a tool for process control as well as a metrology tool for characterizing trench MOSFET devices in a manufacturing environment is examined. In particular this study focuses on three major issues surrounding the implementation of AFM into a high-volume manufacturing environment for process control. First, factors influencing automated data collection are reviewed including scan calibration, alignment identification, alignment issues, and SPC optimization. Second, the critical features of AFM tip selection, behavior, and capability are discussed. Finally, AFM monitoring capability for features within the trench, such as recessed polysilicon and ILD planarization, is evaluated. The AFM is shown to be effective at evaluating depth and surface topography issues. However, the AFM's ability to monitor critical dimension (CD) openings is shown to be very limited.
{"title":"The implementation of AFM for process monitoring and metrology in trench MOSFET device manufacturing","authors":"R. Ridley, C. Strate, J. Cumbo, T. Grebs, C. Gasser","doi":"10.1109/ASMC.2002.1001642","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001642","url":null,"abstract":"In this investigation the implementation of AFM as a tool for process control as well as a metrology tool for characterizing trench MOSFET devices in a manufacturing environment is examined. In particular this study focuses on three major issues surrounding the implementation of AFM into a high-volume manufacturing environment for process control. First, factors influencing automated data collection are reviewed including scan calibration, alignment identification, alignment issues, and SPC optimization. Second, the critical features of AFM tip selection, behavior, and capability are discussed. Finally, AFM monitoring capability for features within the trench, such as recessed polysilicon and ILD planarization, is evaluated. The AFM is shown to be effective at evaluating depth and surface topography issues. However, the AFM's ability to monitor critical dimension (CD) openings is shown to be very limited.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74585248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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