Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001612
D. Maynard, B. B. Reuter, J. Patrick
Historically, physical design characterization (PDC) has been the focus of product or design engineers. This paper introduces PDC from a manufacturing perspective and the value of design-specific information for successful process control. Several PDC tools are described in terms of this integrated approach and the current embodiment at the IBM Microelectronics Vermont facility. Specifically, these tools include pattern density calculations, critical area extractions, and "swampfinding", a method for locating specific design-process sensitivities. The paper then develops both the technical and business strategies that leverage this information into the manufacturing processes. To clearly illustrate the concepts introduced, several examples of PDC results augmented with traditional characterization information, along with the ensuing manufacturing actions are reviewed. Finally, the larger picture of physical design characterization in manufacturing, and the impact upon development, are further developed.
{"title":"A manufacturing perspective of physical design characterization","authors":"D. Maynard, B. B. Reuter, J. Patrick","doi":"10.1109/ASMC.2002.1001612","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001612","url":null,"abstract":"Historically, physical design characterization (PDC) has been the focus of product or design engineers. This paper introduces PDC from a manufacturing perspective and the value of design-specific information for successful process control. Several PDC tools are described in terms of this integrated approach and the current embodiment at the IBM Microelectronics Vermont facility. Specifically, these tools include pattern density calculations, critical area extractions, and \"swampfinding\", a method for locating specific design-process sensitivities. The paper then develops both the technical and business strategies that leverage this information into the manufacturing processes. To clearly illustrate the concepts introduced, several examples of PDC results augmented with traditional characterization information, along with the ensuing manufacturing actions are reviewed. Finally, the larger picture of physical design characterization in manufacturing, and the impact upon development, are further developed.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84642484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001593
A. Flores, J. Lebowitz, W. Pressnall, C. Martin, C. Bradford Hopper
A data analysis framework has been implemented at the Texas Instruments Kilby Fabrication Center which encourages best practice decision making for yield, equipment and product engineers and managers by incorporating a continuous data flow across multiple vertically focused analytical tools and data sources. This data flow moves beyond drill down and OLAP techniques to "drill across" domains and mirror the way engineers naturally perform exploratory yield analysis. The data flow is presented to users in the form of Process Guides, which codify best practice analysis techniques by stepping the user through data access, analysis and collaboration. Rather than replacing vertical applications and data sources, each step of a given process guide adds value to existing point solutions for electrical test, defect, manufacturing execution, wafer position and process data. The architecture of the system is discussed, and examples of Process Guides are shown which illustrate the interactivity of the presentation layer and the flexibility of the framework to deliver best practice techniques for solving cross functional problems.
{"title":"KFAB DecisionSite: an interactive, exploratory yield analysis framework","authors":"A. Flores, J. Lebowitz, W. Pressnall, C. Martin, C. Bradford Hopper","doi":"10.1109/ASMC.2002.1001593","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001593","url":null,"abstract":"A data analysis framework has been implemented at the Texas Instruments Kilby Fabrication Center which encourages best practice decision making for yield, equipment and product engineers and managers by incorporating a continuous data flow across multiple vertically focused analytical tools and data sources. This data flow moves beyond drill down and OLAP techniques to \"drill across\" domains and mirror the way engineers naturally perform exploratory yield analysis. The data flow is presented to users in the form of Process Guides, which codify best practice analysis techniques by stepping the user through data access, analysis and collaboration. Rather than replacing vertical applications and data sources, each step of a given process guide adds value to existing point solutions for electrical test, defect, manufacturing execution, wafer position and process data. The architecture of the system is discussed, and examples of Process Guides are shown which illustrate the interactivity of the presentation layer and the flexibility of the framework to deliver best practice techniques for solving cross functional problems.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84525911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001578
K. Nemoto, S. Ikeda, O. Yoshida, J. Sasabe, Hua Su
A method is described for reducing systematic defects in the initial stages of production and thereby improving yield. Statistical correlation analysis is used to find the critical process parameters that cause yield loss. Application of the proposed method to actual 300-mm wafer fabrication demonstrated that it does detect the parameters to be modified resulting in yield improvement.
{"title":"A statistical method for reducing systematic defects in the initial stages of production","authors":"K. Nemoto, S. Ikeda, O. Yoshida, J. Sasabe, Hua Su","doi":"10.1109/ASMC.2002.1001578","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001578","url":null,"abstract":"A method is described for reducing systematic defects in the initial stages of production and thereby improving yield. Statistical correlation analysis is used to find the critical process parameters that cause yield loss. Application of the proposed method to actual 300-mm wafer fabrication demonstrated that it does detect the parameters to be modified resulting in yield improvement.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89074629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001587
J. Moyne, V. Solakhian, A. Yershov, M. Anderson, D. Mockler-Hebert
A multi-component Advanced Process Control (APC) system has been developed and deployed for an Applied Materials vapor phase epitaxy tool at Fairchild Semiconductor. The system, which is fully automated, operates on a SEMI APC framework compliant platform, supports the plug-and-play of multiple APC applications ("plug-ins"), and has configurable control rules that allow the user to specify not only how each APC application will be utilized, but also how the APC applications will interact in a complementary fashion. The current system contains real-time data visualization, run-to-run control (R2R), and fault detection and classification (FDC) plug-ins. The data visualization component is currently being utilized for real-time visual monitoring of aspects of equipment health. The R2R component includes a multivariate algorithm and is being used to provide multi-zone control of deposition thickness and resistivity. The FDC component will gather the in-process data from the tool to automatically determine equipment health and classify faults in order to reduce mean time to repair. In this paper, the methodology used to deploy and configure this APC system is described. Data is provided illustrating the use of each of these APC capabilities individually and in complementary fashion. Data analysis is included that focuses on the benefits of utilizing these capabilities, benefits such as improved equipment reliability, improved overall equipment effectiveness and yield. The paper also includes a discussion of the benefits and issues associated with the complementary utilization of multiple APC components in an open architecture framework.
{"title":"Development and deployment of a multi-component Advanced Process Control system for an epitaxy tool","authors":"J. Moyne, V. Solakhian, A. Yershov, M. Anderson, D. Mockler-Hebert","doi":"10.1109/ASMC.2002.1001587","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001587","url":null,"abstract":"A multi-component Advanced Process Control (APC) system has been developed and deployed for an Applied Materials vapor phase epitaxy tool at Fairchild Semiconductor. The system, which is fully automated, operates on a SEMI APC framework compliant platform, supports the plug-and-play of multiple APC applications (\"plug-ins\"), and has configurable control rules that allow the user to specify not only how each APC application will be utilized, but also how the APC applications will interact in a complementary fashion. The current system contains real-time data visualization, run-to-run control (R2R), and fault detection and classification (FDC) plug-ins. The data visualization component is currently being utilized for real-time visual monitoring of aspects of equipment health. The R2R component includes a multivariate algorithm and is being used to provide multi-zone control of deposition thickness and resistivity. The FDC component will gather the in-process data from the tool to automatically determine equipment health and classify faults in order to reduce mean time to repair. In this paper, the methodology used to deploy and configure this APC system is described. Data is provided illustrating the use of each of these APC capabilities individually and in complementary fashion. Data analysis is included that focuses on the benefits of utilizing these capabilities, benefits such as improved equipment reliability, improved overall equipment effectiveness and yield. The paper also includes a discussion of the benefits and issues associated with the complementary utilization of multiple APC components in an open architecture framework.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89364350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001625
Yu-Min Ho, H. Parks, B. Vermeire
A thermal desorption apparatus has been developed to study the adsorption and desorption of organic contaminants on silicon wafers due to outgassing from plastic wafer carrier boxes. This paper describes a complete outgassing model for organic contamination based on characterization of the outgassing of organic contamination from polypropylene carrier boxes using Butylated Hydroxytoluene (BHT) as a model compound. The model was developed from experimental data for a limited set of time/temperature conditions. Verification of the model is provided by its goodness of fit over an extended set of experimental data.
{"title":"A model for outgassing of organic contamination from wafer carrier boxes","authors":"Yu-Min Ho, H. Parks, B. Vermeire","doi":"10.1109/ASMC.2002.1001625","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001625","url":null,"abstract":"A thermal desorption apparatus has been developed to study the adsorption and desorption of organic contaminants on silicon wafers due to outgassing from plastic wafer carrier boxes. This paper describes a complete outgassing model for organic contamination based on characterization of the outgassing of organic contamination from polypropylene carrier boxes using Butylated Hydroxytoluene (BHT) as a model compound. The model was developed from experimental data for a limited set of time/temperature conditions. Verification of the model is provided by its goodness of fit over an extended set of experimental data.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87913083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001635
J. Campbell, M. Boyer, A. Griffin, Z. Imam, H. Lee, C. Montgomery, R. Pak, B. Vialpando
The susceptibility of a self-aligned titanium silicide (salicide) process to the occurrence of conductive sidewall filaments is shown to depend upon the type of wafer cleans that are used prior to the titanium deposition. Aggressive cleans that are predominantly used for resist stripping were implemented immediately following the blanket plasma etch processes that define the sidewall nitride spacers on polysilicon gates. These cleans were effective in reducing the incidence of unwanted filaments between the polysilicon gates and the source/drain regions, as evidenced electrically using parametric test structures and physically via transmission electron microscopy (TEM) characterization. Two mechanisms to explain the efficacy of the cleans are hypothesized and discussed.
{"title":"Sidewall clean effect upon titanium salicide filaments","authors":"J. Campbell, M. Boyer, A. Griffin, Z. Imam, H. Lee, C. Montgomery, R. Pak, B. Vialpando","doi":"10.1109/ASMC.2002.1001635","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001635","url":null,"abstract":"The susceptibility of a self-aligned titanium silicide (salicide) process to the occurrence of conductive sidewall filaments is shown to depend upon the type of wafer cleans that are used prior to the titanium deposition. Aggressive cleans that are predominantly used for resist stripping were implemented immediately following the blanket plasma etch processes that define the sidewall nitride spacers on polysilicon gates. These cleans were effective in reducing the incidence of unwanted filaments between the polysilicon gates and the source/drain regions, as evidenced electrically using parametric test structures and physically via transmission electron microscopy (TEM) characterization. Two mechanisms to explain the efficacy of the cleans are hypothesized and discussed.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86632098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001588
C. Viera, B. Gurcan, K. Crocker, P. Todd, K. Lewis
Fluorine bubbles are a known result of BF/sub 2//sup +/ high energy implants. This work presents a failure mechanism induced by gross fluorine bubbles, that allows poly silicon to be damaged during its subsequent cobalt silicide etch. An alternative implant that includes both BF/sub 2//sup +/ and B11 may alleviate the effects of F precipitates without eliminating the benefits of BF/sub 2//sup +/ self-amorphizing the substrate.
{"title":"BF/sub 2//sup +/ implant: a fluorine bubble induced ET failure","authors":"C. Viera, B. Gurcan, K. Crocker, P. Todd, K. Lewis","doi":"10.1109/ASMC.2002.1001588","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001588","url":null,"abstract":"Fluorine bubbles are a known result of BF/sub 2//sup +/ high energy implants. This work presents a failure mechanism induced by gross fluorine bubbles, that allows poly silicon to be damaged during its subsequent cobalt silicide etch. An alternative implant that includes both BF/sub 2//sup +/ and B11 may alleviate the effects of F precipitates without eliminating the benefits of BF/sub 2//sup +/ self-amorphizing the substrate.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74592221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001571
R. Immelman
A study of enterprise-level project management reveals disparity between factors considered important for effective enterprise-level project management, and the current reality experienced by respondents. This points to unresolved systemic factors that drive unsatisfactory performance. The management of task variability, combined with a clear understanding of both task and resource dependency at project level offers an avenue to shorten project leadtime and smooth workflow. Combined with an understanding of the impact of key resource constraints across a set of projects, it is possible to improve portfolio selection and pipeline staging. By focusing on key metrics in project planning and project execution, resource utilization can be maximized and projects completed with shorter lead times.
{"title":"Fulfilling the speed imperative: new product development and enterprise project management in the new economy","authors":"R. Immelman","doi":"10.1109/ASMC.2002.1001571","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001571","url":null,"abstract":"A study of enterprise-level project management reveals disparity between factors considered important for effective enterprise-level project management, and the current reality experienced by respondents. This points to unresolved systemic factors that drive unsatisfactory performance. The management of task variability, combined with a clear understanding of both task and resource dependency at project level offers an avenue to shorten project leadtime and smooth workflow. Combined with an understanding of the impact of key resource constraints across a set of projects, it is possible to improve portfolio selection and pipeline staging. By focusing on key metrics in project planning and project execution, resource utilization can be maximized and projects completed with shorter lead times.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86674000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001637
E.G. Mammo, N. Singh, C. Mananquil, D. R. Myers
This paper discusses experimental results used to develop an optimized resist strip process for an Advanced Strip and Passivation (ASP+) chamber on Applied Materials Decoupled Plasma Source (DPS) 5200 metal etch platform. The scope of the experiment is to develop a resist strip process on a new ASIC BiCMOS product. To meet tight capacity schedule, the resist removal process must be relatively short. This experiment does not look for the shortest strip time, but considered various gas flow, passivation, and strip sequences to keep the resist strip time well below the total metal etch time. A design of experiment (DOE) was run to measure the response of key recipe parameters. The parameters evaluated were strip time, passivation time, passivation and strip sequence, CF/sub 4/ flow, and temperature. The response was the amount of residual resist remaining after the strip process is completed. The result showed that temperature was the major factor in effective resist removal followed by CF/sub 4/ flow and passivation/strip sequence. A second DOE was run to verify the results and lower margin. Based on the results of the DOE, a robust strip recipe was designed and implemented in manufacturing for all metal etch processes. The new process is shorter than the metal etch process, and does not affect the throughput of the system. Also, no residual resist is found since the new recipe and post-strip inspection procedure was implemented.
{"title":"Optimization of resist strip recipe for aluminum metal etch processes","authors":"E.G. Mammo, N. Singh, C. Mananquil, D. R. Myers","doi":"10.1109/ASMC.2002.1001637","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001637","url":null,"abstract":"This paper discusses experimental results used to develop an optimized resist strip process for an Advanced Strip and Passivation (ASP+) chamber on Applied Materials Decoupled Plasma Source (DPS) 5200 metal etch platform. The scope of the experiment is to develop a resist strip process on a new ASIC BiCMOS product. To meet tight capacity schedule, the resist removal process must be relatively short. This experiment does not look for the shortest strip time, but considered various gas flow, passivation, and strip sequences to keep the resist strip time well below the total metal etch time. A design of experiment (DOE) was run to measure the response of key recipe parameters. The parameters evaluated were strip time, passivation time, passivation and strip sequence, CF/sub 4/ flow, and temperature. The response was the amount of residual resist remaining after the strip process is completed. The result showed that temperature was the major factor in effective resist removal followed by CF/sub 4/ flow and passivation/strip sequence. A second DOE was run to verify the results and lower margin. Based on the results of the DOE, a robust strip recipe was designed and implemented in manufacturing for all metal etch processes. The new process is shorter than the metal etch process, and does not affect the throughput of the system. Also, no residual resist is found since the new recipe and post-strip inspection procedure was implemented.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87319728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001564
A. Usenko, W. Carr, Bo Chen, Y. Chabal
We describe for the first time a layer transfer caused by delamination along the hydrogen platelet layer formed by RF plasma hydrogenation at a place of end-of-range defects. The process involves first creating a buried trap layer using variously silicon, or argon implantation. Wafers thus processed with an initial implant to levels below 10/sup 16/ cm/sup -2/ are then hydrogenated with RF plasma. Next steps include pre-bonding, cleavage, and post-bonding as in the Smart-cut process. The cleavage occurs at a depth corresponding to the maximum of vacancy-enriched defects (between R/sub p//2 and R/sub p/). Plasma hydrogenation may be used as a step in the process of fabricating thin SOI wafers.
{"title":"Alternative Smart-cut-like process for ultra-thin SOI fabrication","authors":"A. Usenko, W. Carr, Bo Chen, Y. Chabal","doi":"10.1109/ASMC.2002.1001564","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001564","url":null,"abstract":"We describe for the first time a layer transfer caused by delamination along the hydrogen platelet layer formed by RF plasma hydrogenation at a place of end-of-range defects. The process involves first creating a buried trap layer using variously silicon, or argon implantation. Wafers thus processed with an initial implant to levels below 10/sup 16/ cm/sup -2/ are then hydrogenated with RF plasma. Next steps include pre-bonding, cleavage, and post-bonding as in the Smart-cut process. The cleavage occurs at a depth corresponding to the maximum of vacancy-enriched defects (between R/sub p//2 and R/sub p/). Plasma hydrogenation may be used as a step in the process of fabricating thin SOI wafers.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89590382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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