Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001602
K. Anderson, E. Hill, A. Mitchell
The quest for increased microprocessor speeds is inexorable... as microprocessor speeds pass two gigahertz, semiconductor manufacturers must wring all the available microprocessor speed from existing processes by any means possible. These means include designed experimentation and analysis of tightly controlled processes, many of which are approaching physical limits. Some questions an engineer must face when confronted with optimizing a 400-operation process is: At which operation to begin, and what factors in that operation influence what responses in the process? Then, after defined optimization projects have been completed: Have all the available opportunities for optimization been exhausted? One of the major products of microelectronics manufacturing is data: huge quantities of data are generated on every production lot processed through a fabrication facility. However, most of these data are observational (some would say 'happenstance') in nature, and are wrought with the problems of classical statistical analysis that experimental design procedures seek to avoid. Data Mining is loosely defined as an activity of extracting information from observational databases, wherein the goal is to discover hidden facts. One promising data mining technique is binary recursive partitioning. This technique is implemented in Classification And Regression Tree software by Salford Systems. This paper will explore the effective use of the CART/spl reg/ software tool to sift through the vast observational data generated in the production of microprocessors in the search of speed optimization opportunities. The procedures for using CART/spl reg/ to optimize microprocessor speed will be explained and demonstrated in several case studies.
{"title":"Spelunking in the data mine: on data mining as an analysis tool for the optimization of microprocessor speed","authors":"K. Anderson, E. Hill, A. Mitchell","doi":"10.1109/ASMC.2002.1001602","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001602","url":null,"abstract":"The quest for increased microprocessor speeds is inexorable... as microprocessor speeds pass two gigahertz, semiconductor manufacturers must wring all the available microprocessor speed from existing processes by any means possible. These means include designed experimentation and analysis of tightly controlled processes, many of which are approaching physical limits. Some questions an engineer must face when confronted with optimizing a 400-operation process is: At which operation to begin, and what factors in that operation influence what responses in the process? Then, after defined optimization projects have been completed: Have all the available opportunities for optimization been exhausted? One of the major products of microelectronics manufacturing is data: huge quantities of data are generated on every production lot processed through a fabrication facility. However, most of these data are observational (some would say 'happenstance') in nature, and are wrought with the problems of classical statistical analysis that experimental design procedures seek to avoid. Data Mining is loosely defined as an activity of extracting information from observational databases, wherein the goal is to discover hidden facts. One promising data mining technique is binary recursive partitioning. This technique is implemented in Classification And Regression Tree software by Salford Systems. This paper will explore the effective use of the CART/spl reg/ software tool to sift through the vast observational data generated in the production of microprocessors in the search of speed optimization opportunities. The procedures for using CART/spl reg/ to optimize microprocessor speed will be explained and demonstrated in several case studies.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81811679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001639
S. Leibiger
A comprehensive, yet easily used, set of SEM analysis structures is presented. These are currently being used in the development of a 0.35 micron, three layer metal, BiCMOS process flow. A summary list of the structure types and arrangements, key design considerations, SEM photographic results, and recommendations for improvement are included. A key design feature, a unique device navigation system allowing quick and accurate location of any particular structure is explained. Without such a feature, analysis would be difficult due to the large number, lateral size, and similarity of the various constructions.
{"title":"Comprehensive and easy to use SEM analysis structures for BiCMOS process development","authors":"S. Leibiger","doi":"10.1109/ASMC.2002.1001639","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001639","url":null,"abstract":"A comprehensive, yet easily used, set of SEM analysis structures is presented. These are currently being used in the development of a 0.35 micron, three layer metal, BiCMOS process flow. A summary list of the structure types and arrangements, key design considerations, SEM photographic results, and recommendations for improvement are included. A key design feature, a unique device navigation system allowing quick and accurate location of any particular structure is explained. Without such a feature, analysis would be difficult due to the large number, lateral size, and similarity of the various constructions.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89194900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001590
K. Woolford, C. Panczyk, G. Martel
Non-contact methods are now available to measure the resistivity of silicon epitaxy. The new technology offers wafer manufacturers the opportunity to significantly lower operating costs and increase reactor capacity by eliminating the need for monitor wafers. Our group investigated the Epimet Model 2 (SemiTest, Inc.) for monitoring epi wafer production. Our evaluation shows suitable measurement repeatability, reproducibility, and stability for the epi parts tested. Further, the Epimet significantly outperforms the Hg-probe CV in head-to-head measurement capability comparison. This paper focuses on the product-wafer integrity tests performed which demonstrated that the Epimet is indeed non-contaminating and non-damaging to wafers, allowing it to be used to monitor actual product wafers.
非接触的方法现在可以用来测量硅外延的电阻率。这项新技术为晶圆制造商提供了显著降低运营成本的机会，并通过消除对监控晶圆的需求来提高反应堆容量。我们的小组研究了Epimet Model 2 (SemiTest, Inc.)用于监测epi晶圆生产。我们的评估显示了合适的测量重复性、再现性和稳定性。此外，Epimet在头对头测量能力比较中显著优于hg探针CV。本文重点介绍了所进行的产品-晶圆完整性测试，这些测试表明Epimet确实对晶圆无污染且不损坏，因此可以用于监控实际产品晶圆。
{"title":"Epi resistivity profiles without wafer damage","authors":"K. Woolford, C. Panczyk, G. Martel","doi":"10.1109/ASMC.2002.1001590","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001590","url":null,"abstract":"Non-contact methods are now available to measure the resistivity of silicon epitaxy. The new technology offers wafer manufacturers the opportunity to significantly lower operating costs and increase reactor capacity by eliminating the need for monitor wafers. Our group investigated the Epimet Model 2 (SemiTest, Inc.) for monitoring epi wafer production. Our evaluation shows suitable measurement repeatability, reproducibility, and stability for the epi parts tested. Further, the Epimet significantly outperforms the Hg-probe CV in head-to-head measurement capability comparison. This paper focuses on the product-wafer integrity tests performed which demonstrated that the Epimet is indeed non-contaminating and non-damaging to wafers, allowing it to be used to monitor actual product wafers.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85738982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001600
Heather Maines, M. Rathmell, L. Veldhuis
In this study, we characterize thermal silicon dioxide, plasma enhanced CVD tetraorthosilicate oxide (PECVD TEOS) and phosphorous doped silicate glass (PSG) etch rates in SC1 as a function of temperature and concentration. We also measure the effect of implant screen oxide loss in SC1 on transistor voltage turn on and elucidate ways to reduce scrap due to oxide loss in SC1.
{"title":"Reduce scrap: control oxide loss in SC1","authors":"Heather Maines, M. Rathmell, L. Veldhuis","doi":"10.1109/ASMC.2002.1001600","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001600","url":null,"abstract":"In this study, we characterize thermal silicon dioxide, plasma enhanced CVD tetraorthosilicate oxide (PECVD TEOS) and phosphorous doped silicate glass (PSG) etch rates in SC1 as a function of temperature and concentration. We also measure the effect of implant screen oxide loss in SC1 on transistor voltage turn on and elucidate ways to reduce scrap due to oxide loss in SC1.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86348503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001636
L. Rothman, R. J. Robey, M. K. Ali, D. Mount
As semiconductor device dimensions approach the nanoscale, it will become increasing difficult to use aqueous-based cleaning processes due to high surface tension and capillary forces. Supercritical fluids provide the enabling capabilities for overcoming these process barriers. This paper will discuss the use of supercritical carbon dioxide and co-solvents for photoresist stripping and wafer cleaning.
{"title":"Supercritical fluid processes for semiconductor device fabrication","authors":"L. Rothman, R. J. Robey, M. K. Ali, D. Mount","doi":"10.1109/ASMC.2002.1001636","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001636","url":null,"abstract":"As semiconductor device dimensions approach the nanoscale, it will become increasing difficult to use aqueous-based cleaning processes due to high surface tension and capillary forces. Supercritical fluids provide the enabling capabilities for overcoming these process barriers. This paper will discuss the use of supercritical carbon dioxide and co-solvents for photoresist stripping and wafer cleaning.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79464119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001640
Zhengrong Zhu, A.L. Swecker, A. Strojwas
Wafer inspection schemes for next generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of DUV wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning or full field schemes can be extremely costly and therefore simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a three-dimensional simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. In this paper, we will present simulation results from METRO-3D for various wafer inspection schemes, including high numerical aperture schemes, on NGL topographies with highly absorptive materials.
{"title":"METRO-3D: an efficient three-dimensional wafer inspection simulator for next generation lithography","authors":"Zhengrong Zhu, A.L. Swecker, A. Strojwas","doi":"10.1109/ASMC.2002.1001640","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001640","url":null,"abstract":"Wafer inspection schemes for next generation lithography (NGL) will play a key role in controlling defect mechanisms and maintaining an acceptable yield. Developing these wafer inspection schemes will require characterization and optimization of DUV wavelength illumination at high numerical apertures (greater than 0.9) to detect defects that may be a fraction of the design rule. Using wafer inspection test benches that provide the flexibility for various illumination polarizations, numerical apertures, scanning or full field schemes can be extremely costly and therefore simulation of these schemes is necessary to characterize the various detection parameters. To model defects for NGL, three-dimensional simulation tools will be required to simulate highly absorptive material in the environment of shorter wavelength illumination. Also, the simulator will be required to simulate high numerical aperture (NA) inspection schemes to capture small defects. With the development of METRO-3D, a three-dimensional simulation tool that rigorously solves the EM field on arbitrary wafer topographies, we are able to model and characterize the wafer inspection schemes for NGL. In this paper, we will present simulation results from METRO-3D for various wafer inspection schemes, including high numerical aperture schemes, on NGL topographies with highly absorptive materials.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84600590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001614
G. A. Allan
This paper reports a new layout modification tool for the automation of yield and reliability enhancement of IC layout. The peye tool combines the eye (Edinburgh Yield Estimator) with Perl (Practical Extraction and Reporting Language). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The new peye tool has been interfaced with a sampling based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. Results of layout modifications are presented.
本文报道了一种新的版图修改工具，用于集成电路版图的成品率和可靠性的自动化提高。peye工具结合了eye (Edinburgh Yield Estimator)和Perl (Practical Extraction and Reporting Language)。这个新工具允许使用Perl强大的语言特性定义复杂的布局修改操作。新的peye工具与基于采样的产量预测系统相结合，可以测量布局修改并根据这些修改进行产量预测。这样就可以在使用前评估对特定设计进行修改的有用性。采样测量和对整个芯片数据库的最终修改都可以外包给许多联网的计算机，使系统能够在合理的时间内评估和应用大型工业ic的布局修改。给出了布局修改的结果。
{"title":"Yield/reliability enhancement using automated minor layout modifications","authors":"G. A. Allan","doi":"10.1109/ASMC.2002.1001614","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001614","url":null,"abstract":"This paper reports a new layout modification tool for the automation of yield and reliability enhancement of IC layout. The peye tool combines the eye (Edinburgh Yield Estimator) with Perl (Practical Extraction and Reporting Language). This new tool permits complex layout modification operations to be defined using the powerful language features of Perl. The new peye tool has been interfaced with a sampling based yield prediction system to enable the measurement of the layout modifications and yield predictions based on these modifications. This enables the usefulness of a modification to a particular design to be assessed before use. Both the sampled measurement and the final modifications to the whole chip database can be farmed out to a number of networked computers, enabling the system to assess and apply layout modifications to large industrial ICs in a reasonable time. Results of layout modifications are presented.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79400966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001618
M. Gupta, G. Rajagopalan, C. K. Hong, J. Lu, K. Rose, R. Gutmann
The planarization requirements for 3D processing are compared to those for conventional 2D processing, indicating that wafer level planarity is essential for 3D as compared to the die level planarity needed for 2D ICs. A yield test structure has been designed to study the number of electrical faults that occur during damascene patterning. Initial experimental data with this test vehicle show that planarity changes with pattern density, although the functional relationship has not been established to date.
{"title":"Planarization yield limiters for wafer-scale 3D ICs","authors":"M. Gupta, G. Rajagopalan, C. K. Hong, J. Lu, K. Rose, R. Gutmann","doi":"10.1109/ASMC.2002.1001618","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001618","url":null,"abstract":"The planarization requirements for 3D processing are compared to those for conventional 2D processing, indicating that wafer level planarity is essential for 3D as compared to the die level planarity needed for 2D ICs. A yield test structure has been designed to study the number of electrical faults that occur during damascene patterning. Initial experimental data with this test vehicle show that planarity changes with pattern density, although the functional relationship has not been established to date.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73084180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001619
Amy Engbrecht, R. Jarvis, A. Warrick
An advanced methodology was implemented using intentionally created defect arrays to enhance the understanding of defect detection tools, thus improving yield learning. Intentional Defect Array (IDA) reticles were designed at International SEMATECH to target current and future ITRS requirements. Each IDA die pattern contains separate inspection areas for metal line widths of 0.18 /spl mu/m, 0.25 /spl mu/m, and 0.35 /spl mu/m. Defect sizes at 25%, 50%, and 100% of the design feature size with known shapes and locations are placed in patterns of memory, logic, and electrical test arrays. Advanced lithographic capabilities, short-loop recipes, and dual damascene copper process flows were used to establish the IDA patterns on 200 mm wafers. The IDA wafers are being used in a variety of wafer inspection applications that require calculating capture and false count rates for defect detection. This paper describes the approach used for creating IDA wafers and the way these wafers can be applied to enhance product wafer yield.
{"title":"An approach for improving yield with intentional defects","authors":"Amy Engbrecht, R. Jarvis, A. Warrick","doi":"10.1109/ASMC.2002.1001619","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001619","url":null,"abstract":"An advanced methodology was implemented using intentionally created defect arrays to enhance the understanding of defect detection tools, thus improving yield learning. Intentional Defect Array (IDA) reticles were designed at International SEMATECH to target current and future ITRS requirements. Each IDA die pattern contains separate inspection areas for metal line widths of 0.18 /spl mu/m, 0.25 /spl mu/m, and 0.35 /spl mu/m. Defect sizes at 25%, 50%, and 100% of the design feature size with known shapes and locations are placed in patterns of memory, logic, and electrical test arrays. Advanced lithographic capabilities, short-loop recipes, and dual damascene copper process flows were used to establish the IDA patterns on 200 mm wafers. The IDA wafers are being used in a variety of wafer inspection applications that require calculating capture and false count rates for defect detection. This paper describes the approach used for creating IDA wafers and the way these wafers can be applied to enhance product wafer yield.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74038961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001577
A. Skumanich, E. Ryabova
A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies for optical capture and SEM review.
{"title":"Methodology for targeted defect reduction and inspection optimization","authors":"A. Skumanich, E. Ryabova","doi":"10.1109/ASMC.2002.1001577","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001577","url":null,"abstract":"A methodology is outlined to establish the prioritization of defects under conditions of low sampling statistics based on the deliberate introduction of defects at specific process points. Probe results from electrical test structures are correlated with optical defect inspection data to determine the kill rates of various defects. The methodology generalizes from a standard approach that typically relies on a high statistical sampling plan with significant wafer area coverage. In this case, the probed area coverage is reduced to 1-3% of the wafer surface but still provides defect impact prioritization for targeted defect reduction and optimized inspection strategies for optical capture and SEM review.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83993563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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