Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001599
P. Werbaneth, J. Almerico, L. Jerde, S. Marks, B. Wachtmann
Ion milling has been used in laboratory applications for patterning ferroelectric thin films and noble metal electrodes in Metal/Ferroelectric/Metal stacks. These MFM stacks are used to form several different families of MEMS devices: moving mirrors for optical signal switching applications, for example, utilize the piezoelectric properties of PZT; varactors, or other tunable circuit elements, depend on the dielectric nonlinearity of PZT and BST. The oxidizing environment encountered during the deposition of these ferroelectric films means that some material capable of resisting oxidation (platinum) or capable of forming an electrically conductive oxide (iridium or ruthenium) must be used as the metal electrode in any metal-ferroelectric-metal (MFM) stack. Its corrosion resistance, electromigration resistance and compatibility with standard IC fabs also make platinum attractive as an interconnect in many other MEMS applications. The physical action of energetic ions (usually argon) can remove surface atoms even when the vapor pressure of the material(s) to be removed is negligibly small. However, when ion milling is used to pattern platinum the removal rate is low (/spl sim/400 /spl Aring//min), the throughput is low, and the tendency is for the etched material to redeposit along the edge of the etch mask, creating veils, or fences, after the etch mask is removed. These residues, being electrically conductive, can lead to yield-limiting defects in finished devices. In this paper we report on MFM and interconnect stack etch results for MEMS applications from a dual frequency high density plasma etch reactor. Platinum and PZT etch rates greater than 100 /spl Aring//min are possible in this reactor at moderate (80/spl deg/C) wafer temperatures using photoresist masks. We can produce good etch profiles with no post-etch residue for MFM stacks like those used for a MEMS-based Atomic Force Microscopy application, for example, which employs a bottom platinum layer 1500 /spl Aring/ thick, 2800 /spl Aring/ of PZT, and a platinum top electrode of 1500 /spl Aring/. We also present production data from a process for etching a platinum/titanium-tungsten (10%/90%) stack for a micromachined mirror device.
{"title":"Pt/PZT/Pt and Pt/barrier stack etches for MEMS devices in a dual frequency high density plasma reactor","authors":"P. Werbaneth, J. Almerico, L. Jerde, S. Marks, B. Wachtmann","doi":"10.1109/ASMC.2002.1001599","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001599","url":null,"abstract":"Ion milling has been used in laboratory applications for patterning ferroelectric thin films and noble metal electrodes in Metal/Ferroelectric/Metal stacks. These MFM stacks are used to form several different families of MEMS devices: moving mirrors for optical signal switching applications, for example, utilize the piezoelectric properties of PZT; varactors, or other tunable circuit elements, depend on the dielectric nonlinearity of PZT and BST. The oxidizing environment encountered during the deposition of these ferroelectric films means that some material capable of resisting oxidation (platinum) or capable of forming an electrically conductive oxide (iridium or ruthenium) must be used as the metal electrode in any metal-ferroelectric-metal (MFM) stack. Its corrosion resistance, electromigration resistance and compatibility with standard IC fabs also make platinum attractive as an interconnect in many other MEMS applications. The physical action of energetic ions (usually argon) can remove surface atoms even when the vapor pressure of the material(s) to be removed is negligibly small. However, when ion milling is used to pattern platinum the removal rate is low (/spl sim/400 /spl Aring//min), the throughput is low, and the tendency is for the etched material to redeposit along the edge of the etch mask, creating veils, or fences, after the etch mask is removed. These residues, being electrically conductive, can lead to yield-limiting defects in finished devices. In this paper we report on MFM and interconnect stack etch results for MEMS applications from a dual frequency high density plasma etch reactor. Platinum and PZT etch rates greater than 100 /spl Aring//min are possible in this reactor at moderate (80/spl deg/C) wafer temperatures using photoresist masks. We can produce good etch profiles with no post-etch residue for MFM stacks like those used for a MEMS-based Atomic Force Microscopy application, for example, which employs a bottom platinum layer 1500 /spl Aring/ thick, 2800 /spl Aring/ of PZT, and a platinum top electrode of 1500 /spl Aring/. We also present production data from a process for etching a platinum/titanium-tungsten (10%/90%) stack for a micromachined mirror device.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90640937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001574
D. Williams, D. Favero
In semiconductor manufacturing, according to Marcoux et al. (1999) tool deployment has been identified as a key factor driving capacity loss and lower operational efficiency. In most cases, the losses are uncovered by analysis of Cycle Time data and investigation of specific tool performance. For the photolithography sector, this feedback approach often highlights problems after they may have already past or have been fixed. This paper will discuss a feed forward model for managing deployment of a large fleet of photolithography tools. This model predicts tool loading using existing tool planning parameters, actual and forecast wafer start data and extensive turn-around-time matrices. The model provides a portable tool with immediate readout of various loading scenarios. The deployment decision process makes use of these simulations. The model output comes in the form of graphs and tables that can summarize load by tool, tool groups, resist groups, technologies, and levels at various time slices. The output identifies where tool qualifications or additional resists may be needed, and deployment adjustments for WIP balance is warranted. These changes prevent operational efficiency loss and maintain cycle time performance.
{"title":"Dynamic deployment modeling tool for photolithography WIP management","authors":"D. Williams, D. Favero","doi":"10.1109/ASMC.2002.1001574","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001574","url":null,"abstract":"In semiconductor manufacturing, according to Marcoux et al. (1999) tool deployment has been identified as a key factor driving capacity loss and lower operational efficiency. In most cases, the losses are uncovered by analysis of Cycle Time data and investigation of specific tool performance. For the photolithography sector, this feedback approach often highlights problems after they may have already past or have been fixed. This paper will discuss a feed forward model for managing deployment of a large fleet of photolithography tools. This model predicts tool loading using existing tool planning parameters, actual and forecast wafer start data and extensive turn-around-time matrices. The model provides a portable tool with immediate readout of various loading scenarios. The deployment decision process makes use of these simulations. The model output comes in the form of graphs and tables that can summarize load by tool, tool groups, resist groups, technologies, and levels at various time slices. The output identifies where tool qualifications or additional resists may be needed, and deployment adjustments for WIP balance is warranted. These changes prevent operational efficiency loss and maintain cycle time performance.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78778213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001576
L. Cheema, L. Olmer, O. Patterson, S. López, M. Burns
Semiconductor manufacturers employ various techniques and tools to detect and identify the physical defects that limit product and process yields. Most of these techniques focus on measuring the front side of the semiconductor wafer where the devices are manufactured. Attention to defectivity on the wafer backside has been minimal. Two possible reasons are the lack of suitable equipment and methods, and a lack of awareness of how backside defectivity can affect a manufacturing line. This paper presents four case studies which describe how back side defectivity can affect yield, scrap and production costs. New technology, which facilitates backside inspection, has recently been developed. Key improvements include the ability to non-destructively scan wafer backsides and improved coordinate accuracy, which allows adder calculations and SEM review. This paper describes how this new technology was applied in these case studies, thereby improving yield and reducing scrap and production costs.
{"title":"Wafer back side inspection applications for yield protection and enhancement","authors":"L. Cheema, L. Olmer, O. Patterson, S. López, M. Burns","doi":"10.1109/ASMC.2002.1001576","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001576","url":null,"abstract":"Semiconductor manufacturers employ various techniques and tools to detect and identify the physical defects that limit product and process yields. Most of these techniques focus on measuring the front side of the semiconductor wafer where the devices are manufactured. Attention to defectivity on the wafer backside has been minimal. Two possible reasons are the lack of suitable equipment and methods, and a lack of awareness of how backside defectivity can affect a manufacturing line. This paper presents four case studies which describe how back side defectivity can affect yield, scrap and production costs. New technology, which facilitates backside inspection, has recently been developed. Key improvements include the ability to non-destructively scan wafer backsides and improved coordinate accuracy, which allows adder calculations and SEM review. This paper describes how this new technology was applied in these case studies, thereby improving yield and reducing scrap and production costs.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79534169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001565
W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi
A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.
{"title":"A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies","authors":"W. Lien, W.G. Yeh, C.H. Li, K. Tu, I.H. Chang, H. Chu, W.R. Liaw, H.F. Lee, H. Chou, C.Y. Chen, M.H. Chi","doi":"10.1109/ASMC.2002.1001565","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001565","url":null,"abstract":"A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72846811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001605
I. Bansal, B. Cochran, J. Goodrich, M. Marcel, Joseph Maniachi
An ultra-dilute clean chemistry was successfully employed for effective removal of both surface haze and submicron particulate contamination from silicon wafer substrates. The cleaning chemistry was ultra-dilute RCA-SC1 followed by RCA-SC2 solutions. All chemical cleaning and deionized water (DI) rinsing steps were performed in the same processing vessel. The drying vessel was a "motionless" system. The chemical cleaning, DI water rinsing and drying processes were carried out at an ambient temperature. A laser beam scanning system was employed to directly measure surface haze concentration and light point defects (LPD's) density at or above 0.5-/spl mu/m particle size. Ultra-dilute clean chemistry has been in active use for various manufacturing processes including prebonding, pre-diffusion/oxidation, preepitaxial deposition, post-lasermark, post-chemical mechanical polishing (CMP) cleaning operations. The manufacturing data in terms of particle removal efficiency are discussed The electrical data for total oxide surface charge, density of interface traps, as well as regeneration lifetime are also presented in this paper. A key advantage of this ultra-dilute cleaning system over a conventional wet bench is an approximate 3-fold reduction in the volume of chemical usage. The net cost saving for chemicals including DI water is estimated at $2.32 for each 25-wafers product lot. In addition, an approximate 8-fold reduction could be realized in the wastewater loading. Therefore, this ultra-dilute cleaning operation is both environmental friendly and cost effective.
{"title":"Ultra-dilute silicon wafer clean chemistry for fabrication of RF microwave devices","authors":"I. Bansal, B. Cochran, J. Goodrich, M. Marcel, Joseph Maniachi","doi":"10.1109/ASMC.2002.1001605","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001605","url":null,"abstract":"An ultra-dilute clean chemistry was successfully employed for effective removal of both surface haze and submicron particulate contamination from silicon wafer substrates. The cleaning chemistry was ultra-dilute RCA-SC1 followed by RCA-SC2 solutions. All chemical cleaning and deionized water (DI) rinsing steps were performed in the same processing vessel. The drying vessel was a \"motionless\" system. The chemical cleaning, DI water rinsing and drying processes were carried out at an ambient temperature. A laser beam scanning system was employed to directly measure surface haze concentration and light point defects (LPD's) density at or above 0.5-/spl mu/m particle size. Ultra-dilute clean chemistry has been in active use for various manufacturing processes including prebonding, pre-diffusion/oxidation, preepitaxial deposition, post-lasermark, post-chemical mechanical polishing (CMP) cleaning operations. The manufacturing data in terms of particle removal efficiency are discussed The electrical data for total oxide surface charge, density of interface traps, as well as regeneration lifetime are also presented in this paper. A key advantage of this ultra-dilute cleaning system over a conventional wet bench is an approximate 3-fold reduction in the volume of chemical usage. The net cost saving for chemicals including DI water is estimated at $2.32 for each 25-wafers product lot. In addition, an approximate 8-fold reduction could be realized in the wastewater loading. Therefore, this ultra-dilute cleaning operation is both environmental friendly and cost effective.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72890855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001621
G. Baweja, M. Chandrasekaran, B. OuYang
Due to the capital intensive nature of semiconductor manufacturing, companies are consistently looking for ways to maximize the utilization of the manufacturing tools and avoid errors that may result in loss of capacity. Incorrect specification of the process parameters while processing products is a major source of scrap and yield loss, thus resulting in lost capacity. A recipe management system, which can be used to consistently manage all types of recipe, will go a long way to address this issue. This paper presents the data flow and functional design to support a recipe controller. This methodology of recipe management can be used for all three recipe formats-binary, formatted and ASCII. The methodology is based on the use of a mapping file. This paper presents the challenges/issues while dealing with different recipe formats, along with examples, and further develops an approach for a recipe controller.
{"title":"An approach to recipe control in wafer fab","authors":"G. Baweja, M. Chandrasekaran, B. OuYang","doi":"10.1109/ASMC.2002.1001621","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001621","url":null,"abstract":"Due to the capital intensive nature of semiconductor manufacturing, companies are consistently looking for ways to maximize the utilization of the manufacturing tools and avoid errors that may result in loss of capacity. Incorrect specification of the process parameters while processing products is a major source of scrap and yield loss, thus resulting in lost capacity. A recipe management system, which can be used to consistently manage all types of recipe, will go a long way to address this issue. This paper presents the data flow and functional design to support a recipe controller. This methodology of recipe management can be used for all three recipe formats-binary, formatted and ASCII. The methodology is based on the use of a mapping file. This paper presents the challenges/issues while dealing with different recipe formats, along with examples, and further develops an approach for a recipe controller.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75312990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001615
V. Raghavan
In order to meet high expectations on yield targets, quick identification of root cause for yield loss is essential. Decision trees are shown to be a powerful data mining tool for integrated circuit yield improvement. Several case studies from yield improvement efforts on real products have been presented.
{"title":"Application of decision trees for integrated circuit yield improvement","authors":"V. Raghavan","doi":"10.1109/ASMC.2002.1001615","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001615","url":null,"abstract":"In order to meet high expectations on yield targets, quick identification of root cause for yield loss is essential. Decision trees are shown to be a powerful data mining tool for integrated circuit yield improvement. Several case studies from yield improvement efforts on real products have been presented.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78796657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001585
Ralph Trunk, H. Schmid, C. Schneider, L. Pfitzner, H. Ryssel
When loading and unloading wafers in semiconductor process furnaces, particles from coatings may flake from wafer edges, wafer surfaces, or the boat. This effect is frequently not detected in time. Using an experimental setup, the particle generation and transport behavior was investigated. Based on these investigations, a prototype of an ISPM system was designed and integrated into the loading station of a vertical production furnace. The handling system of the furnace was characterized and monitored my means of the ISPM system and a correlation with wafer surface particle test data was found.
{"title":"HandMon-ISPM: handling monitoring in a loading station of a furnace","authors":"Ralph Trunk, H. Schmid, C. Schneider, L. Pfitzner, H. Ryssel","doi":"10.1109/ASMC.2002.1001585","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001585","url":null,"abstract":"When loading and unloading wafers in semiconductor process furnaces, particles from coatings may flake from wafer edges, wafer surfaces, or the boat. This effect is frequently not detected in time. Using an experimental setup, the particle generation and transport behavior was investigated. Based on these investigations, a prototype of an ISPM system was designed and integrated into the loading station of a vertical production furnace. The handling system of the furnace was characterized and monitored my means of the ISPM system and a correlation with wafer surface particle test data was found.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75833395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001610
M. Lesiecki, B. Simington
Skill Standards are quality standards applied to people. In this project the goal was to develop a skill standards document that identifies the standards in terms of expected behavior, the condition and the standard for performance for technicians working in highly automated environments such as 300 mm fabs with highly centralized manufacturing execution systems and automated materials handling systems.
{"title":"Development of national skill standards for technicians working in highly automated (300 mm) environments","authors":"M. Lesiecki, B. Simington","doi":"10.1109/ASMC.2002.1001610","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001610","url":null,"abstract":"Skill Standards are quality standards applied to people. In this project the goal was to develop a skill standards document that identifies the standards in terms of expected behavior, the condition and the standard for performance for technicians working in highly automated environments such as 300 mm fabs with highly centralized manufacturing execution systems and automated materials handling systems.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74986032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001570
S. Ekbundit, B. Izzio
Wafer uniformity of silicon oxide deposited on 8-in wafer using LPCVD TEOS vertical furnace is examined with an attempt to understand a source of poor uniformity in the bottom zone as observed in most TEOS batch process. By utilizing boat rotation capability, more information can be obtained regarding a possible flow dynamics of the reactive gases, the mechanism that might be responsible for thickness distribution within wafer. Importantly, the results from this study suggested that the nonuniformity of the oxide film deposited using TEOS is most influence by the kinetics of the decomposition reaction of TEOS rather than a temperature variation on the substrate surface.
{"title":"Characterization of film uniformity in LPCVD TEOS vertical furnace","authors":"S. Ekbundit, B. Izzio","doi":"10.1109/ASMC.2002.1001570","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001570","url":null,"abstract":"Wafer uniformity of silicon oxide deposited on 8-in wafer using LPCVD TEOS vertical furnace is examined with an attempt to understand a source of poor uniformity in the bottom zone as observed in most TEOS batch process. By utilizing boat rotation capability, more information can be obtained regarding a possible flow dynamics of the reactive gases, the mechanism that might be responsible for thickness distribution within wafer. Importantly, the results from this study suggested that the nonuniformity of the oxide film deposited using TEOS is most influence by the kinetics of the decomposition reaction of TEOS rather than a temperature variation on the substrate surface.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83169412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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