Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001563
F. Cubaynes, S. Passefort, K. Eason, Xiafang Zhang, L. Date, D. Pique, T. Conard, A. Rothschild, M. Schaekers
In this paper, in-line measurements of ultrathin gate dielectrics are reported. Various plasma nitrided oxides down to 1.5 nm EOT have been studied using in-line optical and non-contact electrical measurement techniques. The good correlation obtained with physical analysis and "classic" capacitance-voltage measurements shows the suitability of in-line measurement techniques for a first qualitative evaluation of ultrathin dielectric films.
{"title":"In-line electrical characterization of ultrathin gate dielectric films","authors":"F. Cubaynes, S. Passefort, K. Eason, Xiafang Zhang, L. Date, D. Pique, T. Conard, A. Rothschild, M. Schaekers","doi":"10.1109/ASMC.2002.1001563","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001563","url":null,"abstract":"In this paper, in-line measurements of ultrathin gate dielectrics are reported. Various plasma nitrided oxides down to 1.5 nm EOT have been studied using in-line optical and non-contact electrical measurement techniques. The good correlation obtained with physical analysis and \"classic\" capacitance-voltage measurements shows the suitability of in-line measurement techniques for a first qualitative evaluation of ultrathin dielectric films.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78495188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001617
A. Busnaina, Hong Lin
As semiconductor device feature size shrinks to 100 nm and smaller, the removal of nano-scale defects presents a tremendous challenge to the industry. There is a need to understand the particle removal mechanisms and recognize their advantages and limitations. In this paper, a particle removal model is modified to be able to consider soft particle deformation. The effect of decreasing particle size down to the nano-scale and its effect on the practical use of present techniques in the future is discussed. The way in which the megasonic-cleaning technique works to remove nano-scale particles from flat and structured surfaces is presented.
{"title":"Physical removal of nano-scale defects from surfaces","authors":"A. Busnaina, Hong Lin","doi":"10.1109/ASMC.2002.1001617","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001617","url":null,"abstract":"As semiconductor device feature size shrinks to 100 nm and smaller, the removal of nano-scale defects presents a tremendous challenge to the industry. There is a need to understand the particle removal mechanisms and recognize their advantages and limitations. In this paper, a particle removal model is modified to be able to consider soft particle deformation. The effect of decreasing particle size down to the nano-scale and its effect on the practical use of present techniques in the future is discussed. The way in which the megasonic-cleaning technique works to remove nano-scale particles from flat and structured surfaces is presented.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75242610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001628
R. Sandell, N. Pierce
Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.
{"title":"A hierarchical approach to cost analysis for next generation semiconductor processes","authors":"R. Sandell, N. Pierce","doi":"10.1109/ASMC.2002.1001628","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001628","url":null,"abstract":"Introduction of next generation semiconductor technologies gets progressively harder and more expensive with each node in the Semiconductor Industry Association (SIA) roadmap. True to tradition, the 0.1-micron node promises to provide a new set of processing complexities and significant capital investment as well as associated manufacturing costs. We have developed a methodology to analyze different process and equipment alternatives, in order to ultimately reduce the capital investment and overall manufacturing cost of wafers through this process. This approach is hierarchical in nature; in other words, it first aids with analysis of alternatives at a process step level and then these results are incorporated in the analysis of the total wafer and die cost at the macro process flow level. A Visual Basic based tool has been developed to enable this analysis.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85975206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001597
K.M. Lewis, C. Daigle, P. Allard, D. Tucker
Higher yield may be achieving through tighter control over transistor speed. At National, speed is measured by testing the critical parameter: saturation current (Idsat). A key variable controlling Idsat turned out to be the spacer etch. Across wafer etch uniformity was substantial enough to span over 60% of the Idsat spec range. This left little room for wafer-to-wafer or lot-to-lot variation. To improve the spacer etch, gas flows and power setting were optimizes through a series of designed experiments. Ultimately, across wafer spacer etch uniformity improved approximately 50%, which improved across wafer Idsat uniformity by approximately 33%.
{"title":"Optimization of oxide spacer etch process for 0.35 um CMOS transistor","authors":"K.M. Lewis, C. Daigle, P. Allard, D. Tucker","doi":"10.1109/ASMC.2002.1001597","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001597","url":null,"abstract":"Higher yield may be achieving through tighter control over transistor speed. At National, speed is measured by testing the critical parameter: saturation current (Idsat). A key variable controlling Idsat turned out to be the spacer etch. Across wafer etch uniformity was substantial enough to span over 60% of the Idsat spec range. This left little room for wafer-to-wafer or lot-to-lot variation. To improve the spacer etch, gas flows and power setting were optimizes through a series of designed experiments. Ultimately, across wafer spacer etch uniformity improved approximately 50%, which improved across wafer Idsat uniformity by approximately 33%.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84447528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001568
Y. Gotkis, D. Wei, R. Kistler
Two major conceptual CMP approaches, namely flexible polishing surface (utilized in linear belt CMP) and rigid polishing surface (hard platen rotary and orbital CMP) concepts are compared with regard to process stability, uniformity, planarization efficiency and other performance features. A new CMP characteristic, Normalized Removal Work, the amount of wafer layer material removed by a unit of active pad area (NRW=(Thickness removed)/(Active pad area), [A/sq. inch]), is used to analyze and compare the concepts. The NRW shows how much of the removed material is transferred and redeposited over a unit of pad area. It influences all aspects of the CMP process. Low NRW is good for CMP, high NRW is bad for CMP.
{"title":"Flexible polishing surface (FPS) vs rigid polishing surface (RPS) in CMP: pros and cons","authors":"Y. Gotkis, D. Wei, R. Kistler","doi":"10.1109/ASMC.2002.1001568","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001568","url":null,"abstract":"Two major conceptual CMP approaches, namely flexible polishing surface (utilized in linear belt CMP) and rigid polishing surface (hard platen rotary and orbital CMP) concepts are compared with regard to process stability, uniformity, planarization efficiency and other performance features. A new CMP characteristic, Normalized Removal Work, the amount of wafer layer material removed by a unit of active pad area (NRW=(Thickness removed)/(Active pad area), [A/sq. inch]), is used to analyze and compare the concepts. The NRW shows how much of the removed material is transferred and redeposited over a unit of pad area. It influences all aspects of the CMP process. Low NRW is good for CMP, high NRW is bad for CMP.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84894659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001613
D. Potts, T. Luk
Designers and test engineers are increasingly being challenged to introduce new high performance products within ever tightening tolerance windows. Traditional production test solutions may not be able to deliver the required accuracy to guarantee performance by test without additional and often prohibitive investments in extreme high-end test systems. In order to maintain a reasonable cost of manufacturing, it is not sufficient that these parts be designed for manufacturability-they must be guaranteed by design. To be considered guaranteed by design, one needs to have the utmost confidence in their design for manufacturability system and particularly in the accuracy of their simulations. This paper describes multivariate analysis techniques, leveraging electrical test data on the process level, to accurately model the statistical variation of the process as well as provide the means for evaluating where any given ET sample falls within that distribution for validating simulations against actual measured performance data. A case study drawn from a recent product introduction in a 0.35 /spl mu/m CMOS technology is used for demonstration.
{"title":"Beyond DFM: when manufacturability has to be guaranteed by design","authors":"D. Potts, T. Luk","doi":"10.1109/ASMC.2002.1001613","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001613","url":null,"abstract":"Designers and test engineers are increasingly being challenged to introduce new high performance products within ever tightening tolerance windows. Traditional production test solutions may not be able to deliver the required accuracy to guarantee performance by test without additional and often prohibitive investments in extreme high-end test systems. In order to maintain a reasonable cost of manufacturing, it is not sufficient that these parts be designed for manufacturability-they must be guaranteed by design. To be considered guaranteed by design, one needs to have the utmost confidence in their design for manufacturability system and particularly in the accuracy of their simulations. This paper describes multivariate analysis techniques, leveraging electrical test data on the process level, to accurately model the statistical variation of the process as well as provide the means for evaluating where any given ET sample falls within that distribution for validating simulations against actual measured performance data. A case study drawn from a recent product introduction in a 0.35 /spl mu/m CMOS technology is used for demonstration.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82016031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001616
H. Melzner
This paper presents a yield analysis technique based on test fail counts, as these are the most comprehensive and fundamental yield data available. Obviously, this requires the analysis of large volumes of data. Using powerful statistical techniques, such as Principal Component Analysis (PCA) and Multiple Linear Regression (MLR), efficient data reduction is achieved. A basic concept for the modeling of both defect related and parametric fails is presented. Based on a real life examples, means, variances, and covariances of test fail counts are analyzed. As covariance turns out to play a significant role, it is further analyzed using PCA to work out major independent sources of variation. MLR is then applied to partition total yield loss, resulting in the complete representation of actual yield data by just a few relevant patterns. Identification of physical root causes is consequently greatly simplified and accelerated, leading to fast problem solving and yield improvement.
{"title":"Statistical modeling and analysis of wafer test fail counts","authors":"H. Melzner","doi":"10.1109/ASMC.2002.1001616","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001616","url":null,"abstract":"This paper presents a yield analysis technique based on test fail counts, as these are the most comprehensive and fundamental yield data available. Obviously, this requires the analysis of large volumes of data. Using powerful statistical techniques, such as Principal Component Analysis (PCA) and Multiple Linear Regression (MLR), efficient data reduction is achieved. A basic concept for the modeling of both defect related and parametric fails is presented. Based on a real life examples, means, variances, and covariances of test fail counts are analyzed. As covariance turns out to play a significant role, it is further analyzed using PCA to work out major independent sources of variation. MLR is then applied to partition total yield loss, resulting in the complete representation of actual yield data by just a few relevant patterns. Identification of physical root causes is consequently greatly simplified and accelerated, leading to fast problem solving and yield improvement.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73732354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001586
Weidong Yang, R. Lowe-Webb, R. Korlahalli, V. Zhuang, H. Sasano, Wei Liu, D. Mui
Optical critical dimension metrology (OCD), an optical-wavelength light-diffraction technique, is currently undergoing an industry-wide evaluation as a fast, accurate, and non-destructive sub-100 nm line-width monitor. The spectroscopic, zeroth-order diffraction signature obtained from a printed diffraction grating allows extraction of structural information, such as linewidth, sidewall angle, and profile characteristics. The OCD spectrometer is compact and designed for integration into etch tools and lithography tracks. Effective process monitoring requires detailed understanding of the correlation between CD-SEM and OCD measurements. Correlation between the OCD technique and CD-SEM is investigated in this paper by measuring photo-resist gratings on a polysilicon gate film stack. The scatter in the correlation plot is shown to reduce significantly when several CD-SEM measurements are averaged from a single grating. A positive offset in the correlation is observed and a mechanism is proposed to account for the discrepancy.
{"title":"Line-profile and critical dimension measurements using a normal incidence optical metrology system","authors":"Weidong Yang, R. Lowe-Webb, R. Korlahalli, V. Zhuang, H. Sasano, Wei Liu, D. Mui","doi":"10.1109/ASMC.2002.1001586","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001586","url":null,"abstract":"Optical critical dimension metrology (OCD), an optical-wavelength light-diffraction technique, is currently undergoing an industry-wide evaluation as a fast, accurate, and non-destructive sub-100 nm line-width monitor. The spectroscopic, zeroth-order diffraction signature obtained from a printed diffraction grating allows extraction of structural information, such as linewidth, sidewall angle, and profile characteristics. The OCD spectrometer is compact and designed for integration into etch tools and lithography tracks. Effective process monitoring requires detailed understanding of the correlation between CD-SEM and OCD measurements. Correlation between the OCD technique and CD-SEM is investigated in this paper by measuring photo-resist gratings on a polysilicon gate film stack. The scatter in the correlation plot is shown to reduce significantly when several CD-SEM measurements are averaged from a single grating. A positive offset in the correlation is observed and a mechanism is proposed to account for the discrepancy.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90715847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001575
N. Tandon, G. Baweja
The complex semiconductor fabrication process needs to be optimized quickly to increase process yield and efficiency in fab operations. The Design of Experiments (DOE) technique is frequently applied in semiconductor domain by separating a wafer lot into wafer splits, and studying the effects of varying process parameters in relation to a baseline split across diffusion, photo, etch and other fabrication tools. An automated solution implemented at Kilby Center (KFAB) of Texas Instruments to capture and store the lot split DOE data for analysis, which satisfies the requirements of data volume, accuracy, and accessibility, is presented. Guidelines on how lot splits are defined consistently (the "rule set"), design and implementation of the system infrastructure components, and system's applications are included.
{"title":"Automated system infrastructure to facilitate design of experiments (DOE) data analysis","authors":"N. Tandon, G. Baweja","doi":"10.1109/ASMC.2002.1001575","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001575","url":null,"abstract":"The complex semiconductor fabrication process needs to be optimized quickly to increase process yield and efficiency in fab operations. The Design of Experiments (DOE) technique is frequently applied in semiconductor domain by separating a wafer lot into wafer splits, and studying the effects of varying process parameters in relation to a baseline split across diffusion, photo, etch and other fabrication tools. An automated solution implemented at Kilby Center (KFAB) of Texas Instruments to capture and store the lot split DOE data for analysis, which satisfies the requirements of data volume, accuracy, and accessibility, is presented. Guidelines on how lot splits are defined consistently (the \"rule set\"), design and implementation of the system infrastructure components, and system's applications are included.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78576981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ASMC.2002.1001604
G. Kong
ULSI semiconductor processing today involves hundreds of process steps through various semiconductor processing tools. Any tool excursion could lead to serious and costly yield problems. Tool commonality among bad lots is a proven technique to identify the root cause of the problem. As the complexity of process and the number of process steps increase, it is a very challenging task to pin point which tool is the source of problem and at which process step it occurs. Taking advantage of electronic lot tracking systems, systematic tool commonality analysis is capable of effectively identifying the problem source. The critical elements of successful tool commonality analysis are discussed and summarized in this paper, including sample size selection, raw data classification, statistical analysis, time series and analysis of tools with multiple entry points within the same process flow. Several pitfalls of the analysis are identified and discussed. This analysis is successfully applied on a yield enhancement effort in an advanced volume manufacturing fab.
{"title":"Tool commonality analysis for yield enhancement","authors":"G. Kong","doi":"10.1109/ASMC.2002.1001604","DOIUrl":"https://doi.org/10.1109/ASMC.2002.1001604","url":null,"abstract":"ULSI semiconductor processing today involves hundreds of process steps through various semiconductor processing tools. Any tool excursion could lead to serious and costly yield problems. Tool commonality among bad lots is a proven technique to identify the root cause of the problem. As the complexity of process and the number of process steps increase, it is a very challenging task to pin point which tool is the source of problem and at which process step it occurs. Taking advantage of electronic lot tracking systems, systematic tool commonality analysis is capable of effectively identifying the problem source. The critical elements of successful tool commonality analysis are discussed and summarized in this paper, including sample size selection, raw data classification, statistical analysis, time series and analysis of tools with multiple entry points within the same process flow. Several pitfalls of the analysis are identified and discussed. This analysis is successfully applied on a yield enhancement effort in an advanced volume manufacturing fab.","PeriodicalId":64779,"journal":{"name":"半导体技术","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90998351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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