Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803887
Y. Jiang, Dong Wang, P. K. Chan
This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 μA. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.
{"title":"A sub-1V low dropout regulator with improved transient performance for low power digital systems","authors":"Y. Jiang, Dong Wang, P. K. Chan","doi":"10.1109/APCCAS.2016.7803887","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803887","url":null,"abstract":"This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 μA. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77049124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804029
I. Kang, Jun Young Hwang, B. Bae
The fingerprint pixel sensor array was investigated for the application to the mobile phone. For the fingerprint sensing high resolution pixel array is necessary. Therefore, the readout voltage dependence on the resistance of the wires was investigated after composing 450th pixel array. The readout voltage was investigated for the ridge contact and valley contact. The simulated results show that the transparent electrode wire can be applied for the fingerprint pixel sensor array.
{"title":"Fingerprint pixel sensor array on a display","authors":"I. Kang, Jun Young Hwang, B. Bae","doi":"10.1109/APCCAS.2016.7804029","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804029","url":null,"abstract":"The fingerprint pixel sensor array was investigated for the application to the mobile phone. For the fingerprint sensing high resolution pixel array is necessary. Therefore, the readout voltage dependence on the resistance of the wires was investigated after composing 450th pixel array. The readout voltage was investigated for the ridge contact and valley contact. The simulated results show that the transparent electrode wire can be applied for the fingerprint pixel sensor array.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86316901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803969
Wei Mao, Yongfu Li, C. Heng, Y. Lian
To design high-resolution and high-speed current-steering digital-to-analog converter (DAC), both amplitude and timing mismatches should be minimized. In this paper, a dynamic mapping method based on the combination of magic-square-mapping (MSM) and random-segment-selection (RSS) is proposed to improve the performance of DAC. A design example of 12-bit 500-MS/s current-steering DAC is used to illustrate the advantages of the proposed dynamic mapping method. The design is verified by the Monte Carlo simulation, which attains more than 90dB SFDR across the Nyquist bandwidth.
为了设计高分辨率和高速的电流转向数模转换器(DAC)，幅度和时序失配都应该最小化。为了提高DAC的性能，本文提出了一种基于魔方映射(MSM)和随机段选择(RSS)相结合的动态映射方法。通过一个12位500 ms /s电流转向DAC的设计实例，说明了所提出的动态映射方法的优点。通过蒙特卡洛仿真验证了该设计，在奈奎斯特带宽上实现了超过90dB的SFDR。
{"title":"Dynamic mapping method for static and dynamic performance improvement on current-steering digital-to-analog converter","authors":"Wei Mao, Yongfu Li, C. Heng, Y. Lian","doi":"10.1109/APCCAS.2016.7803969","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803969","url":null,"abstract":"To design high-resolution and high-speed current-steering digital-to-analog converter (DAC), both amplitude and timing mismatches should be minimized. In this paper, a dynamic mapping method based on the combination of magic-square-mapping (MSM) and random-segment-selection (RSS) is proposed to improve the performance of DAC. A design example of 12-bit 500-MS/s current-steering DAC is used to illustrate the advantages of the proposed dynamic mapping method. The design is verified by the Monte Carlo simulation, which attains more than 90dB SFDR across the Nyquist bandwidth.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84759281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803925
E. Ogawa, Yosuke Sugiura, T. Shimamura
In this paper, we propose a new method for mitigating narrowband interference in Ultra-WideBand (UWB) communication systems based on Orthogonal Frequency Division Multiplexing (OFDM). Spreading data symbols to some subcarriers, the interference is effectively mitigated. However, the range to be spread for the interference is limited in conventional methods. In the proposed method, we widen more the range of the interference spread by applying symbol interleaving and deinterleaving techniques. We can obtain better Bit Error Rate (BER) performance with the proposed method. Combining the proposed method with spectral shaping, a further improved BER performance is obtained.
{"title":"Narrowband interference suppression with symbol interleaving for UWB communication systems","authors":"E. Ogawa, Yosuke Sugiura, T. Shimamura","doi":"10.1109/APCCAS.2016.7803925","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803925","url":null,"abstract":"In this paper, we propose a new method for mitigating narrowband interference in Ultra-WideBand (UWB) communication systems based on Orthogonal Frequency Division Multiplexing (OFDM). Spreading data symbols to some subcarriers, the interference is effectively mitigated. However, the range to be spread for the interference is limited in conventional methods. In the proposed method, we widen more the range of the interference spread by applying symbol interleaving and deinterleaving techniques. We can obtain better Bit Error Rate (BER) performance with the proposed method. Combining the proposed method with spectral shaping, a further improved BER performance is obtained.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82667623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803903
Chundong Wu, W. Goh, Wei Mao, Lei Wang, Yat-Hei Lam, Alan Chang, Y. Lian
A full range current sensor based on self-bias structure for buck regulator is presented in this paper. The proposed full range current sensor can sense current from both the high side and low side switches of the power regulator within the same switching cycle with input current varying from 50 mA to 500 mA. It has higher than 95% sensing accuracy while consuming less than 1% of the total input power. All the simulation results are based on 0.18μm CMOS process.
{"title":"A self biased full range current sensor for buck regulator","authors":"Chundong Wu, W. Goh, Wei Mao, Lei Wang, Yat-Hei Lam, Alan Chang, Y. Lian","doi":"10.1109/APCCAS.2016.7803903","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803903","url":null,"abstract":"A full range current sensor based on self-bias structure for buck regulator is presented in this paper. The proposed full range current sensor can sense current from both the high side and low side switches of the power regulator within the same switching cycle with input current varying from 50 mA to 500 mA. It has higher than 95% sensing accuracy while consuming less than 1% of the total input power. All the simulation results are based on 0.18μm CMOS process.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84359909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803992
M. Delgado-Restituto, Manuel Carrasco-Robles, R. Fiorelli, A. Arteaga, Á. Rodríguez-Vázquez
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.
{"title":"A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications","authors":"M. Delgado-Restituto, Manuel Carrasco-Robles, R. Fiorelli, A. Arteaga, Á. Rodríguez-Vázquez","doi":"10.1109/APCCAS.2016.7803992","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803992","url":null,"abstract":"This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain comparator which includes an offset cancellation mechanism. The power dissipated by the ADC is 76.2nW at 4kS/s and achieves 9.5 ENOB.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87134344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803986
Huyen Thi Pham, Hanho Lee
This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.
{"title":"Low latency check node unit architecture for nonbinary LDPC decoding","authors":"Huyen Thi Pham, Hanho Lee","doi":"10.1109/APCCAS.2016.7803986","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803986","url":null,"abstract":"This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86470906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803996
L. Ke, J. Wang, Xi-Juan Zhao, Fan Liang
Scale invariant feature transform(SIFT) is an algorithm to extract distinctive and invariant features from images to achieve reliable object matching between different images in variant scales and rotations. However, SIFT's huge computation impedes its real-time implementation. In this paper, a Fast-Gaussian SIFT(FG-SIFT) is proposed. Keypoint detection is optimized in FG-SIFT. SIFT's 2-D difference of Gaussian(DoG) in Gaussian Scale-Space(GSS) is separated into two 1-D DoG in x and y dimensions, and the level of scales in DoG pyramid is also reduced. The experiment shows that FG-SIFT reduces the computational complexity about 95% in GSS construction, also increases the accuracy of keypoint detection. Subsequently, the accuracy of generated features is increased 162%, and the accuracy of matched features is increased 8%. Apart from optimization in algorithm level, a hardware architecture of FG-SIFT's keypoint detection module is proposed. With a parallel architectural incorporating a five-stage pipeline, the execution time of keypoint detection is only 1.42ms@Xilinx Virtex5. Compared to conventional works, the speed is 21% faster than the fastest solution [9](ASIC), and hardware resources are 70% less than the most resources saved solutions [5] [6](Xilinx Virtex5).
{"title":"Fast-Gaussian SIFT and its hardware architecture for keypoint detection","authors":"L. Ke, J. Wang, Xi-Juan Zhao, Fan Liang","doi":"10.1109/APCCAS.2016.7803996","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803996","url":null,"abstract":"Scale invariant feature transform(SIFT) is an algorithm to extract distinctive and invariant features from images to achieve reliable object matching between different images in variant scales and rotations. However, SIFT's huge computation impedes its real-time implementation. In this paper, a Fast-Gaussian SIFT(FG-SIFT) is proposed. Keypoint detection is optimized in FG-SIFT. SIFT's 2-D difference of Gaussian(DoG) in Gaussian Scale-Space(GSS) is separated into two 1-D DoG in x and y dimensions, and the level of scales in DoG pyramid is also reduced. The experiment shows that FG-SIFT reduces the computational complexity about 95% in GSS construction, also increases the accuracy of keypoint detection. Subsequently, the accuracy of generated features is increased 162%, and the accuracy of matched features is increased 8%. Apart from optimization in algorithm level, a hardware architecture of FG-SIFT's keypoint detection module is proposed. With a parallel architectural incorporating a five-stage pipeline, the execution time of keypoint detection is only 1.42ms@Xilinx Virtex5. Compared to conventional works, the speed is 21% faster than the fastest solution [9](ASIC), and hardware resources are 70% less than the most resources saved solutions [5] [6](Xilinx Virtex5).","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80509923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804052
Sangwoo Han, Hyeokjun Seo, Byoung Jin Kim, Eui-Young Chung
Modern processor and memory have significant performance gap that incurs memory-wall phenomenon causing overall system performance degradation. Recently, PIM came out as one of solutions to overcome memory-wall phenomenon as well as increasing system performance. This paper studies how to implement functions within PIM logic for some broadly used applications. Our experiments are based on gem5 simulator. The experimental results show that some of functions are more efficient with PIM and their efficiency depends on the data size.
{"title":"PIM architecture exploration for HMC","authors":"Sangwoo Han, Hyeokjun Seo, Byoung Jin Kim, Eui-Young Chung","doi":"10.1109/APCCAS.2016.7804052","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804052","url":null,"abstract":"Modern processor and memory have significant performance gap that incurs memory-wall phenomenon causing overall system performance degradation. Recently, PIM came out as one of solutions to overcome memory-wall phenomenon as well as increasing system performance. This paper studies how to implement functions within PIM logic for some broadly used applications. Our experiments are based on gem5 simulator. The experimental results show that some of functions are more efficient with PIM and their efficiency depends on the data size.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77693664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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