Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803989
Junbo Shim, Min-Kyu Kim, Seongkwan Hong, O. Kwon
We propose a low-power single-ended 11-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors. The proposed SA-ADC uses a supply voltage of 1 V instead of 2 V for a 2 V input voltage range in order to reduce power consumption. The proposed ADC reduces the conversion time and area by sampling the input signal only twice and converting it to the most significant bit (MSB) and lower 10-bit without any additional analog circuit. A test chip with the proposed SA-ADC was fabricated using a 0.18 μm CMOS process technology. The measurement results show that the total power consumption of the proposed SA-ADC is 9.0 μW. The static and dynamic power consumptions using a 1 V supply voltage are reduced by 54% and 76%, respectively, compared with those using a 2 V supply voltage. In addition, the proposed SA-ADC achieves a short conversion time of 6.5 μs and occupies a small area of 320 μm × 270 μm. The measured DNL and INL are −0.53/+0.57 LSB and −0.91/+0.71 LSB, respectively.
{"title":"A low-power single-ended 11-bit SA-ADC with 1 V supply voltage and 2 V input voltage range for CMOS image sensors","authors":"Junbo Shim, Min-Kyu Kim, Seongkwan Hong, O. Kwon","doi":"10.1109/APCCAS.2016.7803989","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803989","url":null,"abstract":"We propose a low-power single-ended 11-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors. The proposed SA-ADC uses a supply voltage of 1 V instead of 2 V for a 2 V input voltage range in order to reduce power consumption. The proposed ADC reduces the conversion time and area by sampling the input signal only twice and converting it to the most significant bit (MSB) and lower 10-bit without any additional analog circuit. A test chip with the proposed SA-ADC was fabricated using a 0.18 μm CMOS process technology. The measurement results show that the total power consumption of the proposed SA-ADC is 9.0 μW. The static and dynamic power consumptions using a 1 V supply voltage are reduced by 54% and 76%, respectively, compared with those using a 2 V supply voltage. In addition, the proposed SA-ADC achieves a short conversion time of 6.5 μs and occupies a small area of 320 μm × 270 μm. The measured DNL and INL are −0.53/+0.57 LSB and −0.91/+0.71 LSB, respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"135 1","pages":"410-413"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90787124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803885
Huei-Shiuan Tang, C. Yang, Chih-Wei Liu, Chia-Cheng Chien
This paper presents a low-power and real-time noise reduction (NR) algorithm using 18-band 1/3-octave quasi-ANSI filter bank for binaural hearing aids. With aids of binaural cues and minima controlled recursive average (MCRA) approach, the proposed NR algorithm consists of a directional mask and an estimated mask. The directional mask exploits the interaural time difference (ITD) together with the interaural level difference (ILD) of two input sources to attenuate the lateral noise, while the estimated mask is used to further reduce the background noise and the coherence noise. Investigated by the circumstances with the −3 dB, 0 dB, and 3 dB, respectively, cocktail-party effect, the simulation results show that the proposed binaural NR algorithm gains an average of approximately 5.07 dB SNR improvement. Moreover, the speech intelligibility index (SII) performance is superior, comparing that with the state-of-the-art NR algorithms for hearing aids. The proposed binaural NR algorithm has been implemented in TSMC 90 nm CMOS high-VT technology. The chip design is operated by 288 KHz and consumes approximately 121.6 μW (@1 V). The chip design can be operated by 0.6 V for real-time processing 24 kHz audio. The simulated power consumption is approximately 64.52 μW for binaural hearing aids.
{"title":"Binaural-cue-based noise reduction using multirate quasi-ANSI filter bank for hearing aids","authors":"Huei-Shiuan Tang, C. Yang, Chih-Wei Liu, Chia-Cheng Chien","doi":"10.1109/APCCAS.2016.7803885","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803885","url":null,"abstract":"This paper presents a low-power and real-time noise reduction (NR) algorithm using 18-band 1/3-octave quasi-ANSI filter bank for binaural hearing aids. With aids of binaural cues and minima controlled recursive average (MCRA) approach, the proposed NR algorithm consists of a directional mask and an estimated mask. The directional mask exploits the interaural time difference (ITD) together with the interaural level difference (ILD) of two input sources to attenuate the lateral noise, while the estimated mask is used to further reduce the background noise and the coherence noise. Investigated by the circumstances with the −3 dB, 0 dB, and 3 dB, respectively, cocktail-party effect, the simulation results show that the proposed binaural NR algorithm gains an average of approximately 5.07 dB SNR improvement. Moreover, the speech intelligibility index (SII) performance is superior, comparing that with the state-of-the-art NR algorithms for hearing aids. The proposed binaural NR algorithm has been implemented in TSMC 90 nm CMOS high-VT technology. The chip design is operated by 288 KHz and consumes approximately 121.6 μW (@1 V). The chip design can be operated by 0.6 V for real-time processing 24 kHz audio. The simulated power consumption is approximately 64.52 μW for binaural hearing aids.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"28 1","pages":"21-24"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75722434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803947
C. Sawigun, P. Pawarangkoon
This paper presents a concept of using the flipped voltage follower as a 2nd-order lowpass filter. Combining two capacitors with the well-known two-transistor flipped voltage follower circuit, a single-branch transistorized gm-C filter, able to function from a low supply voltage, is obtained. Besides, the proposed filter can be configured as both single-ended and differential forms. Circuit simulation using 0.35-μm CMOS process shows that, to obtain a 100-Hz cutoff frequency with a 52.2-dB dynamic range, total capacitance of 36 pF and power consumption of 0.36 nW are required for the differential filter that operates in subthreshold region from a supply voltage of 0.6 V. Compared with the previously reported designs in the category of low-power biomedical filters, this proposed filter is the most power-efficient and operates from the lowest level of supply voltage.
{"title":"0.6-V, Sub-nW, second-order lowpass filters using flipped voltage followers","authors":"C. Sawigun, P. Pawarangkoon","doi":"10.1109/APCCAS.2016.7803947","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803947","url":null,"abstract":"This paper presents a concept of using the flipped voltage follower as a 2nd-order lowpass filter. Combining two capacitors with the well-known two-transistor flipped voltage follower circuit, a single-branch transistorized gm-C filter, able to function from a low supply voltage, is obtained. Besides, the proposed filter can be configured as both single-ended and differential forms. Circuit simulation using 0.35-μm CMOS process shows that, to obtain a 100-Hz cutoff frequency with a 52.2-dB dynamic range, total capacitance of 36 pF and power consumption of 0.36 nW are required for the differential filter that operates in subthreshold region from a supply voltage of 0.6 V. Compared with the previously reported designs in the category of low-power biomedical filters, this proposed filter is the most power-efficient and operates from the lowest level of supply voltage.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"16 1","pages":"254-257"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80882645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803923
Gain Kim, Y. Leblebici
This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter-symbol interference (ISI) and to increase receiver (RX) timing margin. A single-sideband (SSB) modulation has also been employed for saving of required bandwidth per sub-channel, so as to minimize inter-channel interference (ICI). System-level simulation results show that the proposed TRX can easily transmit 20 Gb/s data stream over a lossy backplane channel that exhibits 28-dB attenuation at 10 GHz while requiring neither of continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE). By transmitting 3-to-5 Gb/s data stream over each of four sub-channels, at least 44% unit interval (UI) eye openings are achieved for all sub-channels when 20 Gb/s aggregate data is transmitted.
{"title":"Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links","authors":"Gain Kim, Y. Leblebici","doi":"10.1109/APCCAS.2016.7803923","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803923","url":null,"abstract":"This paper presents a serial link transceiver (TRX) architecture that enables high-speed data transmission over a lossy backplane channel without the presence of equalization circuits. The proposed architecture employs multi-tone signaling to reduce inter-symbol interference (ISI) and to increase receiver (RX) timing margin. A single-sideband (SSB) modulation has also been employed for saving of required bandwidth per sub-channel, so as to minimize inter-channel interference (ICI). System-level simulation results show that the proposed TRX can easily transmit 20 Gb/s data stream over a lossy backplane channel that exhibits 28-dB attenuation at 10 GHz while requiring neither of continuous-time linear equalizer (CTLE) and decision feedback equalizer (DFE). By transmitting 3-to-5 Gb/s data stream over each of four sub-channels, at least 44% unit interval (UI) eye openings are achieved for all sub-channels when 20 Gb/s aggregate data is transmitted.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"4 1","pages":"164-167"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76355607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804037
Jung Woo Shin, J. Oh, Sang Muk Lee, Seung Eun Lee
In this paper, we propose a controller for the Controller Area Network with Flexible Data-Rate (CAN FD), an automotive communication protocol that supports flexible data length. The CAN FD is suitable for in-vehicle communication networks that requires a high reliability and high data transmission rate among ECUs. Experimental results show that our controller receives data from virtual ECU through SPI and transmits the data to the CANFD bus, completing the communication successfully.
{"title":"Live demonstration: CAN FD controller for in-vehicle network","authors":"Jung Woo Shin, J. Oh, Sang Muk Lee, Seung Eun Lee","doi":"10.1109/APCCAS.2016.7804037","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804037","url":null,"abstract":"In this paper, we propose a controller for the Controller Area Network with Flexible Data-Rate (CAN FD), an automotive communication protocol that supports flexible data length. The CAN FD is suitable for in-vehicle communication networks that requires a high reliability and high data transmission rate among ECUs. Experimental results show that our controller receives data from virtual ECU through SPI and transmits the data to the CANFD bus, completing the communication successfully.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"42 1","pages":"748-749"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74134056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803966
Ki-Hyun Pyun, D. Kwon, W. Choi
A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.
{"title":"A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector","authors":"Ki-Hyun Pyun, D. Kwon, W. Choi","doi":"10.1109/APCCAS.2016.7803966","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803966","url":null,"abstract":"A new type of multi-rate clock and data recovery (CDR) circuit is realized that can operate at multiple data rates of 3.5, 7.0 and 14-Gb/s. A multi-mode rotational binary phase detector supports full-rate, half-rate and quarter-rate CDR operation with only one voltage-controlled oscillator. A prototype CDR circuit implemented in 65nm CMOS technology successfully demonstrates the multi-rate operation with energy efficiency of 0.64pJ/bit and chip size of 0.017mm2, both of which are much less than those of conventional multi-rate CDR circuits.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"9 1","pages":"327-329"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84164599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803973
Takahiro Yamamoto, Ittetsu Taniguchi, H. Tomiyama, S. Yamashita, Yuko Hara-Azumi
Approximate computing is considered as a promising approach to design of power-or area-efficient digital circuits. This paper proposes a systematic methodology for design and analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay and accuracy of the approximate multipliers.
{"title":"A systematic methodology for design and analysis of approximate array multipliers","authors":"Takahiro Yamamoto, Ittetsu Taniguchi, H. Tomiyama, S. Yamashita, Yuko Hara-Azumi","doi":"10.1109/APCCAS.2016.7803973","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803973","url":null,"abstract":"Approximate computing is considered as a promising approach to design of power-or area-efficient digital circuits. This paper proposes a systematic methodology for design and analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay and accuracy of the approximate multipliers.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"29 1","pages":"352-354"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90740148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803930
Ting-An Chang, Jung-Ping Kuo, J. Yang
Structured-light RGB-D cameras are commonly used to capture depth images, which convey the per-pixel depth information in a scene. However, these cameras often produce regions with missing pixels. The missing pixel regions, which refer to holes, will not contain any depth information for the depth image. This reason would lead the performance to degrade seriously in modern-day three-dimensional (3D) video applications. Therefore, how to effectively utilize image information and depth maps become more and more important. In this paper, we propose adaptive texture-similarity-based hole filling (ATSHF) and adaptive texture-similarity-based depth enhancement (ATSDE). The proposed system, which is used for the enhancement of depth maps, is achieved by suppressing the noise, filling holes and sharpening object edges simultaneously. Experimental results demonstrate that the proposed method provides a superior performance, especially around the object boundary. Beside, we compare with the other state-of-the-art methods about the image and the depth map enhancement.
{"title":"Efficient hole filling and depth enhancement based on texture image and depth map consistency","authors":"Ting-An Chang, Jung-Ping Kuo, J. Yang","doi":"10.1109/APCCAS.2016.7803930","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803930","url":null,"abstract":"Structured-light RGB-D cameras are commonly used to capture depth images, which convey the per-pixel depth information in a scene. However, these cameras often produce regions with missing pixels. The missing pixel regions, which refer to holes, will not contain any depth information for the depth image. This reason would lead the performance to degrade seriously in modern-day three-dimensional (3D) video applications. Therefore, how to effectively utilize image information and depth maps become more and more important. In this paper, we propose adaptive texture-similarity-based hole filling (ATSHF) and adaptive texture-similarity-based depth enhancement (ATSDE). The proposed system, which is used for the enhancement of depth maps, is achieved by suppressing the noise, filling holes and sharpening object edges simultaneously. Experimental results demonstrate that the proposed method provides a superior performance, especially around the object boundary. Beside, we compare with the other state-of-the-art methods about the image and the depth map enhancement.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"33 1","pages":"192-195"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91105623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7804028
Jong-Seok Kim, Jin-O. Yoon, B. Choi
A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.
{"title":"Low-power counter for column-parallel CMOS image sensors","authors":"Jong-Seok Kim, Jin-O. Yoon, B. Choi","doi":"10.1109/APCCAS.2016.7804028","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7804028","url":null,"abstract":"A low-power counter (LPC) for column-parallel CMOS image sensors (CISs) is presented. The proposed LPCs can reduce the number of switching events of D-flip-flop (DFF) in the counter by 50% compared to the traditional counter. The simulation results with 200 MHz of clock signal show that the power consumption of the traditional counter is 55.7 μW, and the proposed LPC is 27.9 μW.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"135 1","pages":"554-556"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88989995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/APCCAS.2016.7803915
Om. Prakash, Mohit Sharma, B. Anand, A. Saxena, S. Manhas, S. Maheshwaram
At deep nano-scale nodes Silicon Nanowire field effect transistor (SiNW FET) imparts best performance. However, analysis of SiNW FET based circuit design is lacking in existing literature. In this study, we design a standard cell library for advanced 10nm lateral SiNW FET technology in super threshold regime. For this, we create a Verilog-A compact model. Our compact Verilog-A model includes all the short channel effect as well as the geometrical dependent parasitics, which are crucial for short channel devices. The model is well calibrated with TCAD and reported fabricated data. The standard cell library developed comprise INVERTER, NAND, and NOR gate cells. Finally, we compared the standard cell performance to FinFET based standard cell. We found that the Si NW CMOS based standard cells have ∼3–4X, ∼2–3X, and 3X performance in terms of power dissipation, energy-delay product and power delay product respectively compared to FinFET based designs.
{"title":"Lateral silicon nanowire based standard cell design for higher performance","authors":"Om. Prakash, Mohit Sharma, B. Anand, A. Saxena, S. Manhas, S. Maheshwaram","doi":"10.1109/APCCAS.2016.7803915","DOIUrl":"https://doi.org/10.1109/APCCAS.2016.7803915","url":null,"abstract":"At deep nano-scale nodes Silicon Nanowire field effect transistor (SiNW FET) imparts best performance. However, analysis of SiNW FET based circuit design is lacking in existing literature. In this study, we design a standard cell library for advanced 10nm lateral SiNW FET technology in super threshold regime. For this, we create a Verilog-A compact model. Our compact Verilog-A model includes all the short channel effect as well as the geometrical dependent parasitics, which are crucial for short channel devices. The model is well calibrated with TCAD and reported fabricated data. The standard cell library developed comprise INVERTER, NAND, and NOR gate cells. Finally, we compared the standard cell performance to FinFET based standard cell. We found that the Si NW CMOS based standard cells have ∼3–4X, ∼2–3X, and 3X performance in terms of power dissipation, energy-delay product and power delay product respectively compared to FinFET based designs.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"45 1","pages":"135-138"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81241812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：