Shunsuke Tonouchi, E. Mizushima, Tomio Fukuda, Tomokazu Shimada, Yukio Nakamura, T. Iijima
The next generation communication system, which is called 5G, is coming. With the introduction of 5G, dielectric material with low dielectric constant (Dk) and low dissipation factor (Df) is required to reduce transmission loss. And, the substrate is also required to be thin with the performance of suppressing the package warpage. Therefore, the package substrate for 5G mobile device will be required to satisfy the low transmission loss and the small package warpage. Low coefficient of thermal expansion (CTE) is known to reduce package warpage, so the substrate material with low CTE is also required. In this research, the substrate material having low Dk and Df, and CTE has been developed. The base resin system consists of the polycyclic resin having the planer stack structure of aromatic ring. The strong intermolecular force between the stacks restricts the local movement of the resin system, which can contribute to the small CTE and the low Df. Besides, low or non-polarity component is a basic idea to design low Dk and Df resin system. In general, different polarity components have less compatibility each other. We have overcome the compatibility issue by introducing chemical co-crosslinking reaction modifying both the polycyclic and the low polarity components. Warpage behavior of the package was evaluated comparing with the conventional coreless thin substrate. The warpage value of the developed substrate material was 150 µm, smaller than that of the conventional substrate. Signal transmission property at 28 to 77 GHz was also evaluated. The loss values of the substrate at 28 and 77 GHz were 0.47 and 1.29 dB/cm, respectively. Those were smaller than the values of the conventional one.
{"title":"Organic Substrate Material with Low Transmission Loss and Effective in Suppressing Package Warpage for 5G Application","authors":"Shunsuke Tonouchi, E. Mizushima, Tomio Fukuda, Tomokazu Shimada, Yukio Nakamura, T. Iijima","doi":"10.1109/ECTC.2018.00012","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00012","url":null,"abstract":"The next generation communication system, which is called 5G, is coming. With the introduction of 5G, dielectric material with low dielectric constant (Dk) and low dissipation factor (Df) is required to reduce transmission loss. And, the substrate is also required to be thin with the performance of suppressing the package warpage. Therefore, the package substrate for 5G mobile device will be required to satisfy the low transmission loss and the small package warpage. Low coefficient of thermal expansion (CTE) is known to reduce package warpage, so the substrate material with low CTE is also required. In this research, the substrate material having low Dk and Df, and CTE has been developed. The base resin system consists of the polycyclic resin having the planer stack structure of aromatic ring. The strong intermolecular force between the stacks restricts the local movement of the resin system, which can contribute to the small CTE and the low Df. Besides, low or non-polarity component is a basic idea to design low Dk and Df resin system. In general, different polarity components have less compatibility each other. We have overcome the compatibility issue by introducing chemical co-crosslinking reaction modifying both the polycyclic and the low polarity components. Warpage behavior of the package was evaluated comparing with the conventional coreless thin substrate. The warpage value of the developed substrate material was 150 µm, smaller than that of the conventional substrate. Signal transmission property at 28 to 77 GHz was also evaluated. The loss values of the substrate at 28 and 77 GHz were 0.47 and 1.29 dB/cm, respectively. Those were smaller than the values of the conventional one.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"28-32"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84329599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sebastian Bengsch, M. Wurz, Maximilian Aue, Sascha de Wall
A new manufacturing technique for low cost sensor production was developed at the Institute of Micro Production Technology at the Leibniz University Hanover. The herein described manufacturing technique uses common injection molding processes to pre-structure thermoplastic polymers such as Polycarbonate, which can subsequently be used as a substrate to build up sensor structures. The sensor structures are generated by sputter deposition and a following chemical mechanical polishing step. The realized sensor structure can be manufactured neglecting any lithography processes and therefore eliminates expensive clean room technology. This work investigates and optimizes injection molding parameter using design of experiment methods. Following the parameter studies, a manufacturing process designed to realize a micro technologically fabricated injection mold inlay was performed, and the performance of an electroplated Ni based injection mold master form for sensor structure manufacturing evaluated. A temperature sensor on a thermoplastic substrate (polycarbonate) prototype was realized, which was able to prove the feasibility of the manufacturing technique and the robustness of polymers as a substrate material.
{"title":"Structuring Methods of Polymers for low Cost Sensor Manufacturing","authors":"Sebastian Bengsch, M. Wurz, Maximilian Aue, Sascha de Wall","doi":"10.1109/ECTC.2018.00213","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00213","url":null,"abstract":"A new manufacturing technique for low cost sensor production was developed at the Institute of Micro Production Technology at the Leibniz University Hanover. The herein described manufacturing technique uses common injection molding processes to pre-structure thermoplastic polymers such as Polycarbonate, which can subsequently be used as a substrate to build up sensor structures. The sensor structures are generated by sputter deposition and a following chemical mechanical polishing step. The realized sensor structure can be manufactured neglecting any lithography processes and therefore eliminates expensive clean room technology. This work investigates and optimizes injection molding parameter using design of experiment methods. Following the parameter studies, a manufacturing process designed to realize a micro technologically fabricated injection mold inlay was performed, and the performance of an electroplated Ni based injection mold master form for sensor structure manufacturing evaluated. A temperature sensor on a thermoplastic substrate (polycarbonate) prototype was realized, which was able to prove the feasibility of the manufacturing technique and the robustness of polymers as a substrate material.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"1396-1401"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82148308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Raid, S. Gallois-Garreignot, R. Estevez, V. Coutellier
We present a device that provides in-situ optical observations of interface delamination along a heterogeneous surface with various interface strengths, namely chips with "crack stops" in their perimeters. We adopt a four-point bending test in which a glass plate is used that allows for the optical tracking of the crack advances. Because the interface strength is heterogeneous, drops in the force-displacement curve are observed, corresponding to a non-uniform crack advance. This is confirmed with a 2D finite elements simulation of the four-point bending test; the heterogeneous interface being described with a cohesive model. Results show that the method is reproducible and is able to detect the crack front in a complex interconnect environment. The coupling between force-displacement curve and observations provide insight on the crack propagation sequence. Based on this, some assumptions have been drawn, even if further work investigation is necessary. However, this new experimental approach is seen as a promising method for future characterization of crack growth.
{"title":"Seal Rings Toughness Characterization by Numerical and Experimental Approaches","authors":"I. Raid, S. Gallois-Garreignot, R. Estevez, V. Coutellier","doi":"10.1109/ECTC.2018.00155","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00155","url":null,"abstract":"We present a device that provides in-situ optical observations of interface delamination along a heterogeneous surface with various interface strengths, namely chips with \"crack stops\" in their perimeters. We adopt a four-point bending test in which a glass plate is used that allows for the optical tracking of the crack advances. Because the interface strength is heterogeneous, drops in the force-displacement curve are observed, corresponding to a non-uniform crack advance. This is confirmed with a 2D finite elements simulation of the four-point bending test; the heterogeneous interface being described with a cohesive model. Results show that the method is reproducible and is able to detect the crack front in a complex interconnect environment. The coupling between force-displacement curve and observations provide insight on the crack propagation sequence. Based on this, some assumptions have been drawn, even if further work investigation is necessary. However, this new experimental approach is seen as a promising method for future characterization of crack growth.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"1010-1016"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82181057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fabian Schempp, M. Dressler, Daniel Kraetschmer, Friederike Loerke, J. Wilde
The reliability assessment of ball grid array (BGA) components on system level for automotive applications requires a detailed simulation model, which describes the warpage behavior over temperature very accurately, for a credible reliability assessment [1]. However, in the product development process, detailed models of these complex components are not always available for a numerical investigation due to various reasons, e.g. missing information about material properties or stack up. The work presented in this paper advances the state of the art in solder joint reliability assessment under thermomechanical load by introducing a new load based metric. This approach facilitates the process of ensuring the reliability of BGA type packages on system level by aiming to use the easier accessible and experimentally quantifiable displacements of BGA component and printed circuit board (PCB) over temperature. To develop this metric, in a first step the deformations of individual solder joints, due to displacements from BGA and PCB, are investigated. A parameter related to the deformation of the solder joints is introduced and then correlated with crack growth data from a passive temperature cycling test. By showing the correlation between the deformation related parameter and experimental crack growth data, the basis is established to further develop the method and use displacements, measured on top of component and PCB, for the correlation with cycles to failure. The accuracy of the new metric is assessed by comparison with results from the state of the art reliability assessment approach on the basis of strain based damage related parameters obtained by means of the finite element method.
{"title":"Introduction of a New Metric for the Solder Joint Reliability Assessment of BGA Packages on System Level","authors":"Fabian Schempp, M. Dressler, Daniel Kraetschmer, Friederike Loerke, J. Wilde","doi":"10.1109/ECTC.2018.00329","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00329","url":null,"abstract":"The reliability assessment of ball grid array (BGA) components on system level for automotive applications requires a detailed simulation model, which describes the warpage behavior over temperature very accurately, for a credible reliability assessment [1]. However, in the product development process, detailed models of these complex components are not always available for a numerical investigation due to various reasons, e.g. missing information about material properties or stack up. The work presented in this paper advances the state of the art in solder joint reliability assessment under thermomechanical load by introducing a new load based metric. This approach facilitates the process of ensuring the reliability of BGA type packages on system level by aiming to use the easier accessible and experimentally quantifiable displacements of BGA component and printed circuit board (PCB) over temperature. To develop this metric, in a first step the deformations of individual solder joints, due to displacements from BGA and PCB, are investigated. A parameter related to the deformation of the solder joints is introduced and then correlated with crack growth data from a passive temperature cycling test. By showing the correlation between the deformation related parameter and experimental crack growth data, the basis is established to further develop the method and use displacements, measured on top of component and PCB, for the correlation with cycles to failure. The accuracy of the new metric is assessed by comparison with results from the state of the art reliability assessment approach on the basis of strain based damage related parameters obtained by means of the finite element method.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"108 1","pages":"2192-2197"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79405091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Manoharan, C. Patel, S. Dunford, C. Morillo, P. McCluskey
Epoxy mold compounds can exhibit changes in material properties with aging at high temperature, that can significantly affect reliability of interconnects. This study focuses on characterizing elastic modulus, coefficient of thermal expansion and glass transition temperature for epoxy 'green' mold compounds, on un-aged and devices that were aged at maximum dwell temperature of 185°C. This study involves using commercial devices unlike other studies presented in literature where lab cured specimen were used. Characterization of mold compound on commercially available packages molded in production line gives valuable information but is challenging due to geometrical constraints. Hence, conventional techniques, such as DMA, cannot be used to obtain properties of mold compound in packaged devices. Thus, majority of the work is done with nanoindentation and thermomechanical analyzer (TMA). Additionally, the mechanism of aging due to oxidation is discussed and growth constant and activation energies for oxidized layer are provided.
{"title":"Aging Characteristics of Green Mold Compound for Use in Encapsulation of Microelectronic Devices","authors":"S. Manoharan, C. Patel, S. Dunford, C. Morillo, P. McCluskey","doi":"10.1109/ECTC.2018.00266","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00266","url":null,"abstract":"Epoxy mold compounds can exhibit changes in material properties with aging at high temperature, that can significantly affect reliability of interconnects. This study focuses on characterizing elastic modulus, coefficient of thermal expansion and glass transition temperature for epoxy 'green' mold compounds, on un-aged and devices that were aged at maximum dwell temperature of 185°C. This study involves using commercial devices unlike other studies presented in literature where lab cured specimen were used. Characterization of mold compound on commercially available packages molded in production line gives valuable information but is challenging due to geometrical constraints. Hence, conventional techniques, such as DMA, cannot be used to obtain properties of mold compound in packaged devices. Thus, majority of the work is done with nanoindentation and thermomechanical analyzer (TMA). Additionally, the mechanism of aging due to oxidation is discussed and growth constant and activation energies for oxidized layer are provided.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1768-1773"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79877363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Moreau Stéphane, N. Allouti, C. Ribiére, J. Charbonnier, D. Bouchu, J. Michel, N. Buffet, P. Chausse
Even if polymers are used for decades in electronics and microelectronics, one of the primary drawbacks is their susceptibility to moisture uptake. Moisture penetrating into polymers reduces their mechanical and electrical performances and consequently, moisture becomes a reliability issue for the RDL level. This paper presents results which highlight the need of choosing the right integration scheme in addition to the right polymer to ensure steady electrical performances of the Cu RDL level. The reliability studies using high temperature storages demonstrate that the main moisture diffusion path is through the polymer itself and the use of a bilayer (inorganic/organic) as passivation layer seems to be the best choice to minimize the moisture permeation. In addition, we have identify the failure modes, due to the electromigration phenomenon in the Cu RDL level, as being the grain boundaries and the Cu/SiN interface.
{"title":"Passivation Materials for a Reliable Fine Pitch RDL","authors":"Moreau Stéphane, N. Allouti, C. Ribiére, J. Charbonnier, D. Bouchu, J. Michel, N. Buffet, P. Chausse","doi":"10.1109/ECTC.2018.00240","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00240","url":null,"abstract":"Even if polymers are used for decades in electronics and microelectronics, one of the primary drawbacks is their susceptibility to moisture uptake. Moisture penetrating into polymers reduces their mechanical and electrical performances and consequently, moisture becomes a reliability issue for the RDL level. This paper presents results which highlight the need of choosing the right integration scheme in addition to the right polymer to ensure steady electrical performances of the Cu RDL level. The reliability studies using high temperature storages demonstrate that the main moisture diffusion path is through the polymer itself and the use of a bilayer (inorganic/organic) as passivation layer seems to be the best choice to minimize the moisture permeation. In addition, we have identify the failure modes, due to the electromigration phenomenon in the Cu RDL level, as being the grain boundaries and the Cu/SiN interface.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"1583-1592"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85481902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Miniaturization trend progresses continuously and enables an increasing integration level up to 3D system in package (3D-SiP). Thus, the structure of electronic packages is getting more and more complex and the material compositions often are heterogeneous mixtures of metals, polymers and ceramics. This causes challenging requirements for the investigation and reliability characterization of materials, interfaces, components and systems. The target positions are often buried or covered. Additionally the cover and housing materials are increasingly designed for harsh environment applications and so resistant against chemical attack. All these developments make the preparation for e.g. local access to perform electrical measurements or artefact free cross sectioning more and more complex. Focused ion beam preparation is limited in terms of ablation volume. Chemical decapping does not allow opening a small area very selectively and fails increasingly on the resistivity of the mold compounds against chemicals. Metallographic cross sectioning does not preserve the function of the system or can introduce artifacts which are limiting further investigations like element detection or thin film microstructure analyzes. Within all these difficulties the paper presents a new laser preparation tool for multi-purpose capabilities in failure diagnostics and reliability investigations. Several case studies show that the tool is usable for target and large area decapsulation of molding and protective gel coverage materials with no significant thermal impact. Also stacked die preparation for 3D package analyzes and pre-preparation for multi-position TEM lamellas are possible.
{"title":"A New, Efficient Method for Preparation of 3D Integrated Systems by Laser Techniques","authors":"R. Klengel, S. Klengel, G. Schusser, M. Krause","doi":"10.1109/ECTC.2018.00342","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00342","url":null,"abstract":"Miniaturization trend progresses continuously and enables an increasing integration level up to 3D system in package (3D-SiP). Thus, the structure of electronic packages is getting more and more complex and the material compositions often are heterogeneous mixtures of metals, polymers and ceramics. This causes challenging requirements for the investigation and reliability characterization of materials, interfaces, components and systems. The target positions are often buried or covered. Additionally the cover and housing materials are increasingly designed for harsh environment applications and so resistant against chemical attack. All these developments make the preparation for e.g. local access to perform electrical measurements or artefact free cross sectioning more and more complex. Focused ion beam preparation is limited in terms of ablation volume. Chemical decapping does not allow opening a small area very selectively and fails increasingly on the resistivity of the mold compounds against chemicals. Metallographic cross sectioning does not preserve the function of the system or can introduce artifacts which are limiting further investigations like element detection or thin film microstructure analyzes. Within all these difficulties the paper presents a new laser preparation tool for multi-purpose capabilities in failure diagnostics and reliability investigations. Several case studies show that the tool is usable for target and large area decapsulation of molding and protective gel coverage materials with no significant thermal impact. Also stacked die preparation for 3D package analyzes and pre-preparation for multi-position TEM lamellas are possible.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"87 5 1","pages":"2275-2279"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84026685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Chong, Hongyu Li, Ling Xie, S. Lim, Zhaohui Chen
Market is always looking for way to reduce the cost of package. Traditional way of protecting the fragile micro-bumps is by applying capillary underfill (CUF) to mitigate the issue of CTE mismatch between the die and the substrate. However, the use of CUF introduce additional assembly process on top of high material cost as compared to Moldable Underfill (MUF). In this paper, we explore the use of MUF for the 4-diue stack. MUF is very attractive as it combined the step of molding and underfilling into one single step in addition to the low material cost as compared to CUF. The reliability of MUF is much superior to CUF as shown in the simulation study. The simulation study indicates a drastic 1.65 times more fatigue life for MUF as compared to CUF. The 4 die stack is formed using conventional mass reflow process. The dies is stacked on top of each other on a bottom substrate wafer using conventional noclean flux. The whole substrate wafer with the 4 die stack is then send through a reflow oven to form the solder interconnect for all 4 die stacks. This approach is much prefer than individual thermo-compression process in terms of throughput and less thermal loading to the solder interconnects as no heat is applied to each die stacking process. We had demonstrated no void in the region between the solder bump after the MUF molding process.
{"title":"Process Development of 4-Die Stack Module Using Moldable Underfill","authors":"S. Chong, Hongyu Li, Ling Xie, S. Lim, Zhaohui Chen","doi":"10.1109/ECTC.2018.00347","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00347","url":null,"abstract":"Market is always looking for way to reduce the cost of package. Traditional way of protecting the fragile micro-bumps is by applying capillary underfill (CUF) to mitigate the issue of CTE mismatch between the die and the substrate. However, the use of CUF introduce additional assembly process on top of high material cost as compared to Moldable Underfill (MUF). In this paper, we explore the use of MUF for the 4-diue stack. MUF is very attractive as it combined the step of molding and underfilling into one single step in addition to the low material cost as compared to CUF. The reliability of MUF is much superior to CUF as shown in the simulation study. The simulation study indicates a drastic 1.65 times more fatigue life for MUF as compared to CUF. The 4 die stack is formed using conventional mass reflow process. The dies is stacked on top of each other on a bottom substrate wafer using conventional noclean flux. The whole substrate wafer with the 4 die stack is then send through a reflow oven to form the solder interconnect for all 4 die stacks. This approach is much prefer than individual thermo-compression process in terms of throughput and less thermal loading to the solder interconnects as no heat is applied to each die stacking process. We had demonstrated no void in the region between the solder bump after the MUF molding process.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"204 1","pages":"2307-2312"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80332739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Yamatsu, Kazuki Watanabe, Naoki Kanagawa, Takatoshi Ishikawa, Teppei Kojio
In this research, a combination of thermo-sonic bonding (TSB) process and non-conductive film (NCF) material was used to fabricate vertically stacked through silicon via (TSV) assemblies. TSB is particularly attractive TSV assembly process because it offers up to 10x throughput improvement when compared to conventional processes. By adjusting the properties (e.g. viscosity, and reaction time) of NCF, a 4-layer stacked assembly was fabricated without voids or delamination. Moreover, these parts exhibited no failures after 2,000 times thermal cycles test (-40ºC to 125ºC).
{"title":"3D Stacking Process with Thermo-Sonic Bonding Using Non-conductive Film","authors":"S. Yamatsu, Kazuki Watanabe, Naoki Kanagawa, Takatoshi Ishikawa, Teppei Kojio","doi":"10.1109/ECTC.2018.00307","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00307","url":null,"abstract":"In this research, a combination of thermo-sonic bonding (TSB) process and non-conductive film (NCF) material was used to fabricate vertically stacked through silicon via (TSV) assemblies. TSB is particularly attractive TSV assembly process because it offers up to 10x throughput improvement when compared to conventional processes. By adjusting the properties (e.g. viscosity, and reaction time) of NCF, a 4-layer stacked assembly was fabricated without voids or delamination. Moreover, these parts exhibited no failures after 2,000 times thermal cycles test (-40ºC to 125ºC).","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"2049-2054"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82337649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guang Yang, Yuze Yan, Zhuo Li, Chaowei Li, Yagang Yao
With the shrinkage of chip size and the increase of integration density, chip heat flux increases dramatically. Efficient heat dissipation becomes critical for the performance, reliability and service life of electronics. Therefore, advanced lateral heat spreader materials such as carbon allotropes and their derivatives are highly desirable in modern electronics. Graphene attracts great attention as a lateral heat spreader material due to its unique thermal transfer property (theoretical thermal conductivity ca. 5300 W m-1K-1) and its natural two-dimensional (2D) structure. However, an efficient method to accomplish large scale production and ordered assembly structures of graphene sheets is critical for real application in heat dissipation in electronics. Conventional production methods to produce graphene sheets such as filtration method, solvent evaporation method, chemical vapor deposition, electrostatic spray deposition etc. have some limitations–long production time, high energy consumption and great difficulties in controlling the sheet geometry, for instance. In this contribution, graphene sheets were fabricated by a wet-spinning method of graphene oxide (GO) solution followed by chemical reduction of GO to reduced graphene oxide (rGO). The wet-spinning method was able to produce graphene sheets in a high rate (~1.2m/min) and in different dimensions. Here sheets with different thickness (8µm and 16µm) are demonstrated. A series of characterizations are performed for the produced GO and rGO sheets including their Raman and infrared spectra, X-ray diffraction pattern, scanning microscopic pictures and atomic force microscopic pictures. These data show that the reduction is sufficient and the GO sheets are piled up parallel during the wet-spinning process, which is beneficial for the lateral heat transport. The rGO has an in-plane electrical conductivity ca. 6848.41 S/m and thermal conductivity ca. 1024.86 W m-1K-1. In addition, the film displayed excellent heat dissipation performance when attached on top of a light emitting diode (LED) light strip. The research results indicate our approach is facile and capable of fabricating scalable and controllable heat spreader materials with high performance.
随着芯片尺寸的缩小和集成密度的增大，芯片热流密度急剧增大。高效散热对电子产品的性能、可靠性和使用寿命至关重要。因此，先进的横向散热材料，如碳同素异形体及其衍生物，在现代电子领域是非常可取的。石墨烯作为一种横向导热材料，由于其独特的传热特性(理论导热系数约为5300 W m-1K-1)和其天然的二维(2D)结构而备受关注。然而，实现石墨烯片的大规模生产和有序组装结构的有效方法对于电子散热的实际应用至关重要。传统的石墨烯片材生产方法如过滤法、溶剂蒸发法、化学气相沉积法、静电喷雾沉积法等都存在生产时间长、能耗高、片材几何形状控制困难等局限性。在这项贡献中，石墨烯片是通过氧化石墨烯(GO)溶液的湿纺方法制备的，然后将GO化学还原为还原的氧化石墨烯(rGO)。湿纺法能够以高速率(~1.2m/min)生产不同尺寸的石墨烯片。这里展示了不同厚度(8µm和16µm)的薄片。对制备的氧化石墨烯和还原氧化石墨烯薄片进行了一系列表征，包括拉曼光谱和红外光谱、x射线衍射图、扫描显微图和原子力显微图。结果表明，湿纺过程中氧化石墨烯的还原充分，且氧化石墨烯片平行堆积，有利于横向热传递。rGO的面内电导率约为6848.41 S/m，导热系数约为1024.86 W m- 1k -1。此外，当将薄膜附着在发光二极管(LED)灯带的顶部时，该薄膜显示出优异的散热性能。研究结果表明，我们的方法简单，能够制造出可伸缩、可控的高性能散热材料。
{"title":"Wet-Spun Graphene Sheets as Flexible Heat Spreaders for Efficient Thermal Management","authors":"Guang Yang, Yuze Yan, Zhuo Li, Chaowei Li, Yagang Yao","doi":"10.1109/ECTC.2018.00265","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00265","url":null,"abstract":"With the shrinkage of chip size and the increase of integration density, chip heat flux increases dramatically. Efficient heat dissipation becomes critical for the performance, reliability and service life of electronics. Therefore, advanced lateral heat spreader materials such as carbon allotropes and their derivatives are highly desirable in modern electronics. Graphene attracts great attention as a lateral heat spreader material due to its unique thermal transfer property (theoretical thermal conductivity ca. 5300 W m-1K-1) and its natural two-dimensional (2D) structure. However, an efficient method to accomplish large scale production and ordered assembly structures of graphene sheets is critical for real application in heat dissipation in electronics. Conventional production methods to produce graphene sheets such as filtration method, solvent evaporation method, chemical vapor deposition, electrostatic spray deposition etc. have some limitations–long production time, high energy consumption and great difficulties in controlling the sheet geometry, for instance. In this contribution, graphene sheets were fabricated by a wet-spinning method of graphene oxide (GO) solution followed by chemical reduction of GO to reduced graphene oxide (rGO). The wet-spinning method was able to produce graphene sheets in a high rate (~1.2m/min) and in different dimensions. Here sheets with different thickness (8µm and 16µm) are demonstrated. A series of characterizations are performed for the produced GO and rGO sheets including their Raman and infrared spectra, X-ray diffraction pattern, scanning microscopic pictures and atomic force microscopic pictures. These data show that the reduction is sufficient and the GO sheets are piled up parallel during the wet-spinning process, which is beneficial for the lateral heat transport. The rGO has an in-plane electrical conductivity ca. 6848.41 S/m and thermal conductivity ca. 1024.86 W m-1K-1. In addition, the film displayed excellent heat dissipation performance when attached on top of a light emitting diode (LED) light strip. The research results indicate our approach is facile and capable of fabricating scalable and controllable heat spreader materials with high performance.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"1762-1767"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80883228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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